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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pc.h" | |
26 | #include "fdc.h" | |
27 | #include "pci.h" | |
28 | #include "block.h" | |
29 | #include "sysemu.h" | |
30 | #include "audio/audio.h" | |
31 | #include "net.h" | |
32 | #include "smbus.h" | |
33 | #include "boards.h" | |
cfa2af1f | 34 | #include "console.h" |
3cce6243 | 35 | #include "fw_cfg.h" |
6e02c38d | 36 | #include "virtio-blk.h" |
bd322087 | 37 | #include "virtio-balloon.h" |
16b29ae1 | 38 | #include "hpet_emul.h" |
80cabfad | 39 | |
b41a2cd1 FB |
40 | /* output Bochs bios info messages */ |
41 | //#define DEBUG_BIOS | |
42 | ||
80cabfad FB |
43 | #define BIOS_FILENAME "bios.bin" |
44 | #define VGABIOS_FILENAME "vgabios.bin" | |
de9258a8 | 45 | #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
80cabfad | 46 | |
7fb4fdcf AZ |
47 | #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
48 | ||
a80274c3 PB |
49 | /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ |
50 | #define ACPI_DATA_SIZE 0x10000 | |
3cce6243 | 51 | #define BIOS_CFG_IOPORT 0x510 |
80cabfad | 52 | |
e4bcb14c TS |
53 | #define MAX_IDE_BUS 2 |
54 | ||
baca51fa | 55 | static fdctrl_t *floppy_controller; |
b0a21b53 | 56 | static RTCState *rtc_state; |
ec844b96 | 57 | static PITState *pit; |
d592d303 | 58 | static IOAPICState *ioapic; |
a5954d5c | 59 | static PCIDevice *i440fx_state; |
80cabfad | 60 | |
b41a2cd1 | 61 | static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad FB |
62 | { |
63 | } | |
64 | ||
f929aad6 | 65 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 66 | static qemu_irq ferr_irq; |
f929aad6 FB |
67 | /* XXX: add IGNNE support */ |
68 | void cpu_set_ferr(CPUX86State *s) | |
69 | { | |
d537cf6c | 70 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
71 | } |
72 | ||
73 | static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) | |
74 | { | |
d537cf6c | 75 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
76 | } |
77 | ||
28ab0e2e | 78 | /* TSC handling */ |
28ab0e2e FB |
79 | uint64_t cpu_get_tsc(CPUX86State *env) |
80 | { | |
1dce7c3c FB |
81 | /* Note: when using kqemu, it is more logical to return the host TSC |
82 | because kqemu does not trap the RDTSC instruction for | |
83 | performance reasons */ | |
eb38c52c | 84 | #ifdef USE_KQEMU |
1dce7c3c FB |
85 | if (env->kqemu_enabled) { |
86 | return cpu_get_real_ticks(); | |
5fafdf24 | 87 | } else |
1dce7c3c FB |
88 | #endif |
89 | { | |
90 | return cpu_get_ticks(); | |
91 | } | |
28ab0e2e FB |
92 | } |
93 | ||
a5954d5c FB |
94 | /* SMM support */ |
95 | void cpu_smm_update(CPUState *env) | |
96 | { | |
97 | if (i440fx_state && env == first_cpu) | |
98 | i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); | |
99 | } | |
100 | ||
101 | ||
3de388f6 FB |
102 | /* IRQ handling */ |
103 | int cpu_get_pic_interrupt(CPUState *env) | |
104 | { | |
105 | int intno; | |
106 | ||
3de388f6 FB |
107 | intno = apic_get_interrupt(env); |
108 | if (intno >= 0) { | |
109 | /* set irq request if a PIC irq is still pending */ | |
110 | /* XXX: improve that */ | |
5fafdf24 | 111 | pic_update_irq(isa_pic); |
3de388f6 FB |
112 | return intno; |
113 | } | |
3de388f6 | 114 | /* read the irq from the PIC */ |
0e21e12b TS |
115 | if (!apic_accept_pic_intr(env)) |
116 | return -1; | |
117 | ||
3de388f6 FB |
118 | intno = pic_read_irq(isa_pic); |
119 | return intno; | |
120 | } | |
121 | ||
d537cf6c | 122 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 123 | { |
a5b38b51 AJ |
124 | CPUState *env = first_cpu; |
125 | ||
d5529471 AJ |
126 | if (env->apic_state) { |
127 | while (env) { | |
128 | if (apic_accept_pic_intr(env)) | |
1a7de94a | 129 | apic_deliver_pic_intr(env, level); |
d5529471 AJ |
130 | env = env->next_cpu; |
131 | } | |
132 | } else { | |
b614106a AJ |
133 | if (level) |
134 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
135 | else | |
136 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
a5b38b51 | 137 | } |
3de388f6 FB |
138 | } |
139 | ||
b0a21b53 FB |
140 | /* PC cmos mappings */ |
141 | ||
80cabfad FB |
142 | #define REG_EQUIPMENT_BYTE 0x14 |
143 | ||
777428f2 FB |
144 | static int cmos_get_fd_drive_type(int fd0) |
145 | { | |
146 | int val; | |
147 | ||
148 | switch (fd0) { | |
149 | case 0: | |
150 | /* 1.44 Mb 3"5 drive */ | |
151 | val = 4; | |
152 | break; | |
153 | case 1: | |
154 | /* 2.88 Mb 3"5 drive */ | |
155 | val = 5; | |
156 | break; | |
157 | case 2: | |
158 | /* 1.2 Mb 5"5 drive */ | |
159 | val = 2; | |
160 | break; | |
161 | default: | |
162 | val = 0; | |
163 | break; | |
164 | } | |
165 | return val; | |
166 | } | |
167 | ||
5fafdf24 | 168 | static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
ba6c2377 FB |
169 | { |
170 | RTCState *s = rtc_state; | |
171 | int cylinders, heads, sectors; | |
172 | bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); | |
173 | rtc_set_memory(s, type_ofs, 47); | |
174 | rtc_set_memory(s, info_ofs, cylinders); | |
175 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
176 | rtc_set_memory(s, info_ofs + 2, heads); | |
177 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
178 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
179 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
180 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
181 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
182 | rtc_set_memory(s, info_ofs + 8, sectors); | |
183 | } | |
184 | ||
6ac0e82d AZ |
185 | /* convert boot_device letter to something recognizable by the bios */ |
186 | static int boot_device2nibble(char boot_device) | |
187 | { | |
188 | switch(boot_device) { | |
189 | case 'a': | |
190 | case 'b': | |
191 | return 0x01; /* floppy boot */ | |
192 | case 'c': | |
193 | return 0x02; /* hard drive boot */ | |
194 | case 'd': | |
195 | return 0x03; /* CD-ROM boot */ | |
196 | case 'n': | |
197 | return 0x04; /* Network boot */ | |
198 | } | |
199 | return 0; | |
200 | } | |
201 | ||
0ecdffbb AJ |
202 | /* copy/pasted from cmos_init, should be made a general function |
203 | and used there as well */ | |
3b4366de | 204 | static int pc_boot_set(void *opaque, const char *boot_device) |
0ecdffbb AJ |
205 | { |
206 | #define PC_MAX_BOOT_DEVICES 3 | |
3b4366de | 207 | RTCState *s = (RTCState *)opaque; |
0ecdffbb AJ |
208 | int nbds, bds[3] = { 0, }; |
209 | int i; | |
210 | ||
211 | nbds = strlen(boot_device); | |
212 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
213 | term_printf("Too many boot devices for PC\n"); | |
214 | return(1); | |
215 | } | |
216 | for (i = 0; i < nbds; i++) { | |
217 | bds[i] = boot_device2nibble(boot_device[i]); | |
218 | if (bds[i] == 0) { | |
219 | term_printf("Invalid boot device for PC: '%c'\n", | |
220 | boot_device[i]); | |
221 | return(1); | |
222 | } | |
223 | } | |
224 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
225 | rtc_set_memory(s, 0x38, (bds[2] << 4)); | |
226 | return(0); | |
227 | } | |
228 | ||
ba6c2377 | 229 | /* hd_table must contain 4 block drivers */ |
00f82b8a AJ |
230 | static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
231 | const char *boot_device, BlockDriverState **hd_table) | |
80cabfad | 232 | { |
b0a21b53 | 233 | RTCState *s = rtc_state; |
28c5af54 | 234 | int nbds, bds[3] = { 0, }; |
80cabfad | 235 | int val; |
b41a2cd1 | 236 | int fd0, fd1, nb; |
ba6c2377 | 237 | int i; |
b0a21b53 | 238 | |
b0a21b53 | 239 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
240 | |
241 | /* memory size */ | |
333190eb FB |
242 | val = 640; /* base memory in K */ |
243 | rtc_set_memory(s, 0x15, val); | |
244 | rtc_set_memory(s, 0x16, val >> 8); | |
245 | ||
80cabfad FB |
246 | val = (ram_size / 1024) - 1024; |
247 | if (val > 65535) | |
248 | val = 65535; | |
b0a21b53 FB |
249 | rtc_set_memory(s, 0x17, val); |
250 | rtc_set_memory(s, 0x18, val >> 8); | |
251 | rtc_set_memory(s, 0x30, val); | |
252 | rtc_set_memory(s, 0x31, val >> 8); | |
80cabfad | 253 | |
00f82b8a AJ |
254 | if (above_4g_mem_size) { |
255 | rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); | |
256 | rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); | |
257 | rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); | |
258 | } | |
259 | ||
9da98861 FB |
260 | if (ram_size > (16 * 1024 * 1024)) |
261 | val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); | |
262 | else | |
263 | val = 0; | |
80cabfad FB |
264 | if (val > 65535) |
265 | val = 65535; | |
b0a21b53 FB |
266 | rtc_set_memory(s, 0x34, val); |
267 | rtc_set_memory(s, 0x35, val >> 8); | |
3b46e624 | 268 | |
298e01b6 AJ |
269 | /* set the number of CPU */ |
270 | rtc_set_memory(s, 0x5f, smp_cpus - 1); | |
271 | ||
6ac0e82d | 272 | /* set boot devices, and disable floppy signature check if requested */ |
28c5af54 JM |
273 | #define PC_MAX_BOOT_DEVICES 3 |
274 | nbds = strlen(boot_device); | |
275 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
276 | fprintf(stderr, "Too many boot devices for PC\n"); | |
277 | exit(1); | |
278 | } | |
279 | for (i = 0; i < nbds; i++) { | |
280 | bds[i] = boot_device2nibble(boot_device[i]); | |
281 | if (bds[i] == 0) { | |
282 | fprintf(stderr, "Invalid boot device for PC: '%c'\n", | |
283 | boot_device[i]); | |
284 | exit(1); | |
285 | } | |
286 | } | |
287 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
288 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); | |
80cabfad | 289 | |
b41a2cd1 FB |
290 | /* floppy type */ |
291 | ||
baca51fa FB |
292 | fd0 = fdctrl_get_drive_type(floppy_controller, 0); |
293 | fd1 = fdctrl_get_drive_type(floppy_controller, 1); | |
80cabfad | 294 | |
777428f2 | 295 | val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1); |
b0a21b53 | 296 | rtc_set_memory(s, 0x10, val); |
3b46e624 | 297 | |
b0a21b53 | 298 | val = 0; |
b41a2cd1 | 299 | nb = 0; |
80cabfad FB |
300 | if (fd0 < 3) |
301 | nb++; | |
302 | if (fd1 < 3) | |
303 | nb++; | |
304 | switch (nb) { | |
305 | case 0: | |
306 | break; | |
307 | case 1: | |
b0a21b53 | 308 | val |= 0x01; /* 1 drive, ready for boot */ |
80cabfad FB |
309 | break; |
310 | case 2: | |
b0a21b53 | 311 | val |= 0x41; /* 2 drives, ready for boot */ |
80cabfad FB |
312 | break; |
313 | } | |
b0a21b53 FB |
314 | val |= 0x02; /* FPU is there */ |
315 | val |= 0x04; /* PS/2 mouse installed */ | |
316 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
317 | ||
ba6c2377 FB |
318 | /* hard drives */ |
319 | ||
320 | rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); | |
321 | if (hd_table[0]) | |
322 | cmos_init_hd(0x19, 0x1b, hd_table[0]); | |
5fafdf24 | 323 | if (hd_table[1]) |
ba6c2377 FB |
324 | cmos_init_hd(0x1a, 0x24, hd_table[1]); |
325 | ||
326 | val = 0; | |
40b6ecc6 | 327 | for (i = 0; i < 4; i++) { |
ba6c2377 | 328 | if (hd_table[i]) { |
46d4767d FB |
329 | int cylinders, heads, sectors, translation; |
330 | /* NOTE: bdrv_get_geometry_hint() returns the physical | |
331 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
332 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
333 | geometry can be different if a translation is done. */ | |
334 | translation = bdrv_get_translation_hint(hd_table[i]); | |
335 | if (translation == BIOS_ATA_TRANSLATION_AUTO) { | |
336 | bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); | |
337 | if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { | |
338 | /* No translation. */ | |
339 | translation = 0; | |
340 | } else { | |
341 | /* LBA translation. */ | |
342 | translation = 1; | |
343 | } | |
40b6ecc6 | 344 | } else { |
46d4767d | 345 | translation--; |
ba6c2377 | 346 | } |
ba6c2377 FB |
347 | val |= translation << (i * 2); |
348 | } | |
40b6ecc6 | 349 | } |
ba6c2377 | 350 | rtc_set_memory(s, 0x39, val); |
80cabfad FB |
351 | } |
352 | ||
59b8ad81 FB |
353 | void ioport_set_a20(int enable) |
354 | { | |
355 | /* XXX: send to all CPUs ? */ | |
356 | cpu_x86_set_a20(first_cpu, enable); | |
357 | } | |
358 | ||
359 | int ioport_get_a20(void) | |
360 | { | |
361 | return ((first_cpu->a20_mask >> 20) & 1); | |
362 | } | |
363 | ||
e1a23744 FB |
364 | static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
365 | { | |
59b8ad81 | 366 | ioport_set_a20((val >> 1) & 1); |
e1a23744 FB |
367 | /* XXX: bit 0 is fast reset */ |
368 | } | |
369 | ||
370 | static uint32_t ioport92_read(void *opaque, uint32_t addr) | |
371 | { | |
59b8ad81 | 372 | return ioport_get_a20() << 1; |
e1a23744 FB |
373 | } |
374 | ||
80cabfad FB |
375 | /***********************************************************/ |
376 | /* Bochs BIOS debug ports */ | |
377 | ||
9596ebb7 | 378 | static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
80cabfad | 379 | { |
a2f659ee FB |
380 | static const char shutdown_str[8] = "Shutdown"; |
381 | static int shutdown_index = 0; | |
3b46e624 | 382 | |
80cabfad FB |
383 | switch(addr) { |
384 | /* Bochs BIOS messages */ | |
385 | case 0x400: | |
386 | case 0x401: | |
387 | fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val); | |
388 | exit(1); | |
389 | case 0x402: | |
390 | case 0x403: | |
391 | #ifdef DEBUG_BIOS | |
392 | fprintf(stderr, "%c", val); | |
393 | #endif | |
394 | break; | |
a2f659ee FB |
395 | case 0x8900: |
396 | /* same as Bochs power off */ | |
397 | if (val == shutdown_str[shutdown_index]) { | |
398 | shutdown_index++; | |
399 | if (shutdown_index == 8) { | |
400 | shutdown_index = 0; | |
401 | qemu_system_shutdown_request(); | |
402 | } | |
403 | } else { | |
404 | shutdown_index = 0; | |
405 | } | |
406 | break; | |
80cabfad FB |
407 | |
408 | /* LGPL'ed VGA BIOS messages */ | |
409 | case 0x501: | |
410 | case 0x502: | |
411 | fprintf(stderr, "VGA BIOS panic, line %d\n", val); | |
412 | exit(1); | |
413 | case 0x500: | |
414 | case 0x503: | |
415 | #ifdef DEBUG_BIOS | |
416 | fprintf(stderr, "%c", val); | |
417 | #endif | |
418 | break; | |
419 | } | |
420 | } | |
421 | ||
9596ebb7 | 422 | static void bochs_bios_init(void) |
80cabfad | 423 | { |
3cce6243 BS |
424 | void *fw_cfg; |
425 | ||
b41a2cd1 FB |
426 | register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
427 | register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); | |
428 | register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); | |
429 | register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); | |
a2f659ee | 430 | register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
b41a2cd1 FB |
431 | |
432 | register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); | |
433 | register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); | |
434 | register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); | |
435 | register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); | |
3cce6243 BS |
436 | |
437 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); | |
438 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 | 439 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
80cabfad FB |
440 | } |
441 | ||
642a4f96 TS |
442 | /* Generate an initial boot sector which sets state and jump to |
443 | a specified vector */ | |
4fc9af53 AL |
444 | static void generate_bootsect(uint8_t *option_rom, |
445 | uint32_t gpr[8], uint16_t segs[6], uint16_t ip) | |
642a4f96 | 446 | { |
4fc9af53 AL |
447 | uint8_t rom[512], *p, *reloc; |
448 | uint8_t sum; | |
642a4f96 TS |
449 | int i; |
450 | ||
4fc9af53 AL |
451 | memset(rom, 0, sizeof(rom)); |
452 | ||
453 | p = rom; | |
454 | /* Make sure we have an option rom signature */ | |
455 | *p++ = 0x55; | |
456 | *p++ = 0xaa; | |
642a4f96 | 457 | |
4fc9af53 AL |
458 | /* ROM size in sectors*/ |
459 | *p++ = 1; | |
642a4f96 | 460 | |
4fc9af53 | 461 | /* Hook int19 */ |
642a4f96 | 462 | |
4fc9af53 AL |
463 | *p++ = 0x50; /* push ax */ |
464 | *p++ = 0x1e; /* push ds */ | |
465 | *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ | |
466 | *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ | |
642a4f96 | 467 | |
4fc9af53 AL |
468 | *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
469 | *p++ = 0x64; *p++ = 0x00; | |
470 | reloc = p; | |
471 | *p++ = 0x00; *p++ = 0x00; | |
472 | ||
473 | *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ | |
474 | *p++ = 0x66; *p++ = 0x00; | |
475 | ||
476 | *p++ = 0x1f; /* pop ds */ | |
477 | *p++ = 0x58; /* pop ax */ | |
478 | *p++ = 0xcb; /* lret */ | |
479 | ||
642a4f96 | 480 | /* Actual code */ |
4fc9af53 AL |
481 | *reloc = (p - rom); |
482 | ||
642a4f96 TS |
483 | *p++ = 0xfa; /* CLI */ |
484 | *p++ = 0xfc; /* CLD */ | |
485 | ||
486 | for (i = 0; i < 6; i++) { | |
487 | if (i == 1) /* Skip CS */ | |
488 | continue; | |
489 | ||
490 | *p++ = 0xb8; /* MOV AX,imm16 */ | |
491 | *p++ = segs[i]; | |
492 | *p++ = segs[i] >> 8; | |
493 | *p++ = 0x8e; /* MOV <seg>,AX */ | |
494 | *p++ = 0xc0 + (i << 3); | |
495 | } | |
496 | ||
497 | for (i = 0; i < 8; i++) { | |
498 | *p++ = 0x66; /* 32-bit operand size */ | |
499 | *p++ = 0xb8 + i; /* MOV <reg>,imm32 */ | |
500 | *p++ = gpr[i]; | |
501 | *p++ = gpr[i] >> 8; | |
502 | *p++ = gpr[i] >> 16; | |
503 | *p++ = gpr[i] >> 24; | |
504 | } | |
505 | ||
506 | *p++ = 0xea; /* JMP FAR */ | |
507 | *p++ = ip; /* IP */ | |
508 | *p++ = ip >> 8; | |
509 | *p++ = segs[1]; /* CS */ | |
510 | *p++ = segs[1] >> 8; | |
511 | ||
4fc9af53 AL |
512 | /* sign rom */ |
513 | sum = 0; | |
514 | for (i = 0; i < (sizeof(rom) - 1); i++) | |
515 | sum += rom[i]; | |
516 | rom[sizeof(rom) - 1] = -sum; | |
517 | ||
518 | memcpy(option_rom, rom, sizeof(rom)); | |
642a4f96 | 519 | } |
80cabfad | 520 | |
642a4f96 TS |
521 | static long get_file_size(FILE *f) |
522 | { | |
523 | long where, size; | |
524 | ||
525 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
526 | ||
527 | where = ftell(f); | |
528 | fseek(f, 0, SEEK_END); | |
529 | size = ftell(f); | |
530 | fseek(f, where, SEEK_SET); | |
531 | ||
532 | return size; | |
533 | } | |
534 | ||
4fc9af53 AL |
535 | static void load_linux(uint8_t *option_rom, |
536 | const char *kernel_filename, | |
642a4f96 TS |
537 | const char *initrd_filename, |
538 | const char *kernel_cmdline) | |
539 | { | |
540 | uint16_t protocol; | |
541 | uint32_t gpr[8]; | |
542 | uint16_t seg[6]; | |
543 | uint16_t real_seg; | |
544 | int setup_size, kernel_size, initrd_size, cmdline_size; | |
545 | uint32_t initrd_max; | |
546 | uint8_t header[1024]; | |
a37af289 | 547 | target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr; |
642a4f96 TS |
548 | FILE *f, *fi; |
549 | ||
550 | /* Align to 16 bytes as a paranoia measure */ | |
551 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
552 | ||
553 | /* load the kernel header */ | |
554 | f = fopen(kernel_filename, "rb"); | |
555 | if (!f || !(kernel_size = get_file_size(f)) || | |
556 | fread(header, 1, 1024, f) != 1024) { | |
557 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
558 | kernel_filename); | |
559 | exit(1); | |
560 | } | |
561 | ||
562 | /* kernel protocol version */ | |
bc4edd79 | 563 | #if 0 |
642a4f96 | 564 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 565 | #endif |
642a4f96 TS |
566 | if (ldl_p(header+0x202) == 0x53726448) |
567 | protocol = lduw_p(header+0x206); | |
568 | else | |
569 | protocol = 0; | |
570 | ||
571 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
572 | /* Low kernel */ | |
a37af289 BS |
573 | real_addr = 0x90000; |
574 | cmdline_addr = 0x9a000 - cmdline_size; | |
575 | prot_addr = 0x10000; | |
642a4f96 TS |
576 | } else if (protocol < 0x202) { |
577 | /* High but ancient kernel */ | |
a37af289 BS |
578 | real_addr = 0x90000; |
579 | cmdline_addr = 0x9a000 - cmdline_size; | |
580 | prot_addr = 0x100000; | |
642a4f96 TS |
581 | } else { |
582 | /* High and recent kernel */ | |
a37af289 BS |
583 | real_addr = 0x10000; |
584 | cmdline_addr = 0x20000; | |
585 | prot_addr = 0x100000; | |
642a4f96 TS |
586 | } |
587 | ||
bc4edd79 | 588 | #if 0 |
642a4f96 | 589 | fprintf(stderr, |
526ccb7a AZ |
590 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
591 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
592 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
a37af289 BS |
593 | real_addr, |
594 | cmdline_addr, | |
595 | prot_addr); | |
bc4edd79 | 596 | #endif |
642a4f96 TS |
597 | |
598 | /* highest address for loading the initrd */ | |
599 | if (protocol >= 0x203) | |
600 | initrd_max = ldl_p(header+0x22c); | |
601 | else | |
602 | initrd_max = 0x37ffffff; | |
603 | ||
604 | if (initrd_max >= ram_size-ACPI_DATA_SIZE) | |
605 | initrd_max = ram_size-ACPI_DATA_SIZE-1; | |
606 | ||
607 | /* kernel command line */ | |
a37af289 | 608 | pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline); |
642a4f96 TS |
609 | |
610 | if (protocol >= 0x202) { | |
a37af289 | 611 | stl_p(header+0x228, cmdline_addr); |
642a4f96 TS |
612 | } else { |
613 | stw_p(header+0x20, 0xA33F); | |
614 | stw_p(header+0x22, cmdline_addr-real_addr); | |
615 | } | |
616 | ||
617 | /* loader type */ | |
618 | /* High nybble = B reserved for Qemu; low nybble is revision number. | |
619 | If this code is substantially changed, you may want to consider | |
620 | incrementing the revision. */ | |
621 | if (protocol >= 0x200) | |
622 | header[0x210] = 0xB0; | |
623 | ||
624 | /* heap */ | |
625 | if (protocol >= 0x201) { | |
626 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ | |
627 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
628 | } | |
629 | ||
630 | /* load initrd */ | |
631 | if (initrd_filename) { | |
632 | if (protocol < 0x200) { | |
633 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
634 | exit(1); | |
635 | } | |
636 | ||
637 | fi = fopen(initrd_filename, "rb"); | |
638 | if (!fi) { | |
639 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
640 | initrd_filename); | |
641 | exit(1); | |
642 | } | |
643 | ||
644 | initrd_size = get_file_size(fi); | |
a37af289 | 645 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
642a4f96 | 646 | |
526ccb7a AZ |
647 | fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx |
648 | "\n", initrd_size, initrd_addr); | |
642a4f96 | 649 | |
a37af289 | 650 | if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) { |
642a4f96 TS |
651 | fprintf(stderr, "qemu: read error on initial ram disk '%s'\n", |
652 | initrd_filename); | |
653 | exit(1); | |
654 | } | |
655 | fclose(fi); | |
656 | ||
a37af289 | 657 | stl_p(header+0x218, initrd_addr); |
642a4f96 TS |
658 | stl_p(header+0x21c, initrd_size); |
659 | } | |
660 | ||
661 | /* store the finalized header and load the rest of the kernel */ | |
a37af289 | 662 | cpu_physical_memory_write(real_addr, header, 1024); |
642a4f96 TS |
663 | |
664 | setup_size = header[0x1f1]; | |
665 | if (setup_size == 0) | |
666 | setup_size = 4; | |
667 | ||
668 | setup_size = (setup_size+1)*512; | |
669 | kernel_size -= setup_size; /* Size of protected-mode code */ | |
670 | ||
a37af289 BS |
671 | if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) || |
672 | !fread_targphys_ok(prot_addr, kernel_size, f)) { | |
642a4f96 TS |
673 | fprintf(stderr, "qemu: read error on kernel '%s'\n", |
674 | kernel_filename); | |
675 | exit(1); | |
676 | } | |
677 | fclose(f); | |
678 | ||
679 | /* generate bootsector to set up the initial register state */ | |
a37af289 | 680 | real_seg = real_addr >> 4; |
642a4f96 TS |
681 | seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
682 | seg[1] = real_seg+0x20; /* CS */ | |
683 | memset(gpr, 0, sizeof gpr); | |
684 | gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ | |
685 | ||
4fc9af53 | 686 | generate_bootsect(option_rom, gpr, seg, 0); |
642a4f96 TS |
687 | } |
688 | ||
59b8ad81 FB |
689 | static void main_cpu_reset(void *opaque) |
690 | { | |
691 | CPUState *env = opaque; | |
692 | cpu_reset(env); | |
693 | } | |
694 | ||
b41a2cd1 FB |
695 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
696 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
697 | static const int ide_irq[2] = { 14, 15 }; | |
698 | ||
699 | #define NE2000_NB_MAX 6 | |
700 | ||
8d11df9e | 701 | static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
b41a2cd1 FB |
702 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
703 | ||
8d11df9e FB |
704 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
705 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
706 | ||
6508fe59 FB |
707 | static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
708 | static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
709 | ||
6a36d84e | 710 | #ifdef HAS_AUDIO |
d537cf6c | 711 | static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
6a36d84e FB |
712 | { |
713 | struct soundhw *c; | |
714 | int audio_enabled = 0; | |
715 | ||
716 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
717 | audio_enabled = c->enabled; | |
718 | } | |
719 | ||
720 | if (audio_enabled) { | |
721 | AudioState *s; | |
722 | ||
723 | s = AUD_init (); | |
724 | if (s) { | |
725 | for (c = soundhw; c->name; ++c) { | |
726 | if (c->enabled) { | |
727 | if (c->isa) { | |
d537cf6c | 728 | c->init.init_isa (s, pic); |
6a36d84e FB |
729 | } |
730 | else { | |
731 | if (pci_bus) { | |
732 | c->init.init_pci (pci_bus, s); | |
733 | } | |
734 | } | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | #endif | |
741 | ||
d537cf6c | 742 | static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
a41b2ff2 PB |
743 | { |
744 | static int nb_ne2k = 0; | |
745 | ||
746 | if (nb_ne2k == NE2000_NB_MAX) | |
747 | return; | |
d537cf6c | 748 | isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
a41b2ff2 PB |
749 | nb_ne2k++; |
750 | } | |
751 | ||
80cabfad | 752 | /* PC hardware initialisation */ |
00f82b8a | 753 | static void pc_init1(ram_addr_t ram_size, int vga_ram_size, |
b881c2c6 | 754 | const char *boot_device, DisplayState *ds, |
b5ff2d6e | 755 | const char *kernel_filename, const char *kernel_cmdline, |
3dbbdc25 | 756 | const char *initrd_filename, |
a049de61 | 757 | int pci_enabled, const char *cpu_model) |
80cabfad FB |
758 | { |
759 | char buf[1024]; | |
642a4f96 | 760 | int ret, linux_boot, i; |
970ac5a3 | 761 | ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset; |
00f82b8a | 762 | ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; |
970ac5a3 | 763 | int bios_size, isa_bios_size, vga_bios_size; |
46e50e9d | 764 | PCIBus *pci_bus; |
5c3ff3a7 | 765 | int piix3_devfn = -1; |
59b8ad81 | 766 | CPUState *env; |
d537cf6c PB |
767 | qemu_irq *cpu_irq; |
768 | qemu_irq *i8259; | |
e4bcb14c TS |
769 | int index; |
770 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; | |
771 | BlockDriverState *fd[MAX_FD]; | |
d592d303 | 772 | |
00f82b8a AJ |
773 | if (ram_size >= 0xe0000000 ) { |
774 | above_4g_mem_size = ram_size - 0xe0000000; | |
775 | below_4g_mem_size = 0xe0000000; | |
776 | } else { | |
777 | below_4g_mem_size = ram_size; | |
778 | } | |
779 | ||
80cabfad FB |
780 | linux_boot = (kernel_filename != NULL); |
781 | ||
59b8ad81 | 782 | /* init CPUs */ |
a049de61 FB |
783 | if (cpu_model == NULL) { |
784 | #ifdef TARGET_X86_64 | |
785 | cpu_model = "qemu64"; | |
786 | #else | |
787 | cpu_model = "qemu32"; | |
788 | #endif | |
789 | } | |
790 | ||
59b8ad81 | 791 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
792 | env = cpu_init(cpu_model); |
793 | if (!env) { | |
794 | fprintf(stderr, "Unable to find x86 CPU definition\n"); | |
795 | exit(1); | |
796 | } | |
59b8ad81 | 797 | if (i != 0) |
ce5232c5 | 798 | env->halted = 1; |
59b8ad81 FB |
799 | if (smp_cpus > 1) { |
800 | /* XXX: enable it in all cases */ | |
801 | env->cpuid_features |= CPUID_APIC; | |
802 | } | |
59b8ad81 FB |
803 | qemu_register_reset(main_cpu_reset, env); |
804 | if (pci_enabled) { | |
805 | apic_init(env); | |
806 | } | |
807 | } | |
808 | ||
26fb5e48 AJ |
809 | vmport_init(); |
810 | ||
80cabfad | 811 | /* allocate RAM */ |
82b36dc3 AL |
812 | ram_addr = qemu_ram_alloc(0xa0000); |
813 | cpu_register_physical_memory(0, 0xa0000, ram_addr); | |
814 | ||
815 | /* Allocate, even though we won't register, so we don't break the | |
816 | * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), | |
817 | * and some bios areas, which will be registered later | |
818 | */ | |
819 | ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); | |
820 | ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); | |
821 | cpu_register_physical_memory(0x100000, | |
822 | below_4g_mem_size - 0x100000, | |
823 | ram_addr); | |
00f82b8a AJ |
824 | |
825 | /* above 4giga memory allocation */ | |
826 | if (above_4g_mem_size > 0) { | |
82b36dc3 AL |
827 | ram_addr = qemu_ram_alloc(above_4g_mem_size); |
828 | cpu_register_physical_memory(0x100000000ULL, | |
526ccb7a | 829 | above_4g_mem_size, |
82b36dc3 | 830 | ram_addr); |
00f82b8a | 831 | } |
80cabfad | 832 | |
82b36dc3 | 833 | |
970ac5a3 FB |
834 | /* allocate VGA RAM */ |
835 | vga_ram_addr = qemu_ram_alloc(vga_ram_size); | |
7587cf44 | 836 | |
970ac5a3 | 837 | /* BIOS load */ |
1192dad8 JM |
838 | if (bios_name == NULL) |
839 | bios_name = BIOS_FILENAME; | |
840 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
7587cf44 | 841 | bios_size = get_image_size(buf); |
5fafdf24 | 842 | if (bios_size <= 0 || |
970ac5a3 | 843 | (bios_size % 65536) != 0) { |
7587cf44 FB |
844 | goto bios_error; |
845 | } | |
970ac5a3 | 846 | bios_offset = qemu_ram_alloc(bios_size); |
7587cf44 FB |
847 | ret = load_image(buf, phys_ram_base + bios_offset); |
848 | if (ret != bios_size) { | |
849 | bios_error: | |
970ac5a3 | 850 | fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf); |
80cabfad FB |
851 | exit(1); |
852 | } | |
7587cf44 | 853 | |
80cabfad | 854 | /* VGA BIOS load */ |
de9258a8 FB |
855 | if (cirrus_vga_enabled) { |
856 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME); | |
857 | } else { | |
858 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); | |
859 | } | |
970ac5a3 | 860 | vga_bios_size = get_image_size(buf); |
5fafdf24 | 861 | if (vga_bios_size <= 0 || vga_bios_size > 65536) |
970ac5a3 FB |
862 | goto vga_bios_error; |
863 | vga_bios_offset = qemu_ram_alloc(65536); | |
864 | ||
7587cf44 | 865 | ret = load_image(buf, phys_ram_base + vga_bios_offset); |
970ac5a3 FB |
866 | if (ret != vga_bios_size) { |
867 | vga_bios_error: | |
868 | fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf); | |
869 | exit(1); | |
870 | } | |
871 | ||
80cabfad | 872 | /* setup basic memory access */ |
5fafdf24 | 873 | cpu_register_physical_memory(0xc0000, 0x10000, |
7587cf44 FB |
874 | vga_bios_offset | IO_MEM_ROM); |
875 | ||
876 | /* map the last 128KB of the BIOS in ISA space */ | |
877 | isa_bios_size = bios_size; | |
878 | if (isa_bios_size > (128 * 1024)) | |
879 | isa_bios_size = 128 * 1024; | |
5fafdf24 TS |
880 | cpu_register_physical_memory(0x100000 - isa_bios_size, |
881 | isa_bios_size, | |
7587cf44 | 882 | (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
9ae02555 | 883 | |
970ac5a3 FB |
884 | { |
885 | ram_addr_t option_rom_offset; | |
886 | int size, offset; | |
887 | ||
888 | offset = 0; | |
4fc9af53 AL |
889 | if (linux_boot) { |
890 | option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE); | |
891 | load_linux(phys_ram_base + option_rom_offset, | |
892 | kernel_filename, initrd_filename, kernel_cmdline); | |
893 | cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE, | |
894 | option_rom_offset | IO_MEM_ROM); | |
895 | offset = TARGET_PAGE_SIZE; | |
896 | } | |
897 | ||
970ac5a3 FB |
898 | for (i = 0; i < nb_option_roms; i++) { |
899 | size = get_image_size(option_rom[i]); | |
900 | if (size < 0) { | |
5fafdf24 | 901 | fprintf(stderr, "Could not load option rom '%s'\n", |
970ac5a3 FB |
902 | option_rom[i]); |
903 | exit(1); | |
904 | } | |
905 | if (size > (0x10000 - offset)) | |
906 | goto option_rom_error; | |
907 | option_rom_offset = qemu_ram_alloc(size); | |
908 | ret = load_image(option_rom[i], phys_ram_base + option_rom_offset); | |
909 | if (ret != size) { | |
910 | option_rom_error: | |
911 | fprintf(stderr, "Too many option ROMS\n"); | |
912 | exit(1); | |
913 | } | |
914 | size = (size + 4095) & ~4095; | |
915 | cpu_register_physical_memory(0xd0000 + offset, | |
916 | size, option_rom_offset | IO_MEM_ROM); | |
917 | offset += size; | |
918 | } | |
9ae02555 TS |
919 | } |
920 | ||
7587cf44 | 921 | /* map all the bios at the top of memory */ |
5fafdf24 | 922 | cpu_register_physical_memory((uint32_t)(-bios_size), |
7587cf44 | 923 | bios_size, bios_offset | IO_MEM_ROM); |
3b46e624 | 924 | |
80cabfad FB |
925 | bochs_bios_init(); |
926 | ||
a5b38b51 | 927 | cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
d537cf6c PB |
928 | i8259 = i8259_init(cpu_irq[0]); |
929 | ferr_irq = i8259[13]; | |
930 | ||
69b91039 | 931 | if (pci_enabled) { |
d537cf6c | 932 | pci_bus = i440fx_init(&i440fx_state, i8259); |
8f1c91d8 | 933 | piix3_devfn = piix3_init(pci_bus, -1); |
46e50e9d FB |
934 | } else { |
935 | pci_bus = NULL; | |
69b91039 FB |
936 | } |
937 | ||
80cabfad | 938 | /* init basic PC hardware */ |
b41a2cd1 | 939 | register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
80cabfad | 940 | |
f929aad6 FB |
941 | register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
942 | ||
1f04275e FB |
943 | if (cirrus_vga_enabled) { |
944 | if (pci_enabled) { | |
5fafdf24 TS |
945 | pci_cirrus_vga_init(pci_bus, |
946 | ds, phys_ram_base + vga_ram_addr, | |
970ac5a3 | 947 | vga_ram_addr, vga_ram_size); |
1f04275e | 948 | } else { |
5fafdf24 | 949 | isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 950 | vga_ram_addr, vga_ram_size); |
1f04275e | 951 | } |
d34cab9f TS |
952 | } else if (vmsvga_enabled) { |
953 | if (pci_enabled) | |
45e4522e AZ |
954 | pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
955 | vga_ram_addr, vga_ram_size); | |
d34cab9f TS |
956 | else |
957 | fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); | |
1f04275e | 958 | } else { |
89b6b508 | 959 | if (pci_enabled) { |
5fafdf24 | 960 | pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 961 | vga_ram_addr, vga_ram_size, 0, 0); |
89b6b508 | 962 | } else { |
5fafdf24 | 963 | isa_vga_init(ds, phys_ram_base + vga_ram_addr, |
970ac5a3 | 964 | vga_ram_addr, vga_ram_size); |
89b6b508 | 965 | } |
1f04275e | 966 | } |
80cabfad | 967 | |
d537cf6c | 968 | rtc_state = rtc_init(0x70, i8259[8]); |
80cabfad | 969 | |
3b4366de BS |
970 | qemu_register_boot_set(pc_boot_set, rtc_state); |
971 | ||
e1a23744 FB |
972 | register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
973 | register_ioport_write(0x92, 1, 1, ioport92_write, NULL); | |
974 | ||
d592d303 | 975 | if (pci_enabled) { |
d592d303 FB |
976 | ioapic = ioapic_init(); |
977 | } | |
d537cf6c | 978 | pit = pit_init(0x40, i8259[0]); |
fd06c375 | 979 | pcspk_init(pit); |
16b29ae1 AL |
980 | if (!no_hpet) { |
981 | hpet_init(i8259); | |
982 | } | |
d592d303 FB |
983 | if (pci_enabled) { |
984 | pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); | |
985 | } | |
b41a2cd1 | 986 | |
8d11df9e FB |
987 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
988 | if (serial_hds[i]) { | |
b6cd0ea1 AJ |
989 | serial_init(serial_io[i], i8259[serial_irq[i]], 115200, |
990 | serial_hds[i]); | |
8d11df9e FB |
991 | } |
992 | } | |
b41a2cd1 | 993 | |
6508fe59 FB |
994 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
995 | if (parallel_hds[i]) { | |
d537cf6c PB |
996 | parallel_init(parallel_io[i], i8259[parallel_irq[i]], |
997 | parallel_hds[i]); | |
6508fe59 FB |
998 | } |
999 | } | |
1000 | ||
a41b2ff2 | 1001 | for(i = 0; i < nb_nics; i++) { |
cb457d76 AL |
1002 | NICInfo *nd = &nd_table[i]; |
1003 | ||
1004 | if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) | |
d537cf6c | 1005 | pc_init_ne2k_isa(nd, i8259); |
cb457d76 AL |
1006 | else |
1007 | pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); | |
a41b2ff2 | 1008 | } |
b41a2cd1 | 1009 | |
e4bcb14c TS |
1010 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
1011 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
1012 | exit(1); | |
1013 | } | |
1014 | ||
1015 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
1016 | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); | |
1017 | if (index != -1) | |
1018 | hd[i] = drives_table[index].bdrv; | |
1019 | else | |
1020 | hd[i] = NULL; | |
1021 | } | |
1022 | ||
a41b2ff2 | 1023 | if (pci_enabled) { |
e4bcb14c | 1024 | pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); |
a41b2ff2 | 1025 | } else { |
e4bcb14c | 1026 | for(i = 0; i < MAX_IDE_BUS; i++) { |
d537cf6c | 1027 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
e4bcb14c | 1028 | hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); |
69b91039 | 1029 | } |
b41a2cd1 | 1030 | } |
69b91039 | 1031 | |
d537cf6c | 1032 | i8042_init(i8259[1], i8259[12], 0x60); |
7c29d0c0 | 1033 | DMA_init(0); |
6a36d84e | 1034 | #ifdef HAS_AUDIO |
d537cf6c | 1035 | audio_init(pci_enabled ? pci_bus : NULL, i8259); |
fb065187 | 1036 | #endif |
80cabfad | 1037 | |
e4bcb14c TS |
1038 | for(i = 0; i < MAX_FD; i++) { |
1039 | index = drive_get_index(IF_FLOPPY, 0, i); | |
1040 | if (index != -1) | |
1041 | fd[i] = drives_table[index].bdrv; | |
1042 | else | |
1043 | fd[i] = NULL; | |
1044 | } | |
1045 | floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); | |
b41a2cd1 | 1046 | |
00f82b8a | 1047 | cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
69b91039 | 1048 | |
bb36d470 | 1049 | if (pci_enabled && usb_enabled) { |
afcc3cdf | 1050 | usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); |
bb36d470 FB |
1051 | } |
1052 | ||
6515b203 | 1053 | if (pci_enabled && acpi_enabled) { |
3fffc223 | 1054 | uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
0ff596d0 PB |
1055 | i2c_bus *smbus; |
1056 | ||
1057 | /* TODO: Populate SPD eeprom data. */ | |
cf7a2fe2 | 1058 | smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); |
3fffc223 | 1059 | for (i = 0; i < 8; i++) { |
0ff596d0 | 1060 | smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256)); |
3fffc223 | 1061 | } |
6515b203 | 1062 | } |
3b46e624 | 1063 | |
a5954d5c FB |
1064 | if (i440fx_state) { |
1065 | i440fx_init_memory_mappings(i440fx_state); | |
1066 | } | |
e4bcb14c | 1067 | |
7d8406be | 1068 | if (pci_enabled) { |
e4bcb14c TS |
1069 | int max_bus; |
1070 | int bus, unit; | |
7d8406be | 1071 | void *scsi; |
96d30e48 | 1072 | |
e4bcb14c TS |
1073 | max_bus = drive_get_max_bus(IF_SCSI); |
1074 | ||
1075 | for (bus = 0; bus <= max_bus; bus++) { | |
1076 | scsi = lsi_scsi_init(pci_bus, -1); | |
1077 | for (unit = 0; unit < LSI_MAX_DEVS; unit++) { | |
1078 | index = drive_get_index(IF_SCSI, bus, unit); | |
1079 | if (index == -1) | |
1080 | continue; | |
1081 | lsi_scsi_attach(scsi, drives_table[index].bdrv, unit); | |
1082 | } | |
1083 | } | |
7d8406be | 1084 | } |
6e02c38d AL |
1085 | |
1086 | /* Add virtio block devices */ | |
1087 | if (pci_enabled) { | |
1088 | int index; | |
1089 | int unit_id = 0; | |
1090 | ||
1091 | while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { | |
9b32d5a5 | 1092 | virtio_blk_init(pci_bus, drives_table[index].bdrv); |
6e02c38d AL |
1093 | unit_id++; |
1094 | } | |
1095 | } | |
bd322087 AL |
1096 | |
1097 | /* Add virtio balloon device */ | |
1098 | if (pci_enabled) | |
1099 | virtio_balloon_init(pci_bus); | |
80cabfad | 1100 | } |
b5ff2d6e | 1101 | |
00f82b8a | 1102 | static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size, |
b881c2c6 | 1103 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 1104 | const char *kernel_filename, |
3dbbdc25 | 1105 | const char *kernel_cmdline, |
94fc95cd JM |
1106 | const char *initrd_filename, |
1107 | const char *cpu_model) | |
3dbbdc25 | 1108 | { |
b881c2c6 | 1109 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
3dbbdc25 | 1110 | kernel_filename, kernel_cmdline, |
a049de61 | 1111 | initrd_filename, 1, cpu_model); |
3dbbdc25 FB |
1112 | } |
1113 | ||
00f82b8a | 1114 | static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size, |
b881c2c6 | 1115 | const char *boot_device, DisplayState *ds, |
5fafdf24 | 1116 | const char *kernel_filename, |
3dbbdc25 | 1117 | const char *kernel_cmdline, |
94fc95cd JM |
1118 | const char *initrd_filename, |
1119 | const char *cpu_model) | |
3dbbdc25 | 1120 | { |
b881c2c6 | 1121 | pc_init1(ram_size, vga_ram_size, boot_device, ds, |
3dbbdc25 | 1122 | kernel_filename, kernel_cmdline, |
a049de61 | 1123 | initrd_filename, 0, cpu_model); |
3dbbdc25 FB |
1124 | } |
1125 | ||
0bacd130 AL |
1126 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
1127 | BIOS will read it and start S3 resume at POST Entry */ | |
1128 | void cmos_set_s3_resume(void) | |
1129 | { | |
1130 | if (rtc_state) | |
1131 | rtc_set_memory(rtc_state, 0xF, 0xFE); | |
1132 | } | |
1133 | ||
b5ff2d6e | 1134 | QEMUMachine pc_machine = { |
a245f2e7 AJ |
1135 | .name = "pc", |
1136 | .desc = "Standard PC", | |
1137 | .init = pc_init_pci, | |
1138 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, | |
b2097003 | 1139 | .max_cpus = 255, |
3dbbdc25 FB |
1140 | }; |
1141 | ||
1142 | QEMUMachine isapc_machine = { | |
a245f2e7 AJ |
1143 | .name = "isapc", |
1144 | .desc = "ISA-only PC", | |
1145 | .init = pc_init_isa, | |
1146 | .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE, | |
b2097003 | 1147 | .max_cpus = 1, |
b5ff2d6e | 1148 | }; |