[mirror_qemu.git] / hw / pc.h

#ifndef HW_PC_H
#define HW_PC_H
/* PC-style peripherals (also used by other machines).  */

/* serial.c */

SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
                             qemu_irq irq, CharDriverState *chr,
                             int ioregister);
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);

/* parallel.c */

typedef struct ParallelState ParallelState;
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);

/* i8259.c */

typedef struct PicState2 PicState2;
extern PicState2 *isa_pic;
void pic_set_irq(int irq, int level);
void pic_set_irq_new(void *opaque, int irq, int level);
qemu_irq *i8259_init(qemu_irq parent_irq);
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
                          void *alt_irq_opaque);
int pic_read_irq(PicState2 *s);
void pic_update_irq(PicState2 *s);
uint32_t pic_intack_read(PicState2 *s);
void pic_info(void);
void irq_info(void);

/* APIC */
typedef struct IOAPICState IOAPICState;

#define APIC_LINT0	3

int apic_init(CPUState *env);
int apic_accept_pic_intr(CPUState *env);
void apic_local_deliver(CPUState *env, int vector);
int apic_get_interrupt(CPUState *env);
IOAPICState *ioapic_init(void);
void ioapic_set_irq(void *opaque, int vector, int level);

/* i8254.c */

#define PIT_FREQ 1193182

typedef struct PITState PITState;

PITState *pit_init(int base, qemu_irq irq);
void pit_set_gate(PITState *pit, int channel, int val);
int pit_get_gate(PITState *pit, int channel);
int pit_get_initial_count(PITState *pit, int channel);
int pit_get_mode(PITState *pit, int channel);
int pit_get_out(PITState *pit, int channel, int64_t current_time);

/* vmport.c */
void vmport_init(void);
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);

/* vmmouse.c */
void *vmmouse_init(void *m);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   target_phys_addr_t base, int it_shift);

/* mc146818rtc.c */

typedef struct RTCState RTCState;

RTCState *rtc_init(int base, qemu_irq irq);
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);

/* pc.c */
extern int fd_bootchk;

void ioport_set_a20(int enable);
int ioport_get_a20(void);

/* acpi.c */
extern int acpi_enabled;
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
void acpi_bios_init(void);

/* pcspk.c */
void pcspk_init(PITState *);
int pcspk_audio_init(AudioState *, qemu_irq *pic);

/* piix_pci.c */
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
void i440fx_set_smm(PCIDevice *d, int val);
int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCIDevice *d);

int piix4_init(PCIBus *bus, int devfn);

/* vga.c */

#ifndef TARGET_SPARC
#define VGA_RAM_SIZE (8192 * 1024)
#else
#define VGA_RAM_SIZE (9 * 1024 * 1024)
#endif

int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                 unsigned long vga_ram_offset, int vga_ram_size);
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                 unsigned long vga_ram_offset, int vga_ram_size,
                 unsigned long vga_bios_offset, int vga_bios_size);
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
                    unsigned long vga_ram_offset, int vga_ram_size,
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
                    int it_shift);

/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
                         unsigned long vga_ram_offset, int vga_ram_size);
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
                         unsigned long vga_ram_offset, int vga_ram_size);

/* ide.c */
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
                  BlockDriverState *hd0, BlockDriverState *hd1);
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
                         int secondary_ide_enabled);
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
                        qemu_irq *pic);
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
                        qemu_irq *pic);

/* ne2000.c */

void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
	2	#define HW_PC_H
	3	/* PC-style peripherals (also used by other machines). */
	4
	5	/* serial.c */
	6
	7	SerialState serial_init(int base, qemu_irq irq, CharDriverState chr);
	8	SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
	9	qemu_irq irq, CharDriverState *chr,
	10	int ioregister);
	11	uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
	12	void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
	13	uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
	14	void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
	15	uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
	16	void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
	17
	18	/* parallel.c */
	19
	20	typedef struct ParallelState ParallelState;
	21	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr);
	22	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr);
	23
	24	/* i8259.c */
	25
	26	typedef struct PicState2 PicState2;
	27	extern PicState2 *isa_pic;
	28	void pic_set_irq(int irq, int level);
	29	void pic_set_irq_new(void *opaque, int irq, int level);
	30	qemu_irq *i8259_init(qemu_irq parent_irq);
	31	void pic_set_alt_irq_func(PicState2 s, SetIRQFunc alt_irq_func,
	32	void *alt_irq_opaque);
	33	int pic_read_irq(PicState2 *s);
	34	void pic_update_irq(PicState2 *s);
	35	uint32_t pic_intack_read(PicState2 *s);
	36	void pic_info(void);
	37	void irq_info(void);
	38
	39	/* APIC */
	40	typedef struct IOAPICState IOAPICState;
	41
a5b38b51 AJ	42	#define APIC_LINT0 3
a5b38b51 AJ	43
87ecb68b PB	44	int apic_init(CPUState *env);
87ecb68b PB	45	int apic_accept_pic_intr(CPUState *env);
a5b38b51	46	void apic_local_deliver(CPUState *env, int vector);
87ecb68b PB	47	int apic_get_interrupt(CPUState *env);
	48	IOAPICState *ioapic_init(void);
	49	void ioapic_set_irq(void *opaque, int vector, int level);
	50
	51	/* i8254.c */
	52
	53	#define PIT_FREQ 1193182
	54
	55	typedef struct PITState PITState;
	56
	57	PITState *pit_init(int base, qemu_irq irq);
	58	void pit_set_gate(PITState *pit, int channel, int val);
	59	int pit_get_gate(PITState *pit, int channel);
	60	int pit_get_initial_count(PITState *pit, int channel);
	61	int pit_get_mode(PITState *pit, int channel);
	62	int pit_get_out(PITState *pit, int channel, int64_t current_time);
	63
	64	/* vmport.c */
26fb5e48	65	void vmport_init(void);
87ecb68b PB	66	void vmport_register(unsigned char command, IOPortReadFunc func, void opaque);
	67
	68	/* vmmouse.c */
	69	void vmmouse_init(void m);
	70
	71	/* pckbd.c */
	72
	73	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	74	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
	75	target_phys_addr_t base, int it_shift);
	76
	77	/* mc146818rtc.c */
	78
	79	typedef struct RTCState RTCState;
	80
	81	RTCState *rtc_init(int base, qemu_irq irq);
	82	RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
	83	void rtc_set_memory(RTCState *s, int addr, int val);
	84	void rtc_set_date(RTCState s, const struct tm tm);
	85
	86	/* pc.c */
	87	extern int fd_bootchk;
	88
	89	void ioport_set_a20(int enable);
	90	int ioport_get_a20(void);
	91
	92	/* acpi.c */
	93	extern int acpi_enabled;
cf7a2fe2 AJ	94	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
cf7a2fe2 AJ	95	qemu_irq sci_irq);
87ecb68b PB	96	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
	97	void acpi_bios_init(void);
	98
	99	/* pcspk.c */
	100	void pcspk_init(PITState *);
	101	int pcspk_audio_init(AudioState , qemu_irq pic);
	102
	103	/* piix_pci.c */
	104	PCIBus i440fx_init(PCIDevice pi440fx_state, qemu_irq pic);
	105	void i440fx_set_smm(PCIDevice *d, int val);
	106	int piix3_init(PCIBus *bus, int devfn);
	107	void i440fx_init_memory_mappings(PCIDevice *d);
	108
	109	int piix4_init(PCIBus *bus, int devfn);
	110
	111	/* vga.c */
	112
	113	#ifndef TARGET_SPARC
	114	#define VGA_RAM_SIZE (8192 * 1024)
	115	#else
	116	#define VGA_RAM_SIZE (9 * 1024 * 1024)
	117	#endif
	118
	119	int isa_vga_init(DisplayState ds, uint8_t vga_ram_base,
	120	unsigned long vga_ram_offset, int vga_ram_size);
	121	int pci_vga_init(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
	122	unsigned long vga_ram_offset, int vga_ram_size,
	123	unsigned long vga_bios_offset, int vga_bios_size);
	124	int isa_vga_mm_init(DisplayState ds, uint8_t vga_ram_base,
	125	unsigned long vga_ram_offset, int vga_ram_size,
	126	target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
	127	int it_shift);
	128
	129	/* cirrus_vga.c */
	130	void pci_cirrus_vga_init(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
	131	unsigned long vga_ram_offset, int vga_ram_size);
	132	void isa_cirrus_vga_init(DisplayState ds, uint8_t vga_ram_base,
	133	unsigned long vga_ram_offset, int vga_ram_size);
	134
	135	/* ide.c */
	136	void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
	137	BlockDriverState hd0, BlockDriverState hd1);
	138	void pci_cmd646_ide_init(PCIBus bus, BlockDriverState *hd_table,
	139	int secondary_ide_enabled);
	140	void pci_piix3_ide_init(PCIBus bus, BlockDriverState *hd_table, int devfn,
	141	qemu_irq *pic);
	142	void pci_piix4_ide_init(PCIBus bus, BlockDriverState *hd_table, int devfn,
	143	qemu_irq *pic);
	144
	145	/* ne2000.c */
	146
	147	void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
	148
	149	#endif