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Introduce PIIX3IrqState for piix3 irq's state
[mirror_qemu.git] / hw / pc.h
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1#ifndef HW_PC_H
2#define HW_PC_H
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3
4#include "qemu-common.h"
5
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6/* PC-style peripherals (also used by other machines). */
7
8/* serial.c */
9
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10SerialState *serial_init(int base, qemu_irq irq, int baudbase,
11 CharDriverState *chr);
87ecb68b 12SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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13 qemu_irq irq, int baudbase,
14 CharDriverState *chr, int ioregister);
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15
16/* parallel.c */
17
18typedef struct ParallelState ParallelState;
19ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
20ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
21
22/* i8259.c */
23
24typedef struct PicState2 PicState2;
25extern PicState2 *isa_pic;
26void pic_set_irq(int irq, int level);
27void pic_set_irq_new(void *opaque, int irq, int level);
28qemu_irq *i8259_init(qemu_irq parent_irq);
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29int pic_read_irq(PicState2 *s);
30void pic_update_irq(PicState2 *s);
31uint32_t pic_intack_read(PicState2 *s);
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32void pic_info(Monitor *mon);
33void irq_info(Monitor *mon);
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34
35/* APIC */
36typedef struct IOAPICState IOAPICState;
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37void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
38 uint8_t delivery_mode,
39 uint8_t vector_num, uint8_t polarity,
40 uint8_t trigger_mode);
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41int apic_init(CPUState *env);
42int apic_accept_pic_intr(CPUState *env);
1a7de94a 43void apic_deliver_pic_intr(CPUState *env, int level);
87ecb68b 44int apic_get_interrupt(CPUState *env);
1632dc6a 45qemu_irq *ioapic_init(void);
87ecb68b 46void ioapic_set_irq(void *opaque, int vector, int level);
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47void apic_reset_irq_delivered(void);
48int apic_get_irq_delivered(void);
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49
50/* i8254.c */
51
52#define PIT_FREQ 1193182
53
54typedef struct PITState PITState;
55
56PITState *pit_init(int base, qemu_irq irq);
57void pit_set_gate(PITState *pit, int channel, int val);
58int pit_get_gate(PITState *pit, int channel);
59int pit_get_initial_count(PITState *pit, int channel);
60int pit_get_mode(PITState *pit, int channel);
61int pit_get_out(PITState *pit, int channel, int64_t current_time);
62
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63void hpet_pit_disable(void);
64void hpet_pit_enable(void);
65
87ecb68b 66/* vmport.c */
26fb5e48 67void vmport_init(void);
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68void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
69
70/* vmmouse.c */
71void *vmmouse_init(void *m);
72
73/* pckbd.c */
74
75void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
76void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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77 target_phys_addr_t base, ram_addr_t size,
78 target_phys_addr_t mask);
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79
80/* mc146818rtc.c */
81
82typedef struct RTCState RTCState;
83
42fc73a1 84RTCState *rtc_init(int base, qemu_irq irq, int base_year);
100d9891 85RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year);
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86RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
87 int base_year);
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88void rtc_set_memory(RTCState *s, int addr, int val);
89void rtc_set_date(RTCState *s, const struct tm *tm);
0bacd130 90void cmos_set_s3_resume(void);
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91
92/* pc.c */
93extern int fd_bootchk;
94
95void ioport_set_a20(int enable);
96int ioport_get_a20(void);
97
98/* acpi.c */
99extern int acpi_enabled;
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100extern char *acpi_tables;
101extern size_t acpi_tables_len;
102
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103void acpi_bios_init(void);
104int acpi_table_add(const char *table_desc);
105
106/* acpi_piix.c */
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107i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
108 qemu_irq sci_irq);
87ecb68b 109void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
9d5e77a2 110void piix4_acpi_system_hot_add_init(void);
87ecb68b 111
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112/* hpet.c */
113extern int no_hpet;
114
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115/* pcspk.c */
116void pcspk_init(PITState *);
22d83b14 117int pcspk_audio_init(qemu_irq *pic);
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118
119/* piix_pci.c */
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120struct PCII440FXState;
121typedef struct PCII440FXState PCII440FXState;
122
123PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic);
124void i440fx_set_smm(PCII440FXState *d, int val);
87ecb68b 125int piix3_init(PCIBus *bus, int devfn);
0a3bacf3 126void i440fx_init_memory_mappings(PCII440FXState *d);
87ecb68b 127
823e675a 128/* piix4.c */
b1d8e52e 129extern PCIDevice *piix4_dev;
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130int piix4_init(PCIBus *bus, int devfn);
131
132/* vga.c */
cb5a7aa8 133enum vga_retrace_method {
134 VGA_RETRACE_DUMB,
135 VGA_RETRACE_PRECISE
136};
137
138extern enum vga_retrace_method vga_retrace_method;
87ecb68b 139
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140int isa_vga_init(void);
141int pci_vga_init(PCIBus *bus,
87ecb68b 142 unsigned long vga_bios_offset, int vga_bios_size);
fbe1b595 143int isa_vga_mm_init(target_phys_addr_t vram_base,
b584726d 144 target_phys_addr_t ctrl_base, int it_shift);
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145
146/* cirrus_vga.c */
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147void pci_cirrus_vga_init(PCIBus *bus);
148void isa_cirrus_vga_init(void);
87ecb68b 149
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150/* ne2000.c */
151
152void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
153
678e12cc 154int cpu_is_bsp(CPUState *env);
87ecb68b 155#endif