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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
97d5408f | 25 | #include "qemu/osdep.h" |
2c65db5e | 26 | #include "qemu/datadir.h" |
7c16b5bb | 27 | #include "qemu/units.h" |
64552b6b | 28 | #include "hw/irq.h" |
c759b24f MT |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_bridge.h" | |
06aac7bd | 31 | #include "hw/pci/pci_bus.h" |
568f0690 | 32 | #include "hw/pci/pci_host.h" |
a27bd6c7 | 33 | #include "hw/qdev-properties.h" |
ce35e229 | 34 | #include "hw/qdev-properties-system.h" |
ca77ee28 | 35 | #include "migration/qemu-file-types.h" |
d6454270 | 36 | #include "migration/vmstate.h" |
83c9089e | 37 | #include "monitor/monitor.h" |
1422e32d | 38 | #include "net/net.h" |
b58c5c2d | 39 | #include "sysemu/numa.h" |
46517dd4 | 40 | #include "sysemu/sysemu.h" |
c759b24f | 41 | #include "hw/loader.h" |
d49b6836 | 42 | #include "qemu/error-report.h" |
1de7afc9 | 43 | #include "qemu/range.h" |
7828d750 | 44 | #include "trace.h" |
c759b24f MT |
45 | #include "hw/pci/msi.h" |
46 | #include "hw/pci/msix.h" | |
5e954943 | 47 | #include "hw/hotplug.h" |
e4024630 | 48 | #include "hw/boards.h" |
e688df6b | 49 | #include "qapi/error.h" |
61c7f987 | 50 | #include "qapi/qapi-commands-pci.h" |
f348b6d1 | 51 | #include "qemu/cutils.h" |
69b91039 FB |
52 | |
53 | //#define DEBUG_PCI | |
d8d2e079 | 54 | #ifdef DEBUG_PCI |
2e49d64a | 55 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
56 | #else |
57 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
58 | #endif | |
69b91039 | 59 | |
88c725c7 CH |
60 | bool pci_available = true; |
61 | ||
10c4c98a | 62 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 63 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 64 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
dcc20931 | 65 | static void pcibus_reset(BusState *qbus); |
10c4c98a | 66 | |
3cb75a7c PB |
67 | static Property pci_props[] = { |
68 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), | |
69 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), | |
08b1df8f | 70 | DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1), |
3cb75a7c PB |
71 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
72 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, | |
73 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
6b449540 MT |
74 | DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, |
75 | QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), | |
f03d8ea3 MA |
76 | DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, |
77 | QEMU_PCIE_EXTCAP_INIT_BITNR, true), | |
4f5b6a05 JF |
78 | DEFINE_PROP_STRING("failover_pair_id", PCIDevice, |
79 | failover_pair_id), | |
b32bd763 | 80 | DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), |
3cb75a7c PB |
81 | DEFINE_PROP_END_OF_LIST() |
82 | }; | |
83 | ||
d2f69df7 BD |
84 | static const VMStateDescription vmstate_pcibus = { |
85 | .name = "PCIBUS", | |
86 | .version_id = 1, | |
87 | .minimum_version_id = 1, | |
d49805ae | 88 | .fields = (VMStateField[]) { |
d2164ad3 | 89 | VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), |
d2f69df7 BD |
90 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, |
91 | nirq, 0, vmstate_info_int32, | |
92 | int32_t), | |
93 | VMSTATE_END_OF_LIST() | |
94 | } | |
95 | }; | |
96 | ||
b86eacb8 MA |
97 | static void pci_init_bus_master(PCIDevice *pci_dev) |
98 | { | |
99 | AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); | |
100 | ||
101 | memory_region_init_alias(&pci_dev->bus_master_enable_region, | |
102 | OBJECT(pci_dev), "bus master", | |
103 | dma_as->root, 0, memory_region_size(dma_as->root)); | |
104 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); | |
3716d590 JW |
105 | memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, |
106 | &pci_dev->bus_master_enable_region); | |
b86eacb8 MA |
107 | } |
108 | ||
109 | static void pcibus_machine_done(Notifier *notifier, void *data) | |
110 | { | |
111 | PCIBus *bus = container_of(notifier, PCIBus, machine_done); | |
112 | int i; | |
113 | ||
114 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
115 | if (bus->devices[i]) { | |
116 | pci_init_bus_master(bus->devices[i]); | |
117 | } | |
118 | } | |
119 | } | |
120 | ||
d2f69df7 BD |
121 | static void pci_bus_realize(BusState *qbus, Error **errp) |
122 | { | |
123 | PCIBus *bus = PCI_BUS(qbus); | |
124 | ||
b86eacb8 MA |
125 | bus->machine_done.notify = pcibus_machine_done; |
126 | qemu_add_machine_init_done_notifier(&bus->machine_done); | |
127 | ||
1df2c9a2 | 128 | vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus); |
d2f69df7 BD |
129 | } |
130 | ||
2f57db8a DG |
131 | static void pcie_bus_realize(BusState *qbus, Error **errp) |
132 | { | |
133 | PCIBus *bus = PCI_BUS(qbus); | |
b52fa0ea | 134 | Error *local_err = NULL; |
2f57db8a | 135 | |
b52fa0ea PMD |
136 | pci_bus_realize(qbus, &local_err); |
137 | if (local_err) { | |
138 | error_propagate(errp, local_err); | |
139 | return; | |
140 | } | |
2f57db8a DG |
141 | |
142 | /* | |
143 | * A PCI-E bus can support extended config space if it's the root | |
144 | * bus, or if the bus/bridge above it does as well | |
145 | */ | |
146 | if (pci_bus_is_root(bus)) { | |
147 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; | |
148 | } else { | |
149 | PCIBus *parent_bus = pci_get_bus(bus->parent_dev); | |
150 | ||
151 | if (pci_bus_allows_extended_config_space(parent_bus)) { | |
152 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; | |
153 | } | |
154 | } | |
155 | } | |
156 | ||
b69c3c21 | 157 | static void pci_bus_unrealize(BusState *qbus) |
d2f69df7 BD |
158 | { |
159 | PCIBus *bus = PCI_BUS(qbus); | |
160 | ||
b86eacb8 MA |
161 | qemu_remove_machine_init_done_notifier(&bus->machine_done); |
162 | ||
d2f69df7 BD |
163 | vmstate_unregister(NULL, &vmstate_pcibus, bus); |
164 | } | |
165 | ||
602141d9 MA |
166 | static int pcibus_num(PCIBus *bus) |
167 | { | |
b0e5196a | 168 | if (pci_bus_is_root(bus)) { |
602141d9 MA |
169 | return 0; /* pci host bridge */ |
170 | } | |
171 | return bus->parent_dev->config[PCI_SECONDARY_BUS]; | |
172 | } | |
173 | ||
6a3042b2 MA |
174 | static uint16_t pcibus_numa_node(PCIBus *bus) |
175 | { | |
176 | return NUMA_NODE_UNASSIGNED; | |
177 | } | |
178 | ||
0d936928 AL |
179 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
180 | { | |
181 | BusClass *k = BUS_CLASS(klass); | |
ce6a28ee | 182 | PCIBusClass *pbc = PCI_BUS_CLASS(klass); |
0d936928 AL |
183 | |
184 | k->print_dev = pcibus_dev_print; | |
185 | k->get_dev_path = pcibus_get_dev_path; | |
186 | k->get_fw_dev_path = pcibus_get_fw_dev_path; | |
d2f69df7 BD |
187 | k->realize = pci_bus_realize; |
188 | k->unrealize = pci_bus_unrealize; | |
0d936928 | 189 | k->reset = pcibus_reset; |
ce6a28ee | 190 | |
602141d9 | 191 | pbc->bus_num = pcibus_num; |
6a3042b2 | 192 | pbc->numa_node = pcibus_numa_node; |
0d936928 AL |
193 | } |
194 | ||
195 | static const TypeInfo pci_bus_info = { | |
196 | .name = TYPE_PCI_BUS, | |
197 | .parent = TYPE_BUS, | |
198 | .instance_size = sizeof(PCIBus), | |
ce6a28ee | 199 | .class_size = sizeof(PCIBusClass), |
0d936928 | 200 | .class_init = pci_bus_class_init, |
30468f78 | 201 | }; |
69b91039 | 202 | |
cf04aba2 BW |
203 | static const TypeInfo cxl_interface_info = { |
204 | .name = INTERFACE_CXL_DEVICE, | |
205 | .parent = TYPE_INTERFACE, | |
206 | }; | |
207 | ||
619f02ae EH |
208 | static const TypeInfo pcie_interface_info = { |
209 | .name = INTERFACE_PCIE_DEVICE, | |
210 | .parent = TYPE_INTERFACE, | |
211 | }; | |
212 | ||
213 | static const TypeInfo conventional_pci_interface_info = { | |
214 | .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, | |
215 | .parent = TYPE_INTERFACE, | |
216 | }; | |
217 | ||
1c685a90 GK |
218 | static void pcie_bus_class_init(ObjectClass *klass, void *data) |
219 | { | |
2f57db8a | 220 | BusClass *k = BUS_CLASS(klass); |
1c685a90 | 221 | |
2f57db8a | 222 | k->realize = pcie_bus_realize; |
1c685a90 GK |
223 | } |
224 | ||
3a861c46 AW |
225 | static const TypeInfo pcie_bus_info = { |
226 | .name = TYPE_PCIE_BUS, | |
227 | .parent = TYPE_PCI_BUS, | |
1c685a90 | 228 | .class_init = pcie_bus_class_init, |
3a861c46 AW |
229 | }; |
230 | ||
4f8db871 BW |
231 | static const TypeInfo cxl_bus_info = { |
232 | .name = TYPE_CXL_BUS, | |
233 | .parent = TYPE_PCIE_BUS, | |
234 | .class_init = pcie_bus_class_init, | |
235 | }; | |
236 | ||
d662210a | 237 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
1941d19c | 238 | static void pci_update_mappings(PCIDevice *d); |
d98f08f5 | 239 | static void pci_irq_handler(void *opaque, int irq_num, int level); |
133e9b22 | 240 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); |
230741dc | 241 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 242 | |
d350d97d AL |
243 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
244 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a | 245 | |
7588e2b0 | 246 | static QLIST_HEAD(, PCIHostState) pci_host_bridges; |
30468f78 | 247 | |
cf8c704d | 248 | int pci_bar(PCIDevice *d, int reg) |
5330de09 | 249 | { |
b3b11697 IY |
250 | uint8_t type; |
251 | ||
7c0fa8df KO |
252 | /* PCIe virtual functions do not have their own BARs */ |
253 | assert(!pci_is_vf(d)); | |
254 | ||
b3b11697 IY |
255 | if (reg != PCI_ROM_SLOT) |
256 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
257 | ||
258 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
259 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
260 | } |
261 | ||
d036bb21 MT |
262 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
263 | { | |
7d37435b | 264 | return (d->irq_state >> irq_num) & 0x1; |
d036bb21 MT |
265 | } |
266 | ||
267 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
268 | { | |
7d37435b PB |
269 | d->irq_state &= ~(0x1 << irq_num); |
270 | d->irq_state |= level << irq_num; | |
d036bb21 MT |
271 | } |
272 | ||
b06fe3e7 PMD |
273 | static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) |
274 | { | |
459ca8bf MCA |
275 | assert(irq_num >= 0); |
276 | assert(irq_num < bus->nirq); | |
b06fe3e7 PMD |
277 | bus->irq_count[irq_num] += change; |
278 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
279 | } | |
280 | ||
d036bb21 MT |
281 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
282 | { | |
283 | PCIBus *bus; | |
284 | for (;;) { | |
fd56e061 | 285 | bus = pci_get_bus(pci_dev); |
d036bb21 MT |
286 | irq_num = bus->map_irq(pci_dev, irq_num); |
287 | if (bus->set_irq) | |
288 | break; | |
289 | pci_dev = bus->parent_dev; | |
290 | } | |
b06fe3e7 | 291 | pci_bus_change_irq_level(bus, irq_num, change); |
d036bb21 MT |
292 | } |
293 | ||
9ddf8437 IY |
294 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
295 | { | |
296 | assert(irq_num >= 0); | |
297 | assert(irq_num < bus->nirq); | |
298 | return !!bus->irq_count[irq_num]; | |
299 | } | |
300 | ||
f9bf77dd MT |
301 | /* Update interrupt status bit in config space on interrupt |
302 | * state change. */ | |
303 | static void pci_update_irq_status(PCIDevice *dev) | |
304 | { | |
305 | if (dev->irq_state) { | |
306 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
307 | } else { | |
308 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
309 | } | |
310 | } | |
311 | ||
4c92325b IY |
312 | void pci_device_deassert_intx(PCIDevice *dev) |
313 | { | |
314 | int i; | |
315 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
d98f08f5 | 316 | pci_irq_handler(dev, i, 0); |
4c92325b IY |
317 | } |
318 | } | |
319 | ||
7c0fa8df | 320 | static void pci_reset_regions(PCIDevice *dev) |
5330de09 | 321 | { |
c0b1905b | 322 | int r; |
7c0fa8df KO |
323 | if (pci_is_vf(dev)) { |
324 | return; | |
325 | } | |
326 | ||
327 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
328 | PCIIORegion *region = &dev->io_regions[r]; | |
329 | if (!region->size) { | |
330 | continue; | |
331 | } | |
6fc4925b | 332 | |
7c0fa8df KO |
333 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && |
334 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
335 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
336 | } else { | |
337 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
338 | } | |
339 | } | |
340 | } | |
341 | ||
342 | static void pci_do_device_reset(PCIDevice *dev) | |
343 | { | |
4c92325b | 344 | pci_device_deassert_intx(dev); |
58b59014 CR |
345 | assert(dev->irq_state == 0); |
346 | ||
ebabb67a | 347 | /* Clear all writable bits */ |
99443c21 | 348 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
349 | pci_get_word(dev->wmask + PCI_COMMAND) | |
350 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
351 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
352 | pci_get_word(dev->wmask + PCI_STATUS) | | |
353 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
7ff81d63 BZ |
354 | /* Some devices make bits of PCI_INTERRUPT_LINE read only */ |
355 | pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, | |
356 | pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | | |
357 | pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); | |
c0b1905b | 358 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
7c0fa8df | 359 | pci_reset_regions(dev); |
c0b1905b | 360 | pci_update_mappings(dev); |
cbd2d434 JK |
361 | |
362 | msi_reset(dev); | |
363 | msix_reset(dev); | |
5330de09 MT |
364 | } |
365 | ||
dcc20931 PB |
366 | /* |
367 | * This function is called on #RST and FLR. | |
368 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
369 | */ | |
370 | void pci_device_reset(PCIDevice *dev) | |
371 | { | |
372 | qdev_reset_all(&dev->qdev); | |
373 | pci_do_device_reset(dev); | |
374 | } | |
375 | ||
9bb33586 IY |
376 | /* |
377 | * Trigger pci bus reset under a given bus. | |
dcc20931 PB |
378 | * Called via qbus_reset_all on RST# assert, after the devices |
379 | * have been reset qdev_reset_all-ed already. | |
9bb33586 | 380 | */ |
dcc20931 | 381 | static void pcibus_reset(BusState *qbus) |
6eaa6847 | 382 | { |
81e3e75b | 383 | PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); |
6eaa6847 GN |
384 | int i; |
385 | ||
5330de09 MT |
386 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
387 | if (bus->devices[i]) { | |
dcc20931 | 388 | pci_do_device_reset(bus->devices[i]); |
5330de09 | 389 | } |
6eaa6847 | 390 | } |
9bb33586 | 391 | |
9bdbbfc3 PB |
392 | for (i = 0; i < bus->nirq; i++) { |
393 | assert(bus->irq_count[i] == 0); | |
394 | } | |
9bb33586 IY |
395 | } |
396 | ||
3dbc01ae | 397 | static void pci_host_bus_register(DeviceState *host) |
e822a52a | 398 | { |
3dbc01ae | 399 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); |
7588e2b0 DG |
400 | |
401 | QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); | |
e822a52a IY |
402 | } |
403 | ||
c13ee169 MR |
404 | static void pci_host_bus_unregister(DeviceState *host) |
405 | { | |
406 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); | |
407 | ||
408 | QLIST_REMOVE(host_bridge, next); | |
409 | } | |
410 | ||
c473d18d | 411 | PCIBus *pci_device_root_bus(const PCIDevice *d) |
e075e788 | 412 | { |
fd56e061 | 413 | PCIBus *bus = pci_get_bus(d); |
e075e788 | 414 | |
ce6a28ee MA |
415 | while (!pci_bus_is_root(bus)) { |
416 | d = bus->parent_dev; | |
417 | assert(d != NULL); | |
418 | ||
fd56e061 | 419 | bus = pci_get_bus(d); |
e075e788 IY |
420 | } |
421 | ||
c473d18d DG |
422 | return bus; |
423 | } | |
424 | ||
568f0690 | 425 | const char *pci_root_bus_path(PCIDevice *dev) |
c473d18d | 426 | { |
568f0690 DG |
427 | PCIBus *rootbus = pci_device_root_bus(dev); |
428 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); | |
429 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); | |
c473d18d | 430 | |
568f0690 DG |
431 | assert(host_bridge->bus == rootbus); |
432 | ||
433 | if (hc->root_bus_path) { | |
434 | return (*hc->root_bus_path)(host_bridge, rootbus); | |
e075e788 IY |
435 | } |
436 | ||
568f0690 | 437 | return rootbus->qbus.name; |
e075e788 IY |
438 | } |
439 | ||
2d64b7bb XW |
440 | bool pci_bus_bypass_iommu(PCIBus *bus) |
441 | { | |
442 | PCIBus *rootbus = bus; | |
443 | PCIHostState *host_bridge; | |
444 | ||
445 | if (!pci_bus_is_root(bus)) { | |
446 | rootbus = pci_device_root_bus(bus->parent_dev); | |
447 | } | |
448 | ||
449 | host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); | |
450 | ||
451 | assert(host_bridge->bus == rootbus); | |
452 | ||
453 | return host_bridge->bypass_iommu; | |
454 | } | |
455 | ||
8d4cdf01 PM |
456 | static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, |
457 | MemoryRegion *address_space_mem, | |
458 | MemoryRegion *address_space_io, | |
459 | uint8_t devfn_min) | |
30468f78 | 460 | { |
6fa84913 | 461 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 462 | bus->devfn_min = devfn_min; |
8b884984 | 463 | bus->slot_reserved_mask = 0x0; |
5968eca3 AK |
464 | bus->address_space_mem = address_space_mem; |
465 | bus->address_space_io = address_space_io; | |
b0e5196a | 466 | bus->flags |= PCI_BUS_IS_ROOT; |
e822a52a IY |
467 | |
468 | /* host bridge */ | |
469 | QLIST_INIT(&bus->child); | |
2b8cc89a | 470 | |
3dbc01ae | 471 | pci_host_bus_register(parent); |
21eea4b3 GH |
472 | } |
473 | ||
c13ee169 MR |
474 | static void pci_bus_uninit(PCIBus *bus) |
475 | { | |
476 | pci_host_bus_unregister(BUS(bus)->parent); | |
477 | } | |
478 | ||
8c0bf9e2 AW |
479 | bool pci_bus_is_express(PCIBus *bus) |
480 | { | |
481 | return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); | |
482 | } | |
483 | ||
8d4cdf01 PM |
484 | void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, |
485 | const char *name, | |
486 | MemoryRegion *address_space_mem, | |
487 | MemoryRegion *address_space_io, | |
488 | uint8_t devfn_min, const char *typename) | |
4fec6404 | 489 | { |
d637e1dc | 490 | qbus_init(bus, bus_size, typename, parent, name); |
8d4cdf01 PM |
491 | pci_root_bus_internal_init(bus, parent, address_space_mem, |
492 | address_space_io, devfn_min); | |
4fec6404 PB |
493 | } |
494 | ||
1115ff6d DG |
495 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, |
496 | MemoryRegion *address_space_mem, | |
497 | MemoryRegion *address_space_io, | |
498 | uint8_t devfn_min, const char *typename) | |
21eea4b3 GH |
499 | { |
500 | PCIBus *bus; | |
501 | ||
9388d170 | 502 | bus = PCI_BUS(qbus_new(typename, parent, name)); |
8d4cdf01 PM |
503 | pci_root_bus_internal_init(bus, parent, address_space_mem, |
504 | address_space_io, devfn_min); | |
21eea4b3 GH |
505 | return bus; |
506 | } | |
507 | ||
c13ee169 MR |
508 | void pci_root_bus_cleanup(PCIBus *bus) |
509 | { | |
510 | pci_bus_uninit(bus); | |
07578b0a | 511 | /* the caller of the unplug hotplug handler will delete this device */ |
f1483b46 | 512 | qbus_unrealize(BUS(bus)); |
c13ee169 MR |
513 | } |
514 | ||
21eea4b3 GH |
515 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
516 | void *irq_opaque, int nirq) | |
517 | { | |
518 | bus->set_irq = set_irq; | |
519 | bus->map_irq = map_irq; | |
520 | bus->irq_opaque = irq_opaque; | |
521 | bus->nirq = nirq; | |
7267c094 | 522 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
21eea4b3 GH |
523 | } |
524 | ||
c13ee169 MR |
525 | void pci_bus_irqs_cleanup(PCIBus *bus) |
526 | { | |
527 | bus->set_irq = NULL; | |
528 | bus->map_irq = NULL; | |
529 | bus->irq_opaque = NULL; | |
530 | bus->nirq = 0; | |
531 | g_free(bus->irq_count); | |
532 | } | |
533 | ||
1115ff6d DG |
534 | PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, |
535 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
536 | void *irq_opaque, | |
537 | MemoryRegion *address_space_mem, | |
538 | MemoryRegion *address_space_io, | |
539 | uint8_t devfn_min, int nirq, | |
540 | const char *typename) | |
21eea4b3 GH |
541 | { |
542 | PCIBus *bus; | |
543 | ||
1115ff6d DG |
544 | bus = pci_root_bus_new(parent, name, address_space_mem, |
545 | address_space_io, devfn_min, typename); | |
21eea4b3 | 546 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
30468f78 FB |
547 | return bus; |
548 | } | |
69b91039 | 549 | |
c13ee169 MR |
550 | void pci_unregister_root_bus(PCIBus *bus) |
551 | { | |
552 | pci_bus_irqs_cleanup(bus); | |
553 | pci_root_bus_cleanup(bus); | |
554 | } | |
555 | ||
502a5395 PB |
556 | int pci_bus_num(PCIBus *s) |
557 | { | |
602141d9 | 558 | return PCI_BUS_GET_CLASS(s)->bus_num(s); |
502a5395 PB |
559 | } |
560 | ||
500db1da XW |
561 | /* Returns the min and max bus numbers of a PCI bus hierarchy */ |
562 | void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) | |
563 | { | |
564 | int i; | |
565 | *min_bus = *max_bus = pci_bus_num(bus); | |
566 | ||
567 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
568 | PCIDevice *dev = bus->devices[i]; | |
569 | ||
570 | if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { | |
571 | *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); | |
572 | *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
6a3042b2 MA |
577 | int pci_bus_numa_node(PCIBus *bus) |
578 | { | |
579 | return PCI_BUS_GET_CLASS(bus)->numa_node(bus); | |
502a5395 PB |
580 | } |
581 | ||
2c21ee76 | 582 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, |
03fee66f | 583 | const VMStateField *field) |
30ca2aab | 584 | { |
73534f2f | 585 | PCIDevice *s = container_of(pv, PCIDevice, config); |
e78e9ae4 | 586 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); |
a9f49946 | 587 | uint8_t *config; |
52fc1d83 AZ |
588 | int i; |
589 | ||
a9f49946 | 590 | assert(size == pci_config_size(s)); |
7267c094 | 591 | config = g_malloc(size); |
a9f49946 IY |
592 | |
593 | qemu_get_buffer(f, config, size); | |
594 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
595 | if ((config[i] ^ s->config[i]) & |
596 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
7c59364d DDAG |
597 | error_report("%s: Bad config data: i=0x%x read: %x device: %x " |
598 | "cmask: %x wmask: %x w1cmask:%x", __func__, | |
599 | i, config[i], s->config[i], | |
600 | s->cmask[i], s->wmask[i], s->w1cmask[i]); | |
7267c094 | 601 | g_free(config); |
bd4b65ee | 602 | return -EINVAL; |
a9f49946 IY |
603 | } |
604 | } | |
605 | memcpy(s->config, config, size); | |
bd4b65ee | 606 | |
1941d19c | 607 | pci_update_mappings(s); |
e78e9ae4 | 608 | if (pc->is_bridge) { |
f055e96b | 609 | PCIBridge *b = PCI_BRIDGE(s); |
e78e9ae4 DK |
610 | pci_bridge_update_mappings(b); |
611 | } | |
52fc1d83 | 612 | |
4ea375bf GH |
613 | memory_region_set_enabled(&s->bus_master_enable_region, |
614 | pci_get_word(s->config + PCI_COMMAND) | |
615 | & PCI_COMMAND_MASTER); | |
616 | ||
7267c094 | 617 | g_free(config); |
30ca2aab FB |
618 | return 0; |
619 | } | |
620 | ||
73534f2f | 621 | /* just put buffer */ |
2c21ee76 | 622 | static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, |
3ddba9a9 | 623 | const VMStateField *field, JSONWriter *vmdesc) |
73534f2f | 624 | { |
dbe73d7f | 625 | const uint8_t **v = pv; |
a9f49946 | 626 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 627 | qemu_put_buffer(f, *v, size); |
2c21ee76 JD |
628 | |
629 | return 0; | |
73534f2f JQ |
630 | } |
631 | ||
632 | static VMStateInfo vmstate_info_pci_config = { | |
633 | .name = "pci config", | |
634 | .get = get_pci_config_device, | |
635 | .put = put_pci_config_device, | |
636 | }; | |
637 | ||
2c21ee76 | 638 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, |
03fee66f | 639 | const VMStateField *field) |
d036bb21 | 640 | { |
c3f8f611 | 641 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
642 | uint32_t irq_state[PCI_NUM_PINS]; |
643 | int i; | |
644 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
645 | irq_state[i] = qemu_get_be32(f); | |
646 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
647 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
648 | irq_state[i]); | |
649 | return -EINVAL; | |
650 | } | |
651 | } | |
652 | ||
653 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
654 | pci_set_irq_state(s, i, irq_state[i]); | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
2c21ee76 | 660 | static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, |
3ddba9a9 | 661 | const VMStateField *field, JSONWriter *vmdesc) |
d036bb21 MT |
662 | { |
663 | int i; | |
c3f8f611 | 664 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
665 | |
666 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
667 | qemu_put_be32(f, pci_irq_state(s, i)); | |
668 | } | |
2c21ee76 JD |
669 | |
670 | return 0; | |
d036bb21 MT |
671 | } |
672 | ||
673 | static VMStateInfo vmstate_info_pci_irq_state = { | |
674 | .name = "pci irq state", | |
675 | .get = get_pci_irq_state, | |
676 | .put = put_pci_irq_state, | |
677 | }; | |
678 | ||
20daa90a DDAG |
679 | static bool migrate_is_pcie(void *opaque, int version_id) |
680 | { | |
681 | return pci_is_express((PCIDevice *)opaque); | |
682 | } | |
683 | ||
684 | static bool migrate_is_not_pcie(void *opaque, int version_id) | |
685 | { | |
686 | return !pci_is_express((PCIDevice *)opaque); | |
687 | } | |
688 | ||
73534f2f JQ |
689 | const VMStateDescription vmstate_pci_device = { |
690 | .name = "PCIDevice", | |
691 | .version_id = 2, | |
692 | .minimum_version_id = 1, | |
d49805ae | 693 | .fields = (VMStateField[]) { |
3476436a | 694 | VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), |
20daa90a DDAG |
695 | VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, |
696 | migrate_is_not_pcie, | |
697 | 0, vmstate_info_pci_config, | |
a9f49946 | 698 | PCI_CONFIG_SPACE_SIZE), |
20daa90a DDAG |
699 | VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, |
700 | migrate_is_pcie, | |
701 | 0, vmstate_info_pci_config, | |
a9f49946 | 702 | PCIE_CONFIG_SPACE_SIZE), |
d036bb21 | 703 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
7d37435b PB |
704 | vmstate_info_pci_irq_state, |
705 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
706 | VMSTATE_END_OF_LIST() |
707 | } | |
708 | }; | |
709 | ||
a9f49946 | 710 | |
73534f2f JQ |
711 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
712 | { | |
f9bf77dd MT |
713 | /* Clear interrupt status bit: it is implicit |
714 | * in irq_state which we are saving. | |
715 | * This makes us compatible with old devices | |
716 | * which never set or clear this bit. */ | |
717 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
20daa90a | 718 | vmstate_save_state(f, &vmstate_pci_device, s, NULL); |
f9bf77dd MT |
719 | /* Restore the interrupt status bit. */ |
720 | pci_update_irq_status(s); | |
73534f2f JQ |
721 | } |
722 | ||
723 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
724 | { | |
f9bf77dd | 725 | int ret; |
20daa90a | 726 | ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); |
f9bf77dd MT |
727 | /* Restore the interrupt status bit. */ |
728 | pci_update_irq_status(s); | |
729 | return ret; | |
73534f2f JQ |
730 | } |
731 | ||
5e434f4e | 732 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 733 | { |
5e434f4e IY |
734 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
735 | pci_default_sub_vendor_id); | |
736 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
737 | pci_default_sub_device_id); | |
d350d97d AL |
738 | } |
739 | ||
880345c4 | 740 | /* |
43c945f1 IY |
741 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
742 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 743 | */ |
6dbcb819 MA |
744 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
745 | unsigned int *slotp, unsigned int *funcp) | |
880345c4 AL |
746 | { |
747 | const char *p; | |
748 | char *e; | |
749 | unsigned long val; | |
750 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
751 | unsigned int slot = 0; |
752 | unsigned int func = 0; | |
880345c4 AL |
753 | |
754 | p = addr; | |
755 | val = strtoul(p, &e, 16); | |
756 | if (e == p) | |
7d37435b | 757 | return -1; |
880345c4 | 758 | if (*e == ':') { |
7d37435b PB |
759 | bus = val; |
760 | p = e + 1; | |
761 | val = strtoul(p, &e, 16); | |
762 | if (e == p) | |
763 | return -1; | |
764 | if (*e == ':') { | |
765 | dom = bus; | |
766 | bus = val; | |
767 | p = e + 1; | |
768 | val = strtoul(p, &e, 16); | |
769 | if (e == p) | |
770 | return -1; | |
771 | } | |
880345c4 AL |
772 | } |
773 | ||
880345c4 AL |
774 | slot = val; |
775 | ||
43c945f1 IY |
776 | if (funcp != NULL) { |
777 | if (*e != '.') | |
778 | return -1; | |
779 | ||
780 | p = e + 1; | |
781 | val = strtoul(p, &e, 16); | |
782 | if (e == p) | |
783 | return -1; | |
784 | ||
785 | func = val; | |
786 | } | |
787 | ||
788 | /* if funcp == NULL func is 0 */ | |
789 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
7d37435b | 790 | return -1; |
43c945f1 | 791 | |
880345c4 | 792 | if (*e) |
7d37435b | 793 | return -1; |
880345c4 | 794 | |
880345c4 AL |
795 | *domp = dom; |
796 | *busp = bus; | |
797 | *slotp = slot; | |
43c945f1 IY |
798 | if (funcp != NULL) |
799 | *funcp = func; | |
880345c4 AL |
800 | return 0; |
801 | } | |
802 | ||
bd4b65ee MT |
803 | static void pci_init_cmask(PCIDevice *dev) |
804 | { | |
805 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
806 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
807 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
808 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
809 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
810 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
811 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
812 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
813 | } | |
814 | ||
b7ee1603 MT |
815 | static void pci_init_wmask(PCIDevice *dev) |
816 | { | |
a9f49946 IY |
817 | int config_size = pci_config_size(dev); |
818 | ||
b7ee1603 MT |
819 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
820 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 821 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
822 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
823 | PCI_COMMAND_INTX_DISABLE); | |
2a4dbaf1 | 824 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); |
3e21ffc9 IY |
825 | |
826 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
827 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
828 | } |
829 | ||
89d437df IY |
830 | static void pci_init_w1cmask(PCIDevice *dev) |
831 | { | |
832 | /* | |
f6bdfcc9 | 833 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
834 | * long as their value is hardwired to 0. |
835 | */ | |
836 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
837 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
838 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
839 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
840 | } | |
841 | ||
d5f27e88 | 842 | static void pci_init_mask_bridge(PCIDevice *d) |
fb231628 IY |
843 | { |
844 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
845 | PCI_SEC_LETENCY_TIMER */ | |
846 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
847 | ||
848 | /* base and limit */ | |
849 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
850 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
851 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
852 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
853 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
854 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
855 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
856 | PCI_PREF_RANGE_MASK & 0xffff); | |
857 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
858 | PCI_PREF_RANGE_MASK & 0xffff); | |
859 | ||
860 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
861 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
862 | ||
d5f27e88 | 863 | /* Supported memory and i/o types */ |
68917102 MT |
864 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
865 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; | |
d5f27e88 MT |
866 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
867 | PCI_PREF_RANGE_TYPE_64); | |
868 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, | |
869 | PCI_PREF_RANGE_TYPE_64); | |
870 | ||
45eb768c MT |
871 | /* |
872 | * TODO: Bridges default to 10-bit VGA decoding but we currently only | |
873 | * implement 16-bit decoding (no alias support). | |
874 | */ | |
f6bdfcc9 MT |
875 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
876 | PCI_BRIDGE_CTL_PARITY | | |
877 | PCI_BRIDGE_CTL_SERR | | |
878 | PCI_BRIDGE_CTL_ISA | | |
879 | PCI_BRIDGE_CTL_VGA | | |
880 | PCI_BRIDGE_CTL_VGA_16BIT | | |
881 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
882 | PCI_BRIDGE_CTL_BUS_RESET | | |
883 | PCI_BRIDGE_CTL_FAST_BACK | | |
884 | PCI_BRIDGE_CTL_DISCARD | | |
885 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
886 | PCI_BRIDGE_CTL_DISCARD_SERR); |
887 | /* Below does not do anything as we never set this bit, put here for | |
888 | * completeness. */ | |
889 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
890 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
d5f27e88 | 891 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
15ab7a75 | 892 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
d5f27e88 MT |
893 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
894 | PCI_PREF_RANGE_TYPE_MASK); | |
15ab7a75 MT |
895 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
896 | PCI_PREF_RANGE_TYPE_MASK); | |
fb231628 IY |
897 | } |
898 | ||
133e9b22 | 899 | static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) |
6eab3de1 IY |
900 | { |
901 | uint8_t slot = PCI_SLOT(dev->devfn); | |
902 | uint8_t func; | |
903 | ||
904 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
905 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
906 | } | |
907 | ||
7c0fa8df KO |
908 | /* |
909 | * With SR/IOV and ARI, a device at function 0 need not be a multifunction | |
910 | * device, as it may just be a VF that ended up with function 0 in | |
911 | * the legacy PCI interpretation. Avoid failing in such cases: | |
912 | */ | |
913 | if (pci_is_vf(dev) && | |
914 | dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
915 | return; | |
916 | } | |
917 | ||
6eab3de1 | 918 | /* |
b0cd712c | 919 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
920 | * - all functions must set the bit to 1. |
921 | * Example: Intel X53 | |
922 | * - function 0 must set the bit, but the rest function (> 0) | |
923 | * is allowed to leave the bit to 0. | |
924 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
925 | * | |
926 | * So OS (at least Linux) checks the bit of only function 0, | |
927 | * and doesn't see the bit of function > 0. | |
928 | * | |
929 | * The below check allows both interpretation. | |
930 | */ | |
931 | if (PCI_FUNC(dev->devfn)) { | |
932 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
933 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
934 | /* function 0 should set multifunction bit */ | |
133e9b22 MA |
935 | error_setg(errp, "PCI: single function device can't be populated " |
936 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
937 | return; | |
6eab3de1 | 938 | } |
133e9b22 | 939 | return; |
6eab3de1 IY |
940 | } |
941 | ||
942 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
133e9b22 | 943 | return; |
6eab3de1 IY |
944 | } |
945 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
946 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
947 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
133e9b22 MA |
948 | error_setg(errp, "PCI: %x.0 indicates single function, " |
949 | "but %x.%x is already populated.", | |
950 | slot, slot, func); | |
951 | return; | |
6eab3de1 IY |
952 | } |
953 | } | |
6eab3de1 IY |
954 | } |
955 | ||
a9f49946 IY |
956 | static void pci_config_alloc(PCIDevice *pci_dev) |
957 | { | |
958 | int config_size = pci_config_size(pci_dev); | |
959 | ||
7267c094 AL |
960 | pci_dev->config = g_malloc0(config_size); |
961 | pci_dev->cmask = g_malloc0(config_size); | |
962 | pci_dev->wmask = g_malloc0(config_size); | |
963 | pci_dev->w1cmask = g_malloc0(config_size); | |
964 | pci_dev->used = g_malloc0(config_size); | |
a9f49946 IY |
965 | } |
966 | ||
967 | static void pci_config_free(PCIDevice *pci_dev) | |
968 | { | |
7267c094 AL |
969 | g_free(pci_dev->config); |
970 | g_free(pci_dev->cmask); | |
971 | g_free(pci_dev->wmask); | |
972 | g_free(pci_dev->w1cmask); | |
973 | g_free(pci_dev->used); | |
a9f49946 IY |
974 | } |
975 | ||
30607764 MA |
976 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
977 | { | |
fd56e061 | 978 | pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; |
30607764 MA |
979 | pci_config_free(pci_dev); |
980 | ||
193982c6 AK |
981 | if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { |
982 | memory_region_del_subregion(&pci_dev->bus_master_container_region, | |
983 | &pci_dev->bus_master_enable_region); | |
984 | } | |
30607764 | 985 | address_space_destroy(&pci_dev->bus_master_as); |
30607764 MA |
986 | } |
987 | ||
4a94b3aa PX |
988 | /* Extract PCIReqIDCache into BDF format */ |
989 | static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) | |
990 | { | |
991 | uint8_t bus_n; | |
992 | uint16_t result; | |
993 | ||
994 | switch (cache->type) { | |
995 | case PCI_REQ_ID_BDF: | |
996 | result = pci_get_bdf(cache->dev); | |
997 | break; | |
998 | case PCI_REQ_ID_SECONDARY_BUS: | |
fd56e061 | 999 | bus_n = pci_dev_bus_num(cache->dev); |
4a94b3aa PX |
1000 | result = PCI_BUILD_BDF(bus_n, 0); |
1001 | break; | |
1002 | default: | |
eaf27fab | 1003 | error_report("Invalid PCI requester ID cache type: %d", |
4a94b3aa PX |
1004 | cache->type); |
1005 | exit(1); | |
1006 | break; | |
1007 | } | |
1008 | ||
1009 | return result; | |
1010 | } | |
1011 | ||
1012 | /* Parse bridges up to the root complex and return requester ID | |
1013 | * cache for specific device. For full PCIe topology, the cache | |
1014 | * result would be exactly the same as getting BDF of the device. | |
1015 | * However, several tricks are required when system mixed up with | |
1016 | * legacy PCI devices and PCIe-to-PCI bridges. | |
1017 | * | |
1018 | * Here we cache the proxy device (and type) not requester ID since | |
1019 | * bus number might change from time to time. | |
1020 | */ | |
1021 | static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) | |
1022 | { | |
1023 | PCIDevice *parent; | |
1024 | PCIReqIDCache cache = { | |
1025 | .dev = dev, | |
1026 | .type = PCI_REQ_ID_BDF, | |
1027 | }; | |
1028 | ||
fd56e061 | 1029 | while (!pci_bus_is_root(pci_get_bus(dev))) { |
4a94b3aa | 1030 | /* We are under PCI/PCIe bridges */ |
fd56e061 | 1031 | parent = pci_get_bus(dev)->parent_dev; |
4a94b3aa PX |
1032 | if (pci_is_express(parent)) { |
1033 | if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
1034 | /* When we pass through PCIe-to-PCI/PCIX bridges, we | |
1035 | * override the requester ID using secondary bus | |
1036 | * number of parent bridge with zeroed devfn | |
1037 | * (pcie-to-pci bridge spec chap 2.3). */ | |
1038 | cache.type = PCI_REQ_ID_SECONDARY_BUS; | |
1039 | cache.dev = dev; | |
1040 | } | |
1041 | } else { | |
1042 | /* Legacy PCI, override requester ID with the bridge's | |
1043 | * BDF upstream. When the root complex connects to | |
1044 | * legacy PCI devices (including buses), it can only | |
1045 | * obtain requester ID info from directly attached | |
1046 | * devices. If devices are attached under bridges, only | |
1047 | * the requester ID of the bridge that is directly | |
1048 | * attached to the root complex can be recognized. */ | |
1049 | cache.type = PCI_REQ_ID_BDF; | |
1050 | cache.dev = parent; | |
1051 | } | |
1052 | dev = parent; | |
1053 | } | |
1054 | ||
1055 | return cache; | |
1056 | } | |
1057 | ||
1058 | uint16_t pci_requester_id(PCIDevice *dev) | |
1059 | { | |
1060 | return pci_req_id_cache_extract(&dev->requester_id_cache); | |
1061 | } | |
1062 | ||
9b717a3a MCA |
1063 | static bool pci_bus_devfn_available(PCIBus *bus, int devfn) |
1064 | { | |
1065 | return !(bus->devices[devfn]); | |
1066 | } | |
1067 | ||
8b884984 MCA |
1068 | static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) |
1069 | { | |
1070 | return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); | |
1071 | } | |
1072 | ||
69b91039 | 1073 | /* -1 for devfn means auto assign */ |
fd56e061 | 1074 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, |
133e9b22 MA |
1075 | const char *name, int devfn, |
1076 | Error **errp) | |
69b91039 | 1077 | { |
40021f08 AL |
1078 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
1079 | PCIConfigReadFunc *config_read = pc->config_read; | |
1080 | PCIConfigWriteFunc *config_write = pc->config_write; | |
133e9b22 | 1081 | Error *local_err = NULL; |
3f1e1478 | 1082 | DeviceState *dev = DEVICE(pci_dev); |
fd56e061 | 1083 | PCIBus *bus = pci_get_bus(pci_dev); |
3f1e1478 | 1084 | |
0144f6f1 MA |
1085 | /* Only pci bridges can be attached to extra PCI root buses */ |
1086 | if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { | |
1087 | error_setg(errp, | |
1088 | "PCI: Only PCI/PCIe bridges can be plugged into %s", | |
1089 | bus->parent_dev->name); | |
1090 | return NULL; | |
1091 | } | |
113f89df | 1092 | |
69b91039 | 1093 | if (devfn < 0) { |
b47b0706 | 1094 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 1095 | devfn += PCI_FUNC_MAX) { |
8b884984 MCA |
1096 | if (pci_bus_devfn_available(bus, devfn) && |
1097 | !pci_bus_devfn_reserved(bus, devfn)) { | |
69b91039 | 1098 | goto found; |
9b717a3a | 1099 | } |
69b91039 | 1100 | } |
8b884984 MCA |
1101 | error_setg(errp, "PCI: no slot/function available for %s, all in use " |
1102 | "or reserved", name); | |
09e3acc6 | 1103 | return NULL; |
69b91039 | 1104 | found: ; |
8b884984 MCA |
1105 | } else if (pci_bus_devfn_reserved(bus, devfn)) { |
1106 | error_setg(errp, "PCI: slot %d function %d not available for %s," | |
1107 | " reserved", | |
1108 | PCI_SLOT(devfn), PCI_FUNC(devfn), name); | |
1109 | return NULL; | |
9b717a3a | 1110 | } else if (!pci_bus_devfn_available(bus, devfn)) { |
133e9b22 | 1111 | error_setg(errp, "PCI: slot %d function %d not available for %s," |
ad003b9e | 1112 | " in use by %s,id=%s", |
133e9b22 | 1113 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, |
ad003b9e | 1114 | bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); |
09e3acc6 | 1115 | return NULL; |
3f1e1478 | 1116 | } else if (dev->hotplugged && |
7c0fa8df | 1117 | !pci_is_vf(pci_dev) && |
3f1e1478 | 1118 | pci_get_function_0(pci_dev)) { |
3298bbce | 1119 | error_setg(errp, "PCI: slot %d function 0 already occupied by %s," |
3f1e1478 | 1120 | " new func %s cannot be exposed to guest.", |
d93ddfb1 MT |
1121 | PCI_SLOT(pci_get_function_0(pci_dev)->devfn), |
1122 | pci_get_function_0(pci_dev)->name, | |
3f1e1478 C |
1123 | name); |
1124 | ||
1125 | return NULL; | |
69b91039 | 1126 | } |
e00387d5 | 1127 | |
efc8188e | 1128 | pci_dev->devfn = devfn; |
4a94b3aa | 1129 | pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); |
d06bce95 | 1130 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); |
e00387d5 | 1131 | |
3716d590 JW |
1132 | memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), |
1133 | "bus master container", UINT64_MAX); | |
1134 | address_space_init(&pci_dev->bus_master_as, | |
1135 | &pci_dev->bus_master_container_region, pci_dev->name); | |
1136 | ||
2f181fbd | 1137 | if (phase_check(PHASE_MACHINE_READY)) { |
b86eacb8 MA |
1138 | pci_init_bus_master(pci_dev); |
1139 | } | |
d036bb21 | 1140 | pci_dev->irq_state = 0; |
a9f49946 | 1141 | pci_config_alloc(pci_dev); |
fb231628 | 1142 | |
40021f08 AL |
1143 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
1144 | pci_config_set_device_id(pci_dev->config, pc->device_id); | |
1145 | pci_config_set_revision(pci_dev->config, pc->revision); | |
1146 | pci_config_set_class(pci_dev->config, pc->class_id); | |
113f89df | 1147 | |
40021f08 AL |
1148 | if (!pc->is_bridge) { |
1149 | if (pc->subsystem_vendor_id || pc->subsystem_id) { | |
113f89df | 1150 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
40021f08 | 1151 | pc->subsystem_vendor_id); |
113f89df | 1152 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
40021f08 | 1153 | pc->subsystem_id); |
113f89df IY |
1154 | } else { |
1155 | pci_set_default_subsystem_id(pci_dev); | |
1156 | } | |
1157 | } else { | |
1158 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
40021f08 AL |
1159 | assert(!pc->subsystem_vendor_id); |
1160 | assert(!pc->subsystem_id); | |
fb231628 | 1161 | } |
bd4b65ee | 1162 | pci_init_cmask(pci_dev); |
b7ee1603 | 1163 | pci_init_wmask(pci_dev); |
89d437df | 1164 | pci_init_w1cmask(pci_dev); |
40021f08 | 1165 | if (pc->is_bridge) { |
d5f27e88 | 1166 | pci_init_mask_bridge(pci_dev); |
fb231628 | 1167 | } |
133e9b22 MA |
1168 | pci_init_multifunction(bus, pci_dev, &local_err); |
1169 | if (local_err) { | |
1170 | error_propagate(errp, local_err); | |
30607764 | 1171 | do_pci_unregister_device(pci_dev); |
6eab3de1 IY |
1172 | return NULL; |
1173 | } | |
0ac32c83 FB |
1174 | |
1175 | if (!config_read) | |
1176 | config_read = pci_default_read_config; | |
1177 | if (!config_write) | |
1178 | config_write = pci_default_write_config; | |
69b91039 FB |
1179 | pci_dev->config_read = config_read; |
1180 | pci_dev->config_write = config_write; | |
30468f78 | 1181 | bus->devices[devfn] = pci_dev; |
f16c4abf | 1182 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
1183 | return pci_dev; |
1184 | } | |
1185 | ||
5851e08c AL |
1186 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
1187 | { | |
1188 | PCIIORegion *r; | |
1189 | int i; | |
1190 | ||
1191 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
1192 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 1193 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 1194 | continue; |
03952339 | 1195 | memory_region_del_subregion(r->address_space, r->memory); |
5851e08c | 1196 | } |
e01fd687 AW |
1197 | |
1198 | pci_unregister_vga(pci_dev); | |
5851e08c AL |
1199 | } |
1200 | ||
b69c3c21 | 1201 | static void pci_qdev_unrealize(DeviceState *dev) |
5851e08c | 1202 | { |
40021f08 AL |
1203 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
1204 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); | |
5851e08c AL |
1205 | |
1206 | pci_unregister_io_regions(pci_dev); | |
230741dc | 1207 | pci_del_option_rom(pci_dev); |
7cf1b0fd | 1208 | |
f90c2bcd AW |
1209 | if (pc->exit) { |
1210 | pc->exit(pci_dev); | |
1211 | } | |
5851e08c | 1212 | |
3936161f | 1213 | pci_device_deassert_intx(pci_dev); |
925fe64a | 1214 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
1215 | } |
1216 | ||
e824b2cc AK |
1217 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
1218 | uint8_t type, MemoryRegion *memory) | |
69b91039 FB |
1219 | { |
1220 | PCIIORegion *r; | |
5178ecd8 | 1221 | uint32_t addr; /* offset in pci config space */ |
5a9ff381 | 1222 | uint64_t wmask; |
cfc0be25 | 1223 | pcibus_t size = memory_region_size(memory); |
6a5b19ca | 1224 | uint8_t hdr_type; |
a4c20c6a | 1225 | |
7c0fa8df | 1226 | assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ |
2bbb9c2f IY |
1227 | assert(region_num >= 0); |
1228 | assert(region_num < PCI_NUM_REGIONS); | |
2c729dc8 | 1229 | assert(is_power_of_2(size)); |
a4c20c6a | 1230 | |
6a5b19ca BW |
1231 | /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ |
1232 | hdr_type = | |
1233 | pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
1234 | assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); | |
1235 | ||
69b91039 | 1236 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 1237 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
1238 | r->size = size; |
1239 | r->type = type; | |
5178ecd8 C |
1240 | r->memory = memory; |
1241 | r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO | |
fd56e061 DG |
1242 | ? pci_get_bus(pci_dev)->address_space_io |
1243 | : pci_get_bus(pci_dev)->address_space_mem; | |
b7ee1603 MT |
1244 | |
1245 | wmask = ~(size - 1); | |
d7ce493a | 1246 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 1247 | /* ROM enable bit is writable */ |
5330de09 | 1248 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 1249 | } |
5178ecd8 C |
1250 | |
1251 | addr = pci_bar(pci_dev, region_num); | |
b0ff8eb2 | 1252 | pci_set_long(pci_dev->config + addr, type); |
5178ecd8 | 1253 | |
14421258 IY |
1254 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
1255 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1256 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
1257 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
1258 | } else { | |
1259 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
1260 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
1261 | } | |
79ff8cb0 AK |
1262 | } |
1263 | ||
e01fd687 AW |
1264 | static void pci_update_vga(PCIDevice *pci_dev) |
1265 | { | |
1266 | uint16_t cmd; | |
1267 | ||
1268 | if (!pci_dev->has_vga) { | |
1269 | return; | |
1270 | } | |
1271 | ||
1272 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
1273 | ||
1274 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], | |
1275 | cmd & PCI_COMMAND_MEMORY); | |
1276 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], | |
1277 | cmd & PCI_COMMAND_IO); | |
1278 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], | |
1279 | cmd & PCI_COMMAND_IO); | |
1280 | } | |
1281 | ||
1282 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, | |
1283 | MemoryRegion *io_lo, MemoryRegion *io_hi) | |
1284 | { | |
fd56e061 DG |
1285 | PCIBus *bus = pci_get_bus(pci_dev); |
1286 | ||
e01fd687 AW |
1287 | assert(!pci_dev->has_vga); |
1288 | ||
1289 | assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); | |
1290 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; | |
fd56e061 | 1291 | memory_region_add_subregion_overlap(bus->address_space_mem, |
e01fd687 AW |
1292 | QEMU_PCI_VGA_MEM_BASE, mem, 1); |
1293 | ||
1294 | assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); | |
1295 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; | |
fd56e061 | 1296 | memory_region_add_subregion_overlap(bus->address_space_io, |
e01fd687 AW |
1297 | QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); |
1298 | ||
1299 | assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); | |
1300 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; | |
fd56e061 | 1301 | memory_region_add_subregion_overlap(bus->address_space_io, |
e01fd687 AW |
1302 | QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); |
1303 | pci_dev->has_vga = true; | |
1304 | ||
1305 | pci_update_vga(pci_dev); | |
1306 | } | |
1307 | ||
1308 | void pci_unregister_vga(PCIDevice *pci_dev) | |
1309 | { | |
fd56e061 DG |
1310 | PCIBus *bus = pci_get_bus(pci_dev); |
1311 | ||
e01fd687 AW |
1312 | if (!pci_dev->has_vga) { |
1313 | return; | |
1314 | } | |
1315 | ||
fd56e061 | 1316 | memory_region_del_subregion(bus->address_space_mem, |
e01fd687 | 1317 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); |
fd56e061 | 1318 | memory_region_del_subregion(bus->address_space_io, |
e01fd687 | 1319 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); |
fd56e061 | 1320 | memory_region_del_subregion(bus->address_space_io, |
e01fd687 AW |
1321 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); |
1322 | pci_dev->has_vga = false; | |
1323 | } | |
1324 | ||
16a96f28 AK |
1325 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
1326 | { | |
1327 | return pci_dev->io_regions[region_num].addr; | |
1328 | } | |
1329 | ||
7c0fa8df KO |
1330 | static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, |
1331 | uint8_t type, pcibus_t size) | |
1332 | { | |
1333 | pcibus_t new_addr; | |
1334 | if (!pci_is_vf(d)) { | |
1335 | int bar = pci_bar(d, reg); | |
1336 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1337 | new_addr = pci_get_quad(d->config + bar); | |
1338 | } else { | |
1339 | new_addr = pci_get_long(d->config + bar); | |
1340 | } | |
1341 | } else { | |
1342 | PCIDevice *pf = d->exp.sriov_vf.pf; | |
1343 | uint16_t sriov_cap = pf->exp.sriov_cap; | |
1344 | int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; | |
1345 | uint16_t vf_offset = | |
1346 | pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); | |
1347 | uint16_t vf_stride = | |
1348 | pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); | |
1349 | uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; | |
1350 | ||
1351 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1352 | new_addr = pci_get_quad(pf->config + bar); | |
1353 | } else { | |
1354 | new_addr = pci_get_long(pf->config + bar); | |
1355 | } | |
1356 | new_addr += vf_num * size; | |
1357 | } | |
1358 | /* The ROM slot has a specific enable bit, keep it intact */ | |
1359 | if (reg != PCI_ROM_SLOT) { | |
1360 | new_addr &= ~(size - 1); | |
1361 | } | |
1362 | return new_addr; | |
1363 | } | |
1364 | ||
1365 | pcibus_t pci_bar_address(PCIDevice *d, | |
1366 | int reg, uint8_t type, pcibus_t size) | |
876a350d MT |
1367 | { |
1368 | pcibus_t new_addr, last_addr; | |
876a350d | 1369 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
e4024630 LV |
1370 | Object *machine = qdev_get_machine(); |
1371 | ObjectClass *oc = object_get_class(machine); | |
1372 | MachineClass *mc = MACHINE_CLASS(oc); | |
1373 | bool allow_0_address = mc->pci_allow_0_address; | |
876a350d MT |
1374 | |
1375 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1376 | if (!(cmd & PCI_COMMAND_IO)) { | |
1377 | return PCI_BAR_UNMAPPED; | |
1378 | } | |
7c0fa8df | 1379 | new_addr = pci_config_get_bar_addr(d, reg, type, size); |
876a350d | 1380 | last_addr = new_addr + size - 1; |
9f1a029a HP |
1381 | /* Check if 32 bit BAR wraps around explicitly. |
1382 | * TODO: make priorities correct and remove this work around. | |
1383 | */ | |
e4024630 LV |
1384 | if (last_addr <= new_addr || last_addr >= UINT32_MAX || |
1385 | (!allow_0_address && new_addr == 0)) { | |
876a350d MT |
1386 | return PCI_BAR_UNMAPPED; |
1387 | } | |
1388 | return new_addr; | |
1389 | } | |
1390 | ||
1391 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
1392 | return PCI_BAR_UNMAPPED; | |
1393 | } | |
7c0fa8df | 1394 | new_addr = pci_config_get_bar_addr(d, reg, type, size); |
876a350d MT |
1395 | /* the ROM slot has a specific enable bit */ |
1396 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
1397 | return PCI_BAR_UNMAPPED; | |
1398 | } | |
1399 | new_addr &= ~(size - 1); | |
1400 | last_addr = new_addr + size - 1; | |
1401 | /* NOTE: we do not support wrapping */ | |
1402 | /* XXX: as we cannot support really dynamic | |
1403 | mappings, we handle specific values as invalid | |
1404 | mappings. */ | |
e4024630 LV |
1405 | if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || |
1406 | (!allow_0_address && new_addr == 0)) { | |
876a350d MT |
1407 | return PCI_BAR_UNMAPPED; |
1408 | } | |
1409 | ||
1410 | /* Now pcibus_t is 64bit. | |
1411 | * Check if 32 bit BAR wraps around explicitly. | |
1412 | * Without this, PC ide doesn't work well. | |
1413 | * TODO: remove this work around. | |
1414 | */ | |
1415 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
1416 | return PCI_BAR_UNMAPPED; | |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * OS is allowed to set BAR beyond its addressable | |
1421 | * bits. For example, 32 bit OS can set 64bit bar | |
1422 | * to >4G. Check it. TODO: we might need to support | |
1423 | * it in the future for e.g. PAE. | |
1424 | */ | |
a8170e5e | 1425 | if (last_addr >= HWADDR_MAX) { |
876a350d MT |
1426 | return PCI_BAR_UNMAPPED; |
1427 | } | |
1428 | ||
1429 | return new_addr; | |
1430 | } | |
1431 | ||
0ac32c83 FB |
1432 | static void pci_update_mappings(PCIDevice *d) |
1433 | { | |
1434 | PCIIORegion *r; | |
876a350d | 1435 | int i; |
7df32ca0 | 1436 | pcibus_t new_addr; |
3b46e624 | 1437 | |
8a8696a3 | 1438 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1439 | r = &d->io_regions[i]; |
a9688570 IY |
1440 | |
1441 | /* this region isn't registered */ | |
ec503442 | 1442 | if (!r->size) |
a9688570 IY |
1443 | continue; |
1444 | ||
876a350d | 1445 | new_addr = pci_bar_address(d, i, r->type, r->size); |
23786d13 GH |
1446 | if (!d->has_power) { |
1447 | new_addr = PCI_BAR_UNMAPPED; | |
1448 | } | |
a9688570 IY |
1449 | |
1450 | /* This bar isn't changed */ | |
7df32ca0 | 1451 | if (new_addr == r->addr) |
a9688570 IY |
1452 | continue; |
1453 | ||
1454 | /* now do the real mapping */ | |
1455 | if (r->addr != PCI_BAR_UNMAPPED) { | |
deeb956c | 1456 | trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), |
7828d750 | 1457 | PCI_SLOT(d->devfn), |
0f288f85 | 1458 | PCI_FUNC(d->devfn), |
7828d750 | 1459 | i, r->addr, r->size); |
03952339 | 1460 | memory_region_del_subregion(r->address_space, r->memory); |
0ac32c83 | 1461 | } |
a9688570 IY |
1462 | r->addr = new_addr; |
1463 | if (r->addr != PCI_BAR_UNMAPPED) { | |
deeb956c | 1464 | trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), |
7828d750 | 1465 | PCI_SLOT(d->devfn), |
0f288f85 | 1466 | PCI_FUNC(d->devfn), |
7828d750 | 1467 | i, r->addr, r->size); |
8b881e77 AK |
1468 | memory_region_add_subregion_overlap(r->address_space, |
1469 | r->addr, r->memory, 1); | |
a9688570 | 1470 | } |
0ac32c83 | 1471 | } |
e01fd687 AW |
1472 | |
1473 | pci_update_vga(d); | |
0ac32c83 FB |
1474 | } |
1475 | ||
a7b15a5c MT |
1476 | static inline int pci_irq_disabled(PCIDevice *d) |
1477 | { | |
1478 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1479 | } | |
1480 | ||
1481 | /* Called after interrupt disabled field update in config space, | |
1482 | * assert/deassert interrupts if necessary. | |
1483 | * Gets original interrupt disable bit value (before update). */ | |
1484 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1485 | { | |
1486 | int i, disabled = pci_irq_disabled(d); | |
1487 | if (disabled == was_irq_disabled) | |
1488 | return; | |
1489 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1490 | int state = pci_irq_state(d, i); | |
1491 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1492 | } | |
1493 | } | |
1494 | ||
5fafdf24 | 1495 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1496 | uint32_t address, int len) |
69b91039 | 1497 | { |
5029fe12 | 1498 | uint32_t val = 0; |
42e4126b | 1499 | |
f7d6a635 PP |
1500 | assert(address + len <= pci_config_size(d)); |
1501 | ||
727b4866 AW |
1502 | if (pci_is_express_downstream_port(d) && |
1503 | ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { | |
1504 | pcie_sync_bridge_lnk(d); | |
1505 | } | |
5029fe12 IY |
1506 | memcpy(&val, d->config + address, len); |
1507 | return le32_to_cpu(val); | |
0ac32c83 FB |
1508 | } |
1509 | ||
d7efb7e0 | 1510 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) |
0ac32c83 | 1511 | { |
a7b15a5c | 1512 | int i, was_irq_disabled = pci_irq_disabled(d); |
d7efb7e0 | 1513 | uint32_t val = val_in; |
0ac32c83 | 1514 | |
f7d6a635 PP |
1515 | assert(addr + l <= pci_config_size(d)); |
1516 | ||
42e4126b | 1517 | for (i = 0; i < l; val >>= 8, ++i) { |
91011d4f | 1518 | uint8_t wmask = d->wmask[addr + i]; |
92ba5f51 IY |
1519 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1520 | assert(!(wmask & w1cmask)); | |
91011d4f | 1521 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1522 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1523 | } |
260c0cd3 | 1524 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1525 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1526 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1527 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1528 | pci_update_mappings(d); |
a7b15a5c | 1529 | |
1c380f94 | 1530 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
a7b15a5c | 1531 | pci_update_irq_disabled(d, was_irq_disabled); |
1c380f94 | 1532 | memory_region_set_enabled(&d->bus_master_enable_region, |
23786d13 GH |
1533 | (pci_get_word(d->config + PCI_COMMAND) |
1534 | & PCI_COMMAND_MASTER) && d->has_power); | |
1c380f94 | 1535 | } |
95d65800 | 1536 | |
d7efb7e0 KO |
1537 | msi_write_config(d, addr, val_in, l); |
1538 | msix_write_config(d, addr, val_in, l); | |
7c0fa8df | 1539 | pcie_sriov_config_write(d, addr, val_in, l); |
69b91039 FB |
1540 | } |
1541 | ||
502a5395 PB |
1542 | /***********************************************************/ |
1543 | /* generic PCI irq support */ | |
30468f78 | 1544 | |
502a5395 | 1545 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d98f08f5 | 1546 | static void pci_irq_handler(void *opaque, int irq_num, int level) |
69b91039 | 1547 | { |
a60380a5 | 1548 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1549 | int change; |
3b46e624 | 1550 | |
8ddf5432 IY |
1551 | assert(0 <= irq_num && irq_num < PCI_NUM_PINS); |
1552 | assert(level == 0 || level == 1); | |
d036bb21 | 1553 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1554 | if (!change) |
1555 | return; | |
d2b59317 | 1556 | |
d036bb21 | 1557 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1558 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1559 | if (pci_irq_disabled(pci_dev)) |
1560 | return; | |
d036bb21 | 1561 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1562 | } |
1563 | ||
d98f08f5 MA |
1564 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev) |
1565 | { | |
1566 | int intx = pci_intx(pci_dev); | |
8ddf5432 | 1567 | assert(0 <= intx && intx < PCI_NUM_PINS); |
d98f08f5 MA |
1568 | |
1569 | return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); | |
1570 | } | |
1571 | ||
1572 | void pci_set_irq(PCIDevice *pci_dev, int level) | |
1573 | { | |
1574 | int intx = pci_intx(pci_dev); | |
1575 | pci_irq_handler(pci_dev, intx, level); | |
1576 | } | |
1577 | ||
3afa9bb4 MT |
1578 | /* Special hooks used by device assignment */ |
1579 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) | |
1580 | { | |
0889464a | 1581 | assert(pci_bus_is_root(bus)); |
3afa9bb4 MT |
1582 | bus->route_intx_to_irq = route_intx_to_irq; |
1583 | } | |
1584 | ||
1585 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) | |
1586 | { | |
1587 | PCIBus *bus; | |
1588 | ||
1589 | do { | |
fd56e061 DG |
1590 | bus = pci_get_bus(dev); |
1591 | pin = bus->map_irq(dev, pin); | |
1592 | dev = bus->parent_dev; | |
3afa9bb4 | 1593 | } while (dev); |
05c0621e AW |
1594 | |
1595 | if (!bus->route_intx_to_irq) { | |
312fd5f2 | 1596 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", |
05c0621e AW |
1597 | object_get_typename(OBJECT(bus->qbus.parent))); |
1598 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; | |
1599 | } | |
1600 | ||
3afa9bb4 | 1601 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
0ae16251 JK |
1602 | } |
1603 | ||
d6e65d54 AW |
1604 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1605 | { | |
1606 | return old->mode != new->mode || old->irq != new->irq; | |
1607 | } | |
1608 | ||
0ae16251 JK |
1609 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1610 | { | |
1611 | PCIDevice *dev; | |
1612 | PCIBus *sec; | |
1613 | int i; | |
1614 | ||
1615 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1616 | dev = bus->devices[i]; | |
1617 | if (dev && dev->intx_routing_notifier) { | |
1618 | dev->intx_routing_notifier(dev); | |
1619 | } | |
e5368f0d AW |
1620 | } |
1621 | ||
1622 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1623 | pci_bus_fire_intx_routing_notifier(sec); | |
0ae16251 JK |
1624 | } |
1625 | } | |
1626 | ||
1627 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
1628 | PCIINTxRoutingNotifier notifier) | |
1629 | { | |
1630 | dev->intx_routing_notifier = notifier; | |
69b91039 FB |
1631 | } |
1632 | ||
91e56159 IY |
1633 | /* |
1634 | * PCI-to-PCI bridge specification | |
1635 | * 9.1: Interrupt routing. Table 9-1 | |
1636 | * | |
1637 | * the PCI Express Base Specification, Revision 2.1 | |
1638 | * 2.2.8.1: INTx interrutp signaling - Rules | |
1639 | * the Implementation Note | |
1640 | * Table 2-20 | |
1641 | */ | |
1642 | /* | |
1643 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD | |
1644 | * 0-origin unlike PCI interrupt pin register. | |
1645 | */ | |
1646 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) | |
1647 | { | |
e8ec4adf | 1648 | return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); |
91e56159 IY |
1649 | } |
1650 | ||
502a5395 PB |
1651 | /***********************************************************/ |
1652 | /* monitor info on PCI */ | |
0ac32c83 | 1653 | |
6650ee6d PB |
1654 | typedef struct { |
1655 | uint16_t class; | |
1656 | const char *desc; | |
5e0259e7 GN |
1657 | const char *fw_name; |
1658 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1659 | } pci_class_desc; |
1660 | ||
09bc878a | 1661 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1662 | { |
5e0259e7 GN |
1663 | { 0x0001, "VGA controller", "display"}, |
1664 | { 0x0100, "SCSI controller", "scsi"}, | |
1665 | { 0x0101, "IDE controller", "ide"}, | |
1666 | { 0x0102, "Floppy controller", "fdc"}, | |
1667 | { 0x0103, "IPI controller", "ipi"}, | |
1668 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1669 | { 0x0106, "SATA controller"}, |
1670 | { 0x0107, "SAS controller"}, | |
1671 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1672 | { 0x0200, "Ethernet controller", "ethernet"}, |
1673 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1674 | { 0x0202, "FDDI controller", "fddi"}, | |
1675 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1676 | { 0x0280, "Network controller"}, |
5e0259e7 | 1677 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1678 | { 0x0301, "XGA controller"}, |
1679 | { 0x0302, "3D controller"}, | |
1680 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1681 | { 0x0400, "Video controller", "video"}, |
1682 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1683 | { 0x0402, "Phone"}, |
602ef4d9 | 1684 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1685 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1686 | { 0x0500, "RAM controller", "memory"}, |
1687 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1688 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1689 | { 0x0600, "Host bridge", "host"}, |
1690 | { 0x0601, "ISA bridge", "isa"}, | |
1691 | { 0x0602, "EISA bridge", "eisa"}, | |
1692 | { 0x0603, "MC bridge", "mca"}, | |
4c41425d | 1693 | { 0x0604, "PCI bridge", "pci-bridge"}, |
5e0259e7 GN |
1694 | { 0x0605, "PCMCIA bridge", "pcmcia"}, |
1695 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1696 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1697 | { 0x0608, "RACEWAY bridge"}, |
1698 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1699 | { 0x0700, "Serial port", "serial"}, |
1700 | { 0x0701, "Parallel port", "parallel"}, | |
1701 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1702 | { 0x0801, "DMA controller", "dma-controller"}, | |
1703 | { 0x0802, "Timer", "timer"}, | |
1704 | { 0x0803, "RTC", "rtc"}, | |
1705 | { 0x0900, "Keyboard", "keyboard"}, | |
1706 | { 0x0901, "Pen", "pen"}, | |
1707 | { 0x0902, "Mouse", "mouse"}, | |
1708 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1709 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
d1e9e646 | 1710 | { 0x0c00, "Firewire controller", "firewire"}, |
5e0259e7 GN |
1711 | { 0x0c01, "Access bus controller", "access-bus"}, |
1712 | { 0x0c02, "SSA controller", "ssa"}, | |
1713 | { 0x0c03, "USB controller", "usb"}, | |
1714 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
f7748569 | 1715 | { 0x0c05, "SMBus"}, |
6650ee6d PB |
1716 | { 0, NULL} |
1717 | }; | |
1718 | ||
2914fc61 PX |
1719 | void pci_for_each_device_under_bus_reverse(PCIBus *bus, |
1720 | pci_bus_dev_fn fn, | |
1721 | void *opaque) | |
a8eeafda GK |
1722 | { |
1723 | PCIDevice *d; | |
1724 | int devfn; | |
1725 | ||
1726 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1727 | d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; | |
1728 | if (d) { | |
1729 | fn(bus, d, opaque); | |
1730 | } | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | void pci_for_each_device_reverse(PCIBus *bus, int bus_num, | |
b3dcf94f | 1735 | pci_bus_dev_fn fn, void *opaque) |
a8eeafda GK |
1736 | { |
1737 | bus = pci_find_bus_nr(bus, bus_num); | |
1738 | ||
1739 | if (bus) { | |
1740 | pci_for_each_device_under_bus_reverse(bus, fn, opaque); | |
1741 | } | |
1742 | } | |
1743 | ||
2914fc61 PX |
1744 | void pci_for_each_device_under_bus(PCIBus *bus, |
1745 | pci_bus_dev_fn fn, void *opaque) | |
30468f78 | 1746 | { |
163c8a59 LC |
1747 | PCIDevice *d; |
1748 | int devfn; | |
30468f78 | 1749 | |
163c8a59 LC |
1750 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1751 | d = bus->devices[devfn]; | |
1752 | if (d) { | |
7aa8cbb9 | 1753 | fn(bus, d, opaque); |
163c8a59 LC |
1754 | } |
1755 | } | |
1756 | } | |
1757 | ||
1758 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
b3dcf94f | 1759 | pci_bus_dev_fn fn, void *opaque) |
163c8a59 | 1760 | { |
d662210a | 1761 | bus = pci_find_bus_nr(bus, bus_num); |
163c8a59 LC |
1762 | |
1763 | if (bus) { | |
7aa8cbb9 | 1764 | pci_for_each_device_under_bus(bus, fn, opaque); |
163c8a59 LC |
1765 | } |
1766 | } | |
1767 | ||
79627472 | 1768 | static const pci_class_desc *get_class_desc(int class) |
163c8a59 | 1769 | { |
79627472 | 1770 | const pci_class_desc *desc; |
163c8a59 | 1771 | |
79627472 LC |
1772 | desc = pci_class_descriptions; |
1773 | while (desc->desc && class != desc->class) { | |
1774 | desc++; | |
30468f78 | 1775 | } |
b4dccd8d | 1776 | |
79627472 LC |
1777 | return desc; |
1778 | } | |
14421258 | 1779 | |
79627472 | 1780 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
163c8a59 | 1781 | |
79627472 LC |
1782 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1783 | { | |
95b3a8c8 | 1784 | PciMemoryRegionList *head = NULL, **tail = &head; |
79627472 | 1785 | int i; |
163c8a59 | 1786 | |
79627472 LC |
1787 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1788 | const PCIIORegion *r = &dev->io_regions[i]; | |
95b3a8c8 | 1789 | PciMemoryRegion *region; |
79627472 LC |
1790 | |
1791 | if (!r->size) { | |
1792 | continue; | |
502a5395 | 1793 | } |
163c8a59 | 1794 | |
79627472 | 1795 | region = g_malloc0(sizeof(*region)); |
163c8a59 | 1796 | |
79627472 | 1797 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
95b3a8c8 | 1798 | region->type = g_strdup("io"); |
79627472 | 1799 | } else { |
95b3a8c8 EB |
1800 | region->type = g_strdup("memory"); |
1801 | region->has_prefetch = true; | |
1802 | region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1803 | region->has_mem_type_64 = true; | |
1804 | region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
d5e4acf7 | 1805 | } |
163c8a59 | 1806 | |
95b3a8c8 EB |
1807 | region->bar = i; |
1808 | region->address = r->addr; | |
1809 | region->size = r->size; | |
163c8a59 | 1810 | |
95b3a8c8 | 1811 | QAPI_LIST_APPEND(tail, region); |
80b3ada7 | 1812 | } |
384d8876 | 1813 | |
79627472 | 1814 | return head; |
163c8a59 LC |
1815 | } |
1816 | ||
79627472 LC |
1817 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1818 | int bus_num) | |
163c8a59 | 1819 | { |
79627472 | 1820 | PciBridgeInfo *info; |
9fa02cd1 | 1821 | PciMemoryRange *range; |
163c8a59 | 1822 | |
9fa02cd1 | 1823 | info = g_new0(PciBridgeInfo, 1); |
163c8a59 | 1824 | |
9fa02cd1 EB |
1825 | info->bus = g_new0(PciBusInfo, 1); |
1826 | info->bus->number = dev->config[PCI_PRIMARY_BUS]; | |
1827 | info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; | |
1828 | info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
163c8a59 | 1829 | |
9fa02cd1 EB |
1830 | range = info->bus->io_range = g_new0(PciMemoryRange, 1); |
1831 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
1832 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
163c8a59 | 1833 | |
9fa02cd1 EB |
1834 | range = info->bus->memory_range = g_new0(PciMemoryRange, 1); |
1835 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
1836 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
163c8a59 | 1837 | |
9fa02cd1 EB |
1838 | range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); |
1839 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1840 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
163c8a59 | 1841 | |
79627472 | 1842 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
d662210a | 1843 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
79627472 LC |
1844 | if (child_bus) { |
1845 | info->has_devices = true; | |
1846 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); | |
1847 | } | |
163c8a59 LC |
1848 | } |
1849 | ||
79627472 | 1850 | return info; |
163c8a59 LC |
1851 | } |
1852 | ||
79627472 LC |
1853 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1854 | int bus_num) | |
163c8a59 | 1855 | { |
79627472 LC |
1856 | const pci_class_desc *desc; |
1857 | PciDeviceInfo *info; | |
b5937f29 | 1858 | uint8_t type; |
79627472 | 1859 | int class; |
163c8a59 | 1860 | |
9fa02cd1 | 1861 | info = g_new0(PciDeviceInfo, 1); |
79627472 LC |
1862 | info->bus = bus_num; |
1863 | info->slot = PCI_SLOT(dev->devfn); | |
1864 | info->function = PCI_FUNC(dev->devfn); | |
1865 | ||
9fa02cd1 | 1866 | info->class_info = g_new0(PciDeviceClass, 1); |
79627472 | 1867 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
9fa02cd1 | 1868 | info->class_info->q_class = class; |
79627472 LC |
1869 | desc = get_class_desc(class); |
1870 | if (desc->desc) { | |
9fa02cd1 EB |
1871 | info->class_info->has_desc = true; |
1872 | info->class_info->desc = g_strdup(desc->desc); | |
79627472 LC |
1873 | } |
1874 | ||
9fa02cd1 EB |
1875 | info->id = g_new0(PciDeviceId, 1); |
1876 | info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); | |
1877 | info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); | |
79627472 LC |
1878 | info->regions = qmp_query_pci_regions(dev); |
1879 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); | |
163c8a59 | 1880 | |
12fcf49c | 1881 | info->irq_pin = dev->config[PCI_INTERRUPT_PIN]; |
163c8a59 | 1882 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { |
79627472 LC |
1883 | info->has_irq = true; |
1884 | info->irq = dev->config[PCI_INTERRUPT_LINE]; | |
163c8a59 LC |
1885 | } |
1886 | ||
b5937f29 IY |
1887 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1888 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
79627472 LC |
1889 | info->has_pci_bridge = true; |
1890 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); | |
18613dc6 DL |
1891 | } else if (type == PCI_HEADER_TYPE_NORMAL) { |
1892 | info->id->has_subsystem = info->id->has_subsystem_vendor = true; | |
1893 | info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); | |
1894 | info->id->subsystem_vendor = | |
1895 | pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); | |
1896 | } else if (type == PCI_HEADER_TYPE_CARDBUS) { | |
1897 | info->id->has_subsystem = info->id->has_subsystem_vendor = true; | |
1898 | info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); | |
1899 | info->id->subsystem_vendor = | |
1900 | pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); | |
163c8a59 LC |
1901 | } |
1902 | ||
79627472 | 1903 | return info; |
163c8a59 LC |
1904 | } |
1905 | ||
79627472 | 1906 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
384d8876 | 1907 | { |
95b3a8c8 | 1908 | PciDeviceInfoList *head = NULL, **tail = &head; |
163c8a59 | 1909 | PCIDevice *dev; |
79627472 | 1910 | int devfn; |
163c8a59 LC |
1911 | |
1912 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1913 | dev = bus->devices[devfn]; | |
1914 | if (dev) { | |
95b3a8c8 | 1915 | QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num)); |
163c8a59 | 1916 | } |
1074df4f | 1917 | } |
163c8a59 | 1918 | |
79627472 | 1919 | return head; |
1074df4f IY |
1920 | } |
1921 | ||
79627472 | 1922 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1074df4f | 1923 | { |
79627472 LC |
1924 | PciInfo *info = NULL; |
1925 | ||
d662210a | 1926 | bus = pci_find_bus_nr(bus, bus_num); |
502a5395 | 1927 | if (bus) { |
79627472 LC |
1928 | info = g_malloc0(sizeof(*info)); |
1929 | info->bus = bus_num; | |
1930 | info->devices = qmp_query_pci_devices(bus, bus_num); | |
f2aa58c6 | 1931 | } |
163c8a59 | 1932 | |
79627472 | 1933 | return info; |
f2aa58c6 FB |
1934 | } |
1935 | ||
79627472 | 1936 | PciInfoList *qmp_query_pci(Error **errp) |
f2aa58c6 | 1937 | { |
95b3a8c8 | 1938 | PciInfoList *head = NULL, **tail = &head; |
7588e2b0 | 1939 | PCIHostState *host_bridge; |
163c8a59 | 1940 | |
7588e2b0 | 1941 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
95b3a8c8 EB |
1942 | QAPI_LIST_APPEND(tail, |
1943 | qmp_query_pci_bus(host_bridge->bus, | |
1944 | pci_bus_num(host_bridge->bus))); | |
e822a52a | 1945 | } |
163c8a59 | 1946 | |
79627472 | 1947 | return head; |
77d4bc34 | 1948 | } |
a41b2ff2 PB |
1949 | |
1950 | /* Initialize a PCI NIC. */ | |
51f7cb97 | 1951 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
6dbcb819 | 1952 | const char *default_model, |
51f7cb97 | 1953 | const char *default_devaddr) |
a41b2ff2 | 1954 | { |
5607c388 | 1955 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
52310c3f PB |
1956 | GSList *list; |
1957 | GPtrArray *pci_nic_models; | |
07caea31 | 1958 | PCIBus *bus; |
5607c388 | 1959 | PCIDevice *pci_dev; |
9d07d757 | 1960 | DeviceState *dev; |
51f7cb97 | 1961 | int devfn; |
cb457d76 | 1962 | int i; |
2ad778b8 DG |
1963 | int dom, busnr; |
1964 | unsigned slot; | |
cb457d76 | 1965 | |
52310c3f PB |
1966 | if (nd->model && !strcmp(nd->model, "virtio")) { |
1967 | g_free(nd->model); | |
1968 | nd->model = g_strdup("virtio-net-pci"); | |
1969 | } | |
1970 | ||
1971 | list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); | |
1972 | pci_nic_models = g_ptr_array_new(); | |
1973 | while (list) { | |
1974 | DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, | |
1975 | TYPE_DEVICE); | |
1976 | GSList *next; | |
1977 | if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && | |
1978 | dc->user_creatable) { | |
1979 | const char *name = object_class_get_name(list->data); | |
00823980 TH |
1980 | /* |
1981 | * A network device might also be something else than a NIC, see | |
1982 | * e.g. the "rocker" device. Thus we have to look for the "netdev" | |
1983 | * property, too. Unfortunately, some devices like virtio-net only | |
1984 | * create this property during instance_init, so we have to create | |
1985 | * a temporary instance here to be able to check it. | |
1986 | */ | |
1987 | Object *obj = object_new_with_class(OBJECT_CLASS(dc)); | |
efba1595 | 1988 | if (object_property_find(obj, "netdev")) { |
00823980 TH |
1989 | g_ptr_array_add(pci_nic_models, (gpointer)name); |
1990 | } | |
1991 | object_unref(obj); | |
52310c3f PB |
1992 | } |
1993 | next = list->next; | |
1994 | g_slist_free_1(list); | |
1995 | list = next; | |
1996 | } | |
1997 | g_ptr_array_add(pci_nic_models, NULL); | |
1998 | ||
1999 | if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { | |
51f7cb97 TH |
2000 | exit(0); |
2001 | } | |
2002 | ||
52310c3f PB |
2003 | i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, |
2004 | default_model); | |
51f7cb97 TH |
2005 | if (i < 0) { |
2006 | exit(1); | |
2007 | } | |
07caea31 | 2008 | |
2ad778b8 DG |
2009 | if (!rootbus) { |
2010 | error_report("No primary PCI bus"); | |
2011 | exit(1); | |
2012 | } | |
2013 | ||
2014 | assert(!rootbus->parent_dev); | |
2015 | ||
2016 | if (!devaddr) { | |
2017 | devfn = -1; | |
2018 | busnr = 0; | |
2019 | } else { | |
2020 | if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { | |
2021 | error_report("Invalid PCI device address %s for device %s", | |
2022 | devaddr, nd->model); | |
2023 | exit(1); | |
2024 | } | |
2025 | ||
2026 | if (dom != 0) { | |
2027 | error_report("No support for non-zero PCI domains"); | |
2028 | exit(1); | |
2029 | } | |
2030 | ||
2031 | devfn = PCI_DEVFN(slot, 0); | |
2032 | } | |
2033 | ||
2034 | bus = pci_find_bus_nr(rootbus, busnr); | |
07caea31 | 2035 | if (!bus) { |
1ecda02b | 2036 | error_report("Invalid PCI device address %s for device %s", |
52310c3f | 2037 | devaddr, nd->model); |
51f7cb97 | 2038 | exit(1); |
07caea31 MA |
2039 | } |
2040 | ||
9307d06d | 2041 | pci_dev = pci_new(devfn, nd->model); |
9ee05825 | 2042 | dev = &pci_dev->qdev; |
1cc33683 | 2043 | qdev_set_nic_properties(dev, nd); |
9307d06d | 2044 | pci_realize_and_unref(pci_dev, bus, &error_fatal); |
52310c3f | 2045 | g_ptr_array_free(pci_nic_models, true); |
51f7cb97 | 2046 | return pci_dev; |
07caea31 MA |
2047 | } |
2048 | ||
129d42fb AJ |
2049 | PCIDevice *pci_vga_init(PCIBus *bus) |
2050 | { | |
f9bcb2d6 | 2051 | vga_interface_created = true; |
129d42fb AJ |
2052 | switch (vga_interface_type) { |
2053 | case VGA_CIRRUS: | |
2054 | return pci_create_simple(bus, -1, "cirrus-vga"); | |
2055 | case VGA_QXL: | |
2056 | return pci_create_simple(bus, -1, "qxl-vga"); | |
2057 | case VGA_STD: | |
2058 | return pci_create_simple(bus, -1, "VGA"); | |
2059 | case VGA_VMWARE: | |
2060 | return pci_create_simple(bus, -1, "vmware-svga"); | |
a94f0c5c GH |
2061 | case VGA_VIRTIO: |
2062 | return pci_create_simple(bus, -1, "virtio-vga"); | |
129d42fb AJ |
2063 | case VGA_NONE: |
2064 | default: /* Other non-PCI types. Checking for unsupported types is already | |
2065 | done in vl.c. */ | |
2066 | return NULL; | |
2067 | } | |
2068 | } | |
2069 | ||
929176c3 MT |
2070 | /* Whether a given bus number is in range of the secondary |
2071 | * bus of the given bridge device. */ | |
2072 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
2073 | { | |
2074 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
2075 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
09e5b819 | 2076 | dev->config[PCI_SECONDARY_BUS] <= bus_num && |
929176c3 MT |
2077 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; |
2078 | } | |
2079 | ||
09e5b819 MA |
2080 | /* Whether a given bus number is in a range of a root bus */ |
2081 | static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) | |
2082 | { | |
2083 | int i; | |
2084 | ||
2085 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
2086 | PCIDevice *dev = bus->devices[i]; | |
2087 | ||
2088 | if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { | |
2089 | if (pci_secondary_bus_in_range(dev, bus_num)) { | |
2090 | return true; | |
2091 | } | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | return false; | |
2096 | } | |
2097 | ||
d662210a | 2098 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
3ae80618 | 2099 | { |
470e6363 | 2100 | PCIBus *sec; |
3ae80618 | 2101 | |
470e6363 | 2102 | if (!bus) { |
e822a52a | 2103 | return NULL; |
470e6363 | 2104 | } |
3ae80618 | 2105 | |
e822a52a IY |
2106 | if (pci_bus_num(bus) == bus_num) { |
2107 | return bus; | |
2108 | } | |
2109 | ||
929176c3 | 2110 | /* Consider all bus numbers in range for the host pci bridge. */ |
0889464a | 2111 | if (!pci_bus_is_root(bus) && |
929176c3 MT |
2112 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
2113 | return NULL; | |
2114 | } | |
2115 | ||
e822a52a | 2116 | /* try child bus */ |
929176c3 MT |
2117 | for (; bus; bus = sec) { |
2118 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
09e5b819 | 2119 | if (pci_bus_num(sec) == bus_num) { |
929176c3 MT |
2120 | return sec; |
2121 | } | |
09e5b819 MA |
2122 | /* PXB buses assumed to be children of bus 0 */ |
2123 | if (pci_bus_is_root(sec)) { | |
2124 | if (pci_root_bus_in_range(sec, bus_num)) { | |
2125 | break; | |
2126 | } | |
2127 | } else { | |
2128 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
2129 | break; | |
2130 | } | |
c021f8e6 | 2131 | } |
e822a52a IY |
2132 | } |
2133 | } | |
2134 | ||
2135 | return NULL; | |
3ae80618 AL |
2136 | } |
2137 | ||
b3dcf94f PX |
2138 | void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, |
2139 | pci_bus_fn end, void *parent_state) | |
eb0acfdd MT |
2140 | { |
2141 | PCIBus *sec; | |
2142 | void *state; | |
2143 | ||
2144 | if (!bus) { | |
2145 | return; | |
2146 | } | |
2147 | ||
2148 | if (begin) { | |
2149 | state = begin(bus, parent_state); | |
2150 | } else { | |
2151 | state = parent_state; | |
2152 | } | |
2153 | ||
2154 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
2155 | pci_for_each_bus_depth_first(sec, begin, end, state); | |
2156 | } | |
2157 | ||
2158 | if (end) { | |
2159 | end(bus, state); | |
2160 | } | |
2161 | } | |
2162 | ||
2163 | ||
5256d8bf | 2164 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 2165 | { |
d662210a | 2166 | bus = pci_find_bus_nr(bus, bus_num); |
3ae80618 AL |
2167 | |
2168 | if (!bus) | |
2169 | return NULL; | |
2170 | ||
5256d8bf | 2171 | return bus->devices[devfn]; |
3ae80618 AL |
2172 | } |
2173 | ||
133e9b22 | 2174 | static void pci_qdev_realize(DeviceState *qdev, Error **errp) |
6b1b92d3 PB |
2175 | { |
2176 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
40021f08 | 2177 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
d61a363d | 2178 | ObjectClass *klass = OBJECT_CLASS(pc); |
133e9b22 | 2179 | Error *local_err = NULL; |
ab85ceb1 | 2180 | bool is_default_rom; |
4f5b6a05 | 2181 | uint16_t class_id; |
6b1b92d3 | 2182 | |
08b1df8f PB |
2183 | if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) { |
2184 | error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); | |
2185 | return; | |
2186 | } | |
2187 | ||
d61a363d YB |
2188 | /* initialize cap_present for pci_is_express() and pci_config_size(), |
2189 | * Note that hybrid PCIs are not set automatically and need to manage | |
2190 | * QEMU_PCI_CAP_EXPRESS manually */ | |
2191 | if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && | |
2192 | !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { | |
a9f49946 IY |
2193 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
2194 | } | |
2195 | ||
cf04aba2 BW |
2196 | if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { |
2197 | pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; | |
2198 | } | |
2199 | ||
fd56e061 | 2200 | pci_dev = do_pci_register_device(pci_dev, |
6e008585 | 2201 | object_get_typename(OBJECT(qdev)), |
133e9b22 | 2202 | pci_dev->devfn, errp); |
09e3acc6 | 2203 | if (pci_dev == NULL) |
133e9b22 | 2204 | return; |
2897ae02 | 2205 | |
7ee6c1e1 MA |
2206 | if (pc->realize) { |
2207 | pc->realize(pci_dev, &local_err); | |
2208 | if (local_err) { | |
2209 | error_propagate(errp, local_err); | |
c2afc922 | 2210 | do_pci_unregister_device(pci_dev); |
133e9b22 | 2211 | return; |
c2afc922 | 2212 | } |
925fe64a | 2213 | } |
8c52c8f3 | 2214 | |
4f5b6a05 JF |
2215 | if (pci_dev->failover_pair_id) { |
2216 | if (!pci_bus_is_express(pci_get_bus(pci_dev))) { | |
2217 | error_setg(errp, "failover primary device must be on " | |
2218 | "PCIExpress bus"); | |
b69c3c21 | 2219 | pci_qdev_unrealize(DEVICE(pci_dev)); |
4f5b6a05 JF |
2220 | return; |
2221 | } | |
2222 | class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); | |
2223 | if (class_id != PCI_CLASS_NETWORK_ETHERNET) { | |
2224 | error_setg(errp, "failover primary device is not an " | |
2225 | "Ethernet device"); | |
b69c3c21 | 2226 | pci_qdev_unrealize(DEVICE(pci_dev)); |
4f5b6a05 JF |
2227 | return; |
2228 | } | |
b01a4901 LV |
2229 | if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) |
2230 | || (PCI_FUNC(pci_dev->devfn) != 0)) { | |
4f5b6a05 JF |
2231 | error_setg(errp, "failover: primary device must be in its own " |
2232 | "PCI slot"); | |
b69c3c21 | 2233 | pci_qdev_unrealize(DEVICE(pci_dev)); |
4f5b6a05 JF |
2234 | return; |
2235 | } | |
a1190ab6 | 2236 | qdev->allow_unplug_during_migration = true; |
4f5b6a05 JF |
2237 | } |
2238 | ||
8c52c8f3 | 2239 | /* rom loading */ |
ab85ceb1 | 2240 | is_default_rom = false; |
40021f08 AL |
2241 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
2242 | pci_dev->romfile = g_strdup(pc->romfile); | |
ab85ceb1 SW |
2243 | is_default_rom = true; |
2244 | } | |
178e785f | 2245 | |
133e9b22 MA |
2246 | pci_add_option_rom(pci_dev, is_default_rom, &local_err); |
2247 | if (local_err) { | |
2248 | error_propagate(errp, local_err); | |
b69c3c21 | 2249 | pci_qdev_unrealize(DEVICE(pci_dev)); |
133e9b22 | 2250 | return; |
178e785f | 2251 | } |
23786d13 GH |
2252 | |
2253 | pci_set_power(pci_dev, true); | |
ee995ffb GH |
2254 | } |
2255 | ||
7411aa63 MA |
2256 | PCIDevice *pci_new_multifunction(int devfn, bool multifunction, |
2257 | const char *name) | |
2258 | { | |
2259 | DeviceState *dev; | |
2260 | ||
2261 | dev = qdev_new(name); | |
2262 | qdev_prop_set_int32(dev, "addr", devfn); | |
2263 | qdev_prop_set_bit(dev, "multifunction", multifunction); | |
2264 | return PCI_DEVICE(dev); | |
2265 | } | |
2266 | ||
2267 | PCIDevice *pci_new(int devfn, const char *name) | |
2268 | { | |
2269 | return pci_new_multifunction(devfn, false, name); | |
2270 | } | |
2271 | ||
2272 | bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) | |
2273 | { | |
2274 | return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); | |
2275 | } | |
2276 | ||
49823868 IY |
2277 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
2278 | bool multifunction, | |
2279 | const char *name) | |
71077c1c | 2280 | { |
9307d06d MA |
2281 | PCIDevice *dev = pci_new_multifunction(devfn, multifunction, name); |
2282 | pci_realize_and_unref(dev, bus, &error_fatal); | |
71077c1c | 2283 | return dev; |
6b1b92d3 | 2284 | } |
6f4cbd39 | 2285 | |
49823868 IY |
2286 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
2287 | { | |
2288 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
2289 | } | |
2290 | ||
b56d701f | 2291 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
6f4cbd39 MT |
2292 | { |
2293 | int offset = PCI_CONFIG_HEADER_SIZE; | |
2294 | int i; | |
b56d701f | 2295 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
6f4cbd39 MT |
2296 | if (pdev->used[i]) |
2297 | offset = i + 1; | |
2298 | else if (i - offset + 1 == size) | |
2299 | return offset; | |
b56d701f | 2300 | } |
6f4cbd39 MT |
2301 | return 0; |
2302 | } | |
2303 | ||
2304 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
2305 | uint8_t *prev_p) | |
2306 | { | |
2307 | uint8_t next, prev; | |
2308 | ||
2309 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
2310 | return 0; | |
2311 | ||
2312 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
2313 | prev = next + PCI_CAP_LIST_NEXT) | |
2314 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
2315 | break; | |
2316 | ||
2317 | if (prev_p) | |
2318 | *prev_p = prev; | |
2319 | return next; | |
2320 | } | |
2321 | ||
c9abe111 JK |
2322 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
2323 | { | |
2324 | uint8_t next, prev, found = 0; | |
2325 | ||
2326 | if (!(pdev->used[offset])) { | |
2327 | return 0; | |
2328 | } | |
2329 | ||
2330 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); | |
2331 | ||
2332 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
2333 | prev = next + PCI_CAP_LIST_NEXT) { | |
2334 | if (next <= offset && next > found) { | |
2335 | found = next; | |
2336 | } | |
2337 | } | |
2338 | return found; | |
2339 | } | |
2340 | ||
ab85ceb1 SW |
2341 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
2342 | This is needed for an option rom which is used for more than one device. */ | |
7c16b5bb | 2343 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) |
ab85ceb1 SW |
2344 | { |
2345 | uint16_t vendor_id; | |
2346 | uint16_t device_id; | |
2347 | uint16_t rom_vendor_id; | |
2348 | uint16_t rom_device_id; | |
2349 | uint16_t rom_magic; | |
2350 | uint16_t pcir_offset; | |
2351 | uint8_t checksum; | |
2352 | ||
2353 | /* Words in rom data are little endian (like in PCI configuration), | |
2354 | so they can be read / written with pci_get_word / pci_set_word. */ | |
2355 | ||
2356 | /* Only a valid rom will be patched. */ | |
2357 | rom_magic = pci_get_word(ptr); | |
2358 | if (rom_magic != 0xaa55) { | |
2359 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
2360 | return; | |
2361 | } | |
2362 | pcir_offset = pci_get_word(ptr + 0x18); | |
2363 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
2364 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
2365 | return; | |
2366 | } | |
2367 | ||
2368 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
2369 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
2370 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
2371 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
2372 | ||
2373 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
2374 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
2375 | ||
2376 | checksum = ptr[6]; | |
2377 | ||
2378 | if (vendor_id != rom_vendor_id) { | |
2379 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
2380 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
2381 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
2382 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
2383 | ptr[6] = checksum; | |
2384 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
2385 | } | |
2386 | ||
2387 | if (device_id != rom_device_id) { | |
2388 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
2389 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
2390 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
2391 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
2392 | ptr[6] = checksum; | |
2393 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
2394 | } | |
2395 | } | |
2396 | ||
c2039bd0 | 2397 | /* Add an option rom for the device */ |
133e9b22 MA |
2398 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, |
2399 | Error **errp) | |
c2039bd0 | 2400 | { |
7c16b5bb | 2401 | int64_t size; |
c2039bd0 AL |
2402 | char *path; |
2403 | void *ptr; | |
1724f049 | 2404 | char name[32]; |
4be9f0d1 | 2405 | const VMStateDescription *vmsd; |
c2039bd0 | 2406 | |
8c52c8f3 | 2407 | if (!pdev->romfile) |
133e9b22 | 2408 | return; |
8c52c8f3 | 2409 | if (strlen(pdev->romfile) == 0) |
133e9b22 | 2410 | return; |
8c52c8f3 | 2411 | |
88169ddf GH |
2412 | if (!pdev->rom_bar) { |
2413 | /* | |
2414 | * Load rom via fw_cfg instead of creating a rom bar, | |
2415 | * for 0.11 compatibility. | |
2416 | */ | |
2417 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
db80c7b9 MA |
2418 | |
2419 | /* | |
2420 | * Hot-plugged devices can't use the option ROM | |
2421 | * if the rom bar is disabled. | |
2422 | */ | |
2423 | if (DEVICE(pdev)->hotplugged) { | |
133e9b22 MA |
2424 | error_setg(errp, "Hot-plugged device without ROM bar" |
2425 | " can't have an option ROM"); | |
2426 | return; | |
db80c7b9 MA |
2427 | } |
2428 | ||
88169ddf GH |
2429 | if (class == 0x0300) { |
2430 | rom_add_vga(pdev->romfile); | |
2431 | } else { | |
2e55e842 | 2432 | rom_add_option(pdev->romfile, -1); |
88169ddf | 2433 | } |
133e9b22 | 2434 | return; |
88169ddf GH |
2435 | } |
2436 | ||
8c52c8f3 | 2437 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 2438 | if (path == NULL) { |
7267c094 | 2439 | path = g_strdup(pdev->romfile); |
c2039bd0 AL |
2440 | } |
2441 | ||
2442 | size = get_image_size(path); | |
8c52c8f3 | 2443 | if (size < 0) { |
133e9b22 | 2444 | error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); |
8c7f3dd0 | 2445 | g_free(path); |
133e9b22 | 2446 | return; |
8c7f3dd0 | 2447 | } else if (size == 0) { |
133e9b22 | 2448 | error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); |
7267c094 | 2449 | g_free(path); |
133e9b22 | 2450 | return; |
7c16b5bb PB |
2451 | } else if (size > 2 * GiB) { |
2452 | error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)", | |
2453 | pdev->romfile); | |
2454 | g_free(path); | |
2455 | return; | |
8c52c8f3 | 2456 | } |
08b1df8f PB |
2457 | if (pdev->romsize != -1) { |
2458 | if (size > pdev->romsize) { | |
2459 | error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size %u", | |
2460 | pdev->romfile, (uint32_t)size, pdev->romsize); | |
2461 | g_free(path); | |
2462 | return; | |
2463 | } | |
2464 | } else { | |
2465 | pdev->romsize = pow2ceil(size); | |
2466 | } | |
c2039bd0 | 2467 | |
4be9f0d1 AL |
2468 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
2469 | ||
2470 | if (vmsd) { | |
2471 | snprintf(name, sizeof(name), "%s.rom", vmsd->name); | |
2472 | } else { | |
f79f2bfc | 2473 | snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
4be9f0d1 | 2474 | } |
14caaf7f | 2475 | pdev->has_rom = true; |
08b1df8f | 2476 | memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, &error_fatal); |
14caaf7f | 2477 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
36bde091 PM |
2478 | if (load_image_size(path, ptr, size) < 0) { |
2479 | error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); | |
2480 | g_free(path); | |
2481 | return; | |
2482 | } | |
7267c094 | 2483 | g_free(path); |
c2039bd0 | 2484 | |
ab85ceb1 SW |
2485 | if (is_default_rom) { |
2486 | /* Only the default rom images will be patched (if needed). */ | |
2487 | pci_patch_ids(pdev, ptr, size); | |
2488 | } | |
2489 | ||
e824b2cc | 2490 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
c2039bd0 AL |
2491 | } |
2492 | ||
230741dc AW |
2493 | static void pci_del_option_rom(PCIDevice *pdev) |
2494 | { | |
14caaf7f | 2495 | if (!pdev->has_rom) |
230741dc AW |
2496 | return; |
2497 | ||
c5705a77 | 2498 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
14caaf7f | 2499 | pdev->has_rom = false; |
230741dc AW |
2500 | } |
2501 | ||
ca77089d | 2502 | /* |
27841278 | 2503 | * On success, pci_add_capability() returns a positive value |
eacbc632 MZ |
2504 | * that the offset of the pci capability. |
2505 | * On failure, it sets an error and returns a negative error | |
2506 | * code. | |
2507 | */ | |
27841278 | 2508 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
cd9aa33e LE |
2509 | uint8_t offset, uint8_t size, |
2510 | Error **errp) | |
6f4cbd39 | 2511 | { |
ca77089d | 2512 | uint8_t *config; |
c9abe111 JK |
2513 | int i, overlapping_cap; |
2514 | ||
ca77089d IY |
2515 | if (!offset) { |
2516 | offset = pci_find_space(pdev, size); | |
97fe42f1 C |
2517 | /* out of PCI config space is programming error */ |
2518 | assert(offset); | |
c9abe111 JK |
2519 | } else { |
2520 | /* Verify that capabilities don't overlap. Note: device assignment | |
2521 | * depends on this check to verify that the device is not broken. | |
2522 | * Should never trigger for emulated devices, but it's helpful | |
2523 | * for debugging these. */ | |
2524 | for (i = offset; i < offset + size; i++) { | |
2525 | overlapping_cap = pci_find_capability_at_offset(pdev, i); | |
2526 | if (overlapping_cap) { | |
cd9aa33e LE |
2527 | error_setg(errp, "%s:%02x:%02x.%x " |
2528 | "Attempt to add PCI capability %x at offset " | |
2529 | "%x overlaps existing capability %x at offset %x", | |
fd56e061 | 2530 | pci_root_bus_path(pdev), pci_dev_bus_num(pdev), |
cd9aa33e LE |
2531 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
2532 | cap_id, offset, overlapping_cap, i); | |
c9abe111 JK |
2533 | return -EINVAL; |
2534 | } | |
2535 | } | |
ca77089d IY |
2536 | } |
2537 | ||
2538 | config = pdev->config + offset; | |
6f4cbd39 MT |
2539 | config[PCI_CAP_LIST_ID] = cap_id; |
2540 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
2541 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
2542 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
e26631b7 | 2543 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2544 | /* Make capability read-only by default */ |
2545 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
2546 | /* Check capability by default */ |
2547 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
2548 | return offset; |
2549 | } | |
2550 | ||
2551 | /* Unlink capability from the pci config space. */ | |
2552 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
2553 | { | |
2554 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
2555 | if (!offset) | |
2556 | return; | |
2557 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 2558 | /* Make capability writable again */ |
6f4cbd39 | 2559 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 2560 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
2561 | /* Clear cmask as device-specific registers can't be checked */ |
2562 | memset(pdev->cmask + offset, 0, size); | |
e26631b7 | 2563 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2564 | |
2565 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
2566 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
2567 | } | |
2568 | ||
6f4cbd39 MT |
2569 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2570 | { | |
2571 | return pci_find_capability_list(pdev, cap_id, NULL); | |
2572 | } | |
10c4c98a GH |
2573 | |
2574 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
2575 | { | |
2576 | PCIDevice *d = (PCIDevice *)dev; | |
2577 | const pci_class_desc *desc; | |
2578 | char ctxt[64]; | |
2579 | PCIIORegion *r; | |
2580 | int i, class; | |
2581 | ||
b0ff8eb2 | 2582 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
2583 | desc = pci_class_descriptions; |
2584 | while (desc->desc && class != desc->class) | |
2585 | desc++; | |
2586 | if (desc->desc) { | |
2587 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
2588 | } else { | |
2589 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
2590 | } | |
2591 | ||
2592 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
2593 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
fd56e061 | 2594 | indent, "", ctxt, pci_dev_bus_num(d), |
e822a52a | 2595 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
2596 | pci_get_word(d->config + PCI_VENDOR_ID), |
2597 | pci_get_word(d->config + PCI_DEVICE_ID), | |
2598 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
2599 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
2600 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2601 | r = &d->io_regions[i]; | |
2602 | if (!r->size) | |
2603 | continue; | |
89e8b13c IY |
2604 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
2605 | " [0x%"FMT_PCIBUS"]\n", | |
2606 | indent, "", | |
0392a017 | 2607 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
2608 | r->addr, r->addr + r->size - 1); |
2609 | } | |
2610 | } | |
03587182 | 2611 | |
5e0259e7 GN |
2612 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2613 | { | |
2614 | PCIDevice *d = (PCIDevice *)dev; | |
2615 | const char *name = NULL; | |
2616 | const pci_class_desc *desc = pci_class_descriptions; | |
2617 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2618 | ||
2619 | while (desc->desc && | |
2620 | (class & ~desc->fw_ign_bits) != | |
2621 | (desc->class & ~desc->fw_ign_bits)) { | |
2622 | desc++; | |
2623 | } | |
2624 | ||
2625 | if (desc->desc) { | |
2626 | name = desc->fw_name; | |
2627 | } | |
2628 | ||
2629 | if (name) { | |
2630 | pstrcpy(buf, len, name); | |
2631 | } else { | |
2632 | snprintf(buf, len, "pci%04x,%04x", | |
2633 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2634 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2635 | } | |
2636 | ||
2637 | return buf; | |
2638 | } | |
2639 | ||
2640 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2641 | { | |
2642 | PCIDevice *d = (PCIDevice *)dev; | |
2643 | char path[50], name[33]; | |
2644 | int off; | |
2645 | ||
2646 | off = snprintf(path, sizeof(path), "%s@%x", | |
2647 | pci_dev_fw_name(dev, name, sizeof name), | |
2648 | PCI_SLOT(d->devfn)); | |
2649 | if (PCI_FUNC(d->devfn)) | |
2650 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
a5cf8262 | 2651 | return g_strdup(path); |
5e0259e7 GN |
2652 | } |
2653 | ||
4f43c1ff AW |
2654 | static char *pcibus_get_dev_path(DeviceState *dev) |
2655 | { | |
a6a7005d MT |
2656 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2657 | PCIDevice *t; | |
2658 | int slot_depth; | |
2659 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2660 | * 00 is added here to make this format compatible with | |
2661 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2662 | * Slot.Function list specifies the slot and function numbers for all | |
2663 | * devices on the path from root to the specific device. */ | |
568f0690 DG |
2664 | const char *root_bus_path; |
2665 | int root_bus_len; | |
2991181a | 2666 | char slot[] = ":SS.F"; |
2991181a | 2667 | int slot_len = sizeof slot - 1 /* For '\0' */; |
a6a7005d MT |
2668 | int path_len; |
2669 | char *path, *p; | |
2991181a | 2670 | int s; |
a6a7005d | 2671 | |
568f0690 DG |
2672 | root_bus_path = pci_root_bus_path(d); |
2673 | root_bus_len = strlen(root_bus_path); | |
2674 | ||
a6a7005d MT |
2675 | /* Calculate # of slots on path between device and root. */; |
2676 | slot_depth = 0; | |
fd56e061 | 2677 | for (t = d; t; t = pci_get_bus(t)->parent_dev) { |
a6a7005d MT |
2678 | ++slot_depth; |
2679 | } | |
2680 | ||
568f0690 | 2681 | path_len = root_bus_len + slot_len * slot_depth; |
a6a7005d MT |
2682 | |
2683 | /* Allocate memory, fill in the terminating null byte. */ | |
7267c094 | 2684 | path = g_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2685 | path[path_len] = '\0'; |
2686 | ||
568f0690 | 2687 | memcpy(path, root_bus_path, root_bus_len); |
a6a7005d MT |
2688 | |
2689 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2690 | * them in the reverse order, last to first. */ | |
2691 | p = path + path_len; | |
fd56e061 | 2692 | for (t = d; t; t = pci_get_bus(t)->parent_dev) { |
a6a7005d | 2693 | p -= slot_len; |
2991181a | 2694 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2695 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2696 | assert(s == slot_len); |
2697 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2698 | } |
2699 | ||
2700 | return path; | |
4f43c1ff AW |
2701 | } |
2702 | ||
f3006dd1 IY |
2703 | static int pci_qdev_find_recursive(PCIBus *bus, |
2704 | const char *id, PCIDevice **pdev) | |
2705 | { | |
2706 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2707 | if (!qdev) { | |
2708 | return -ENODEV; | |
2709 | } | |
2710 | ||
2711 | /* roughly check if given qdev is pci device */ | |
4be9f0d1 | 2712 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
40021f08 | 2713 | *pdev = PCI_DEVICE(qdev); |
f3006dd1 IY |
2714 | return 0; |
2715 | } | |
2716 | return -EINVAL; | |
2717 | } | |
2718 | ||
2719 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2720 | { | |
7588e2b0 | 2721 | PCIHostState *host_bridge; |
f3006dd1 IY |
2722 | int rc = -ENODEV; |
2723 | ||
7588e2b0 DG |
2724 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
2725 | int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); | |
f3006dd1 IY |
2726 | if (!tmp) { |
2727 | rc = 0; | |
2728 | break; | |
2729 | } | |
2730 | if (tmp != -ENODEV) { | |
2731 | rc = tmp; | |
2732 | } | |
2733 | } | |
2734 | ||
2735 | return rc; | |
2736 | } | |
f5e6fed8 AK |
2737 | |
2738 | MemoryRegion *pci_address_space(PCIDevice *dev) | |
2739 | { | |
fd56e061 | 2740 | return pci_get_bus(dev)->address_space_mem; |
f5e6fed8 | 2741 | } |
e11d6439 RH |
2742 | |
2743 | MemoryRegion *pci_address_space_io(PCIDevice *dev) | |
2744 | { | |
fd56e061 | 2745 | return pci_get_bus(dev)->address_space_io; |
e11d6439 | 2746 | } |
40021f08 | 2747 | |
39bffca2 AL |
2748 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2749 | { | |
2750 | DeviceClass *k = DEVICE_CLASS(klass); | |
7ee6c1e1 | 2751 | |
133e9b22 MA |
2752 | k->realize = pci_qdev_realize; |
2753 | k->unrealize = pci_qdev_unrealize; | |
0d936928 | 2754 | k->bus_type = TYPE_PCI_BUS; |
4f67d30b | 2755 | device_class_set_props(k, pci_props); |
39bffca2 AL |
2756 | } |
2757 | ||
2fefa16c EH |
2758 | static void pci_device_class_base_init(ObjectClass *klass, void *data) |
2759 | { | |
2760 | if (!object_class_is_abstract(klass)) { | |
2761 | ObjectClass *conventional = | |
2762 | object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); | |
2763 | ObjectClass *pcie = | |
2764 | object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); | |
d86d3019 BW |
2765 | ObjectClass *cxl = |
2766 | object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); | |
2767 | assert(conventional || pcie || cxl); | |
2fefa16c EH |
2768 | } |
2769 | } | |
2770 | ||
9eda7d37 AK |
2771 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) |
2772 | { | |
fd56e061 | 2773 | PCIBus *bus = pci_get_bus(dev); |
5af2ae23 | 2774 | PCIBus *iommu_bus = bus; |
77ef8f8d | 2775 | uint8_t devfn = dev->devfn; |
9eda7d37 | 2776 | |
77ef8f8d AW |
2777 | while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { |
2778 | PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); | |
2779 | ||
2780 | /* | |
2781 | * The requester ID of the provided device may be aliased, as seen from | |
2782 | * the IOMMU, due to topology limitations. The IOMMU relies on a | |
2783 | * requester ID to provide a unique AddressSpace for devices, but | |
2784 | * conventional PCI buses pre-date such concepts. Instead, the PCIe- | |
2785 | * to-PCI bridge creates and accepts transactions on behalf of down- | |
2786 | * stream devices. When doing so, all downstream devices are masked | |
2787 | * (aliased) behind a single requester ID. The requester ID used | |
2788 | * depends on the format of the bridge devices. Proper PCIe-to-PCI | |
2789 | * bridges, with a PCIe capability indicating such, follow the | |
2790 | * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, | |
2791 | * where the bridge uses the seconary bus as the bridge portion of the | |
2792 | * requester ID and devfn of 00.0. For other bridges, typically those | |
2793 | * found on the root complex such as the dmi-to-pci-bridge, we follow | |
2794 | * the convention of typical bare-metal hardware, which uses the | |
2795 | * requester ID of the bridge itself. There are device specific | |
2796 | * exceptions to these rules, but these are the defaults that the | |
2797 | * Linux kernel uses when determining DMA aliases itself and believed | |
2798 | * to be true for the bare metal equivalents of the devices emulated | |
2799 | * in QEMU. | |
2800 | */ | |
2801 | if (!pci_bus_is_express(iommu_bus)) { | |
2802 | PCIDevice *parent = iommu_bus->parent_dev; | |
2803 | ||
2804 | if (pci_is_express(parent) && | |
2805 | pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
2806 | devfn = PCI_DEVFN(0, 0); | |
2807 | bus = iommu_bus; | |
2808 | } else { | |
2809 | devfn = parent->devfn; | |
2810 | bus = parent_bus; | |
2811 | } | |
2812 | } | |
2813 | ||
2814 | iommu_bus = parent_bus; | |
9eda7d37 | 2815 | } |
2d64b7bb | 2816 | if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { |
77ef8f8d | 2817 | return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); |
9eda7d37 | 2818 | } |
9eda7d37 AK |
2819 | return &address_space_memory; |
2820 | } | |
2821 | ||
e00387d5 | 2822 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
5fa45de5 | 2823 | { |
e00387d5 AK |
2824 | bus->iommu_fn = fn; |
2825 | bus->iommu_opaque = opaque; | |
5fa45de5 DG |
2826 | } |
2827 | ||
43864069 MT |
2828 | static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) |
2829 | { | |
2830 | Range *range = opaque; | |
2831 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
2832 | uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); | |
77d6f4ea | 2833 | int i; |
43864069 MT |
2834 | |
2835 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
2836 | return; | |
2837 | } | |
2838 | ||
2839 | if (pc->is_bridge) { | |
2840 | pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2841 | pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2842 | ||
2843 | base = MAX(base, 0x1ULL << 32); | |
2844 | ||
2845 | if (limit >= base) { | |
2846 | Range pref_range; | |
a0efbf16 | 2847 | range_set_bounds(&pref_range, base, limit); |
43864069 MT |
2848 | range_extend(range, &pref_range); |
2849 | } | |
2850 | } | |
77d6f4ea MT |
2851 | for (i = 0; i < PCI_NUM_REGIONS; ++i) { |
2852 | PCIIORegion *r = &dev->io_regions[i]; | |
a0efbf16 | 2853 | pcibus_t lob, upb; |
43864069 MT |
2854 | Range region_range; |
2855 | ||
77d6f4ea MT |
2856 | if (!r->size || |
2857 | (r->type & PCI_BASE_ADDRESS_SPACE_IO) || | |
2858 | !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { | |
2859 | continue; | |
2860 | } | |
77d6f4ea | 2861 | |
a0efbf16 MA |
2862 | lob = pci_bar_address(dev, i, r->type, r->size); |
2863 | upb = lob + r->size - 1; | |
2864 | if (lob == PCI_BAR_UNMAPPED) { | |
43864069 MT |
2865 | continue; |
2866 | } | |
43864069 | 2867 | |
a0efbf16 | 2868 | lob = MAX(lob, 0x1ULL << 32); |
43864069 | 2869 | |
a0efbf16 MA |
2870 | if (upb >= lob) { |
2871 | range_set_bounds(®ion_range, lob, upb); | |
43864069 MT |
2872 | range_extend(range, ®ion_range); |
2873 | } | |
2874 | } | |
2875 | } | |
2876 | ||
2877 | void pci_bus_get_w64_range(PCIBus *bus, Range *range) | |
2878 | { | |
a0efbf16 | 2879 | range_make_empty(range); |
43864069 MT |
2880 | pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); |
2881 | } | |
2882 | ||
3f1e1478 C |
2883 | static bool pcie_has_upstream_port(PCIDevice *dev) |
2884 | { | |
fd56e061 | 2885 | PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); |
3f1e1478 C |
2886 | |
2887 | /* Device associated with an upstream port. | |
2888 | * As there are several types of these, it's easier to check the | |
2889 | * parent device: upstream ports are always connected to | |
2890 | * root or downstream ports. | |
2891 | */ | |
2892 | return parent_dev && | |
2893 | pci_is_express(parent_dev) && | |
2894 | parent_dev->exp.exp_cap && | |
2895 | (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || | |
2896 | pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); | |
2897 | } | |
2898 | ||
2899 | PCIDevice *pci_get_function_0(PCIDevice *pci_dev) | |
2900 | { | |
fd56e061 DG |
2901 | PCIBus *bus = pci_get_bus(pci_dev); |
2902 | ||
3f1e1478 C |
2903 | if(pcie_has_upstream_port(pci_dev)) { |
2904 | /* With an upstream PCIe port, we only support 1 device at slot 0 */ | |
fd56e061 | 2905 | return bus->devices[0]; |
3f1e1478 C |
2906 | } else { |
2907 | /* Other bus types might support multiple devices at slots 0-31 */ | |
fd56e061 | 2908 | return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; |
3f1e1478 C |
2909 | } |
2910 | } | |
2911 | ||
e1d4fb2d PX |
2912 | MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) |
2913 | { | |
2914 | MSIMessage msg; | |
2915 | if (msix_enabled(dev)) { | |
2916 | msg = msix_get_message(dev, vector); | |
2917 | } else if (msi_enabled(dev)) { | |
2918 | msg = msi_get_message(dev, vector); | |
2919 | } else { | |
2920 | /* Should never happen */ | |
2921 | error_report("%s: unknown interrupt type", __func__); | |
2922 | abort(); | |
2923 | } | |
2924 | return msg; | |
2925 | } | |
2926 | ||
23786d13 GH |
2927 | void pci_set_power(PCIDevice *d, bool state) |
2928 | { | |
2929 | if (d->has_power == state) { | |
2930 | return; | |
2931 | } | |
2932 | ||
2933 | d->has_power = state; | |
2934 | pci_update_mappings(d); | |
2935 | memory_region_set_enabled(&d->bus_master_enable_region, | |
2936 | (pci_get_word(d->config + PCI_COMMAND) | |
2937 | & PCI_COMMAND_MASTER) && d->has_power); | |
2938 | if (!d->has_power) { | |
2939 | pci_device_reset(d); | |
2940 | } | |
2941 | } | |
2942 | ||
8c43a6f0 | 2943 | static const TypeInfo pci_device_type_info = { |
40021f08 AL |
2944 | .name = TYPE_PCI_DEVICE, |
2945 | .parent = TYPE_DEVICE, | |
2946 | .instance_size = sizeof(PCIDevice), | |
2947 | .abstract = true, | |
2948 | .class_size = sizeof(PCIDeviceClass), | |
39bffca2 | 2949 | .class_init = pci_device_class_init, |
2fefa16c | 2950 | .class_base_init = pci_device_class_base_init, |
40021f08 AL |
2951 | }; |
2952 | ||
83f7d43a | 2953 | static void pci_register_types(void) |
40021f08 | 2954 | { |
0d936928 | 2955 | type_register_static(&pci_bus_info); |
3a861c46 | 2956 | type_register_static(&pcie_bus_info); |
4f8db871 | 2957 | type_register_static(&cxl_bus_info); |
619f02ae | 2958 | type_register_static(&conventional_pci_interface_info); |
cf04aba2 | 2959 | type_register_static(&cxl_interface_info); |
619f02ae | 2960 | type_register_static(&pcie_interface_info); |
40021f08 AL |
2961 | type_register_static(&pci_device_type_info); |
2962 | } | |
2963 | ||
83f7d43a | 2964 | type_init(pci_register_types) |