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69b91039
FB
1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
c759b24f
MT
24#include "hw/hw.h"
25#include "hw/pci/pci.h"
26#include "hw/pci/pci_bridge.h"
06aac7bd 27#include "hw/pci/pci_bus.h"
568f0690 28#include "hw/pci/pci_host.h"
83c9089e 29#include "monitor/monitor.h"
1422e32d 30#include "net/net.h"
9c17d615 31#include "sysemu/sysemu.h"
c759b24f 32#include "hw/loader.h"
1de7afc9 33#include "qemu/range.h"
79627472 34#include "qmp-commands.h"
c759b24f
MT
35#include "hw/pci/msi.h"
36#include "hw/pci/msix.h"
022c62cb 37#include "exec/address-spaces.h"
5e954943 38#include "hw/hotplug.h"
69b91039
FB
39
40//#define DEBUG_PCI
d8d2e079 41#ifdef DEBUG_PCI
2e49d64a 42# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY
43#else
44# define PCI_DPRINTF(format, ...) do { } while (0)
45#endif
69b91039 46
10c4c98a 47static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 48static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 49static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 50static void pcibus_reset(BusState *qbus);
10c4c98a 51
3cb75a7c
PB
52static Property pci_props[] = {
53 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
54 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
55 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
56 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
57 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
58 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
59 QEMU_PCI_CAP_SERR_BITNR, true),
60 DEFINE_PROP_END_OF_LIST()
61};
62
d2f69df7
BD
63static const VMStateDescription vmstate_pcibus = {
64 .name = "PCIBUS",
65 .version_id = 1,
66 .minimum_version_id = 1,
d49805ae 67 .fields = (VMStateField[]) {
d2f69df7
BD
68 VMSTATE_INT32_EQUAL(nirq, PCIBus),
69 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
70 nirq, 0, vmstate_info_int32,
71 int32_t),
72 VMSTATE_END_OF_LIST()
73 }
74};
75
76static void pci_bus_realize(BusState *qbus, Error **errp)
77{
78 PCIBus *bus = PCI_BUS(qbus);
79
80 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
81}
82
83static void pci_bus_unrealize(BusState *qbus, Error **errp)
84{
85 PCIBus *bus = PCI_BUS(qbus);
86
87 vmstate_unregister(NULL, &vmstate_pcibus, bus);
88}
89
0d936928
AL
90static void pci_bus_class_init(ObjectClass *klass, void *data)
91{
92 BusClass *k = BUS_CLASS(klass);
93
94 k->print_dev = pcibus_dev_print;
95 k->get_dev_path = pcibus_get_dev_path;
96 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD
97 k->realize = pci_bus_realize;
98 k->unrealize = pci_bus_unrealize;
0d936928
AL
99 k->reset = pcibus_reset;
100}
101
102static const TypeInfo pci_bus_info = {
103 .name = TYPE_PCI_BUS,
104 .parent = TYPE_BUS,
105 .instance_size = sizeof(PCIBus),
106 .class_init = pci_bus_class_init,
30468f78 107};
69b91039 108
3a861c46
AW
109static const TypeInfo pcie_bus_info = {
110 .name = TYPE_PCIE_BUS,
111 .parent = TYPE_PCI_BUS,
112};
113
d662210a 114static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 115static void pci_update_mappings(PCIDevice *d);
d98f08f5 116static void pci_irq_handler(void *opaque, int irq_num, int level);
ab85ceb1 117static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
230741dc 118static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 119
d350d97d
AL
120static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
121static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 122
7588e2b0 123static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 124
b3b11697 125static int pci_bar(PCIDevice *d, int reg)
5330de09 126{
b3b11697
IY
127 uint8_t type;
128
129 if (reg != PCI_ROM_SLOT)
130 return PCI_BASE_ADDRESS_0 + reg * 4;
131
132 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
133 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT
134}
135
d036bb21
MT
136static inline int pci_irq_state(PCIDevice *d, int irq_num)
137{
138 return (d->irq_state >> irq_num) & 0x1;
139}
140
141static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
142{
143 d->irq_state &= ~(0x1 << irq_num);
144 d->irq_state |= level << irq_num;
145}
146
147static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
148{
149 PCIBus *bus;
150 for (;;) {
151 bus = pci_dev->bus;
152 irq_num = bus->map_irq(pci_dev, irq_num);
153 if (bus->set_irq)
154 break;
155 pci_dev = bus->parent_dev;
156 }
157 bus->irq_count[irq_num] += change;
158 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
159}
160
9ddf8437
IY
161int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
162{
163 assert(irq_num >= 0);
164 assert(irq_num < bus->nirq);
165 return !!bus->irq_count[irq_num];
166}
167
f9bf77dd
MT
168/* Update interrupt status bit in config space on interrupt
169 * state change. */
170static void pci_update_irq_status(PCIDevice *dev)
171{
172 if (dev->irq_state) {
173 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
174 } else {
175 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
176 }
177}
178
4c92325b
IY
179void pci_device_deassert_intx(PCIDevice *dev)
180{
181 int i;
182 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 183 pci_irq_handler(dev, i, 0);
4c92325b
IY
184 }
185}
186
dcc20931 187static void pci_do_device_reset(PCIDevice *dev)
5330de09 188{
c0b1905b 189 int r;
6fc4925b 190
4c92325b 191 pci_device_deassert_intx(dev);
58b59014
CR
192 assert(dev->irq_state == 0);
193
ebabb67a 194 /* Clear all writable bits */
99443c21 195 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT
196 pci_get_word(dev->wmask + PCI_COMMAND) |
197 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY
198 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
199 pci_get_word(dev->wmask + PCI_STATUS) |
200 pci_get_word(dev->w1cmask + PCI_STATUS));
c0b1905b
MT
201 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
202 dev->config[PCI_INTERRUPT_LINE] = 0x0;
203 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY
204 PCIIORegion *region = &dev->io_regions[r];
205 if (!region->size) {
c0b1905b
MT
206 continue;
207 }
71ebd6dc
IY
208
209 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
210 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
211 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
212 } else {
213 pci_set_long(dev->config + pci_bar(dev, r), region->type);
214 }
c0b1905b
MT
215 }
216 pci_update_mappings(dev);
cbd2d434
JK
217
218 msi_reset(dev);
219 msix_reset(dev);
5330de09
MT
220}
221
dcc20931
PB
222/*
223 * This function is called on #RST and FLR.
224 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
225 */
226void pci_device_reset(PCIDevice *dev)
227{
228 qdev_reset_all(&dev->qdev);
229 pci_do_device_reset(dev);
230}
231
9bb33586
IY
232/*
233 * Trigger pci bus reset under a given bus.
dcc20931
PB
234 * Called via qbus_reset_all on RST# assert, after the devices
235 * have been reset qdev_reset_all-ed already.
9bb33586 236 */
dcc20931 237static void pcibus_reset(BusState *qbus)
6eaa6847 238{
81e3e75b 239 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN
240 int i;
241
5330de09
MT
242 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
243 if (bus->devices[i]) {
dcc20931 244 pci_do_device_reset(bus->devices[i]);
5330de09 245 }
6eaa6847 246 }
9bb33586 247
9bdbbfc3
PB
248 for (i = 0; i < bus->nirq; i++) {
249 assert(bus->irq_count[i] == 0);
250 }
9bb33586
IY
251}
252
7588e2b0 253static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
e822a52a 254{
7588e2b0
DG
255 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);
256
257 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY
258}
259
1ef7a2a2 260PCIBus *pci_find_primary_bus(void)
e822a52a 261{
9bc47305 262 PCIBus *primary_bus = NULL;
7588e2b0 263 PCIHostState *host;
e822a52a 264
7588e2b0 265 QLIST_FOREACH(host, &pci_host_bridges, next) {
9bc47305
DG
266 if (primary_bus) {
267 /* We have multiple root buses, refuse to select a primary */
268 return NULL;
e822a52a 269 }
9bc47305 270 primary_bus = host->bus;
e822a52a
IY
271 }
272
9bc47305 273 return primary_bus;
e822a52a
IY
274}
275
c473d18d 276PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 277{
c473d18d 278 PCIBus *bus = d->bus;
e075e788 279
e075e788
IY
280 while ((d = bus->parent_dev) != NULL) {
281 bus = d->bus;
282 }
283
c473d18d
DG
284 return bus;
285}
286
568f0690 287const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 288{
568f0690
DG
289 PCIBus *rootbus = pci_device_root_bus(dev);
290 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
291 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 292
568f0690
DG
293 assert(!rootbus->parent_dev);
294 assert(host_bridge->bus == rootbus);
295
296 if (hc->root_bus_path) {
297 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY
298 }
299
568f0690 300 return rootbus->qbus.name;
e075e788
IY
301}
302
4fec6404 303static void pci_bus_init(PCIBus *bus, DeviceState *parent,
1e39101c 304 const char *name,
aee97b84
AK
305 MemoryRegion *address_space_mem,
306 MemoryRegion *address_space_io,
1e39101c 307 uint8_t devfn_min)
30468f78 308{
6fa84913 309 assert(PCI_FUNC(devfn_min) == 0);
502a5395 310 bus->devfn_min = devfn_min;
5968eca3
AK
311 bus->address_space_mem = address_space_mem;
312 bus->address_space_io = address_space_io;
e822a52a
IY
313
314 /* host bridge */
315 QLIST_INIT(&bus->child);
2b8cc89a 316
7588e2b0 317 pci_host_bus_register(bus, parent);
21eea4b3
GH
318}
319
8c0bf9e2
AW
320bool pci_bus_is_express(PCIBus *bus)
321{
322 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
323}
324
0889464a
AW
325bool pci_bus_is_root(PCIBus *bus)
326{
327 return !bus->parent_dev;
328}
329
dd301ca6 330void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
4fec6404
PB
331 const char *name,
332 MemoryRegion *address_space_mem,
333 MemoryRegion *address_space_io,
60a0e443 334 uint8_t devfn_min, const char *typename)
4fec6404 335{
fb17dfe0 336 qbus_create_inplace(bus, bus_size, typename, parent, name);
4fec6404
PB
337 pci_bus_init(bus, parent, name, address_space_mem,
338 address_space_io, devfn_min);
339}
340
1e39101c 341PCIBus *pci_bus_new(DeviceState *parent, const char *name,
aee97b84
AK
342 MemoryRegion *address_space_mem,
343 MemoryRegion *address_space_io,
60a0e443 344 uint8_t devfn_min, const char *typename)
21eea4b3
GH
345{
346 PCIBus *bus;
347
60a0e443 348 bus = PCI_BUS(qbus_create(typename, parent, name));
4fec6404
PB
349 pci_bus_init(bus, parent, name, address_space_mem,
350 address_space_io, devfn_min);
21eea4b3
GH
351 return bus;
352}
353
354void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
355 void *irq_opaque, int nirq)
356{
357 bus->set_irq = set_irq;
358 bus->map_irq = map_irq;
359 bus->irq_opaque = irq_opaque;
360 bus->nirq = nirq;
7267c094 361 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH
362}
363
364PCIBus *pci_register_bus(DeviceState *parent, const char *name,
365 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
1e39101c 366 void *irq_opaque,
aee97b84
AK
367 MemoryRegion *address_space_mem,
368 MemoryRegion *address_space_io,
60a0e443 369 uint8_t devfn_min, int nirq, const char *typename)
21eea4b3
GH
370{
371 PCIBus *bus;
372
aee97b84 373 bus = pci_bus_new(parent, name, address_space_mem,
60a0e443 374 address_space_io, devfn_min, typename);
21eea4b3 375 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB
376 return bus;
377}
69b91039 378
502a5395
PB
379int pci_bus_num(PCIBus *s)
380{
0889464a 381 if (pci_bus_is_root(s))
e94ff650
IY
382 return 0; /* pci host bridge */
383 return s->parent_dev->config[PCI_SECONDARY_BUS];
502a5395
PB
384}
385
73534f2f 386static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
30ca2aab 387{
73534f2f 388 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 389 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 390 uint8_t *config;
52fc1d83
AZ
391 int i;
392
a9f49946 393 assert(size == pci_config_size(s));
7267c094 394 config = g_malloc(size);
a9f49946
IY
395
396 qemu_get_buffer(f, config, size);
397 for (i = 0; i < size; ++i) {
f9aebe2e
MT
398 if ((config[i] ^ s->config[i]) &
399 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7267c094 400 g_free(config);
bd4b65ee 401 return -EINVAL;
a9f49946
IY
402 }
403 }
404 memcpy(s->config, config, size);
bd4b65ee 405
1941d19c 406 pci_update_mappings(s);
e78e9ae4 407 if (pc->is_bridge) {
f055e96b 408 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK
409 pci_bridge_update_mappings(b);
410 }
52fc1d83 411
4ea375bf
GH
412 memory_region_set_enabled(&s->bus_master_enable_region,
413 pci_get_word(s->config + PCI_COMMAND)
414 & PCI_COMMAND_MASTER);
415
7267c094 416 g_free(config);
30ca2aab
FB
417 return 0;
418}
419
73534f2f 420/* just put buffer */
84e2e3eb 421static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
73534f2f 422{
dbe73d7f 423 const uint8_t **v = pv;
a9f49946 424 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 425 qemu_put_buffer(f, *v, size);
73534f2f
JQ
426}
427
428static VMStateInfo vmstate_info_pci_config = {
429 .name = "pci config",
430 .get = get_pci_config_device,
431 .put = put_pci_config_device,
432};
433
d036bb21
MT
434static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
435{
c3f8f611 436 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT
437 uint32_t irq_state[PCI_NUM_PINS];
438 int i;
439 for (i = 0; i < PCI_NUM_PINS; ++i) {
440 irq_state[i] = qemu_get_be32(f);
441 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
442 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
443 irq_state[i]);
444 return -EINVAL;
445 }
446 }
447
448 for (i = 0; i < PCI_NUM_PINS; ++i) {
449 pci_set_irq_state(s, i, irq_state[i]);
450 }
451
452 return 0;
453}
454
455static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
456{
457 int i;
c3f8f611 458 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT
459
460 for (i = 0; i < PCI_NUM_PINS; ++i) {
461 qemu_put_be32(f, pci_irq_state(s, i));
462 }
463}
464
465static VMStateInfo vmstate_info_pci_irq_state = {
466 .name = "pci irq state",
467 .get = get_pci_irq_state,
468 .put = put_pci_irq_state,
469};
470
73534f2f
JQ
471const VMStateDescription vmstate_pci_device = {
472 .name = "PCIDevice",
473 .version_id = 2,
474 .minimum_version_id = 1,
d49805ae 475 .fields = (VMStateField[]) {
3476436a 476 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
a9f49946
IY
477 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
478 vmstate_info_pci_config,
479 PCI_CONFIG_SPACE_SIZE),
d036bb21
MT
480 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
481 vmstate_info_pci_irq_state,
482 PCI_NUM_PINS * sizeof(int32_t)),
a9f49946
IY
483 VMSTATE_END_OF_LIST()
484 }
485};
486
487const VMStateDescription vmstate_pcie_device = {
1de53459 488 .name = "PCIEDevice",
a9f49946
IY
489 .version_id = 2,
490 .minimum_version_id = 1,
d49805ae 491 .fields = (VMStateField[]) {
3476436a 492 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
a9f49946
IY
493 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
494 vmstate_info_pci_config,
495 PCIE_CONFIG_SPACE_SIZE),
d036bb21
MT
496 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
497 vmstate_info_pci_irq_state,
498 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ
499 VMSTATE_END_OF_LIST()
500 }
501};
502
a9f49946
IY
503static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
504{
505 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
506}
507
73534f2f
JQ
508void pci_device_save(PCIDevice *s, QEMUFile *f)
509{
f9bf77dd
MT
510 /* Clear interrupt status bit: it is implicit
511 * in irq_state which we are saving.
512 * This makes us compatible with old devices
513 * which never set or clear this bit. */
514 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
a9f49946 515 vmstate_save_state(f, pci_get_vmstate(s), s);
f9bf77dd
MT
516 /* Restore the interrupt status bit. */
517 pci_update_irq_status(s);
73534f2f
JQ
518}
519
520int pci_device_load(PCIDevice *s, QEMUFile *f)
521{
f9bf77dd
MT
522 int ret;
523 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
524 /* Restore the interrupt status bit. */
525 pci_update_irq_status(s);
526 return ret;
73534f2f
JQ
527}
528
5e434f4e 529static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 530{
5e434f4e
IY
531 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
532 pci_default_sub_vendor_id);
533 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
534 pci_default_sub_device_id);
d350d97d
AL
535}
536
880345c4 537/*
43c945f1
IY
538 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
539 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 540 */
6ac363b5 541int pci_parse_devaddr(const char *addr, int *domp, int *busp,
43c945f1 542 unsigned int *slotp, unsigned int *funcp)
880345c4
AL
543{
544 const char *p;
545 char *e;
546 unsigned long val;
547 unsigned long dom = 0, bus = 0;
43c945f1
IY
548 unsigned int slot = 0;
549 unsigned int func = 0;
880345c4
AL
550
551 p = addr;
552 val = strtoul(p, &e, 16);
553 if (e == p)
554 return -1;
555 if (*e == ':') {
556 bus = val;
557 p = e + 1;
558 val = strtoul(p, &e, 16);
559 if (e == p)
560 return -1;
561 if (*e == ':') {
562 dom = bus;
563 bus = val;
564 p = e + 1;
565 val = strtoul(p, &e, 16);
566 if (e == p)
567 return -1;
568 }
569 }
570
880345c4
AL
571 slot = val;
572
43c945f1
IY
573 if (funcp != NULL) {
574 if (*e != '.')
575 return -1;
576
577 p = e + 1;
578 val = strtoul(p, &e, 16);
579 if (e == p)
580 return -1;
581
582 func = val;
583 }
584
585 /* if funcp == NULL func is 0 */
586 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
587 return -1;
588
880345c4
AL
589 if (*e)
590 return -1;
591
880345c4
AL
592 *domp = dom;
593 *busp = bus;
594 *slotp = slot;
43c945f1
IY
595 if (funcp != NULL)
596 *funcp = func;
880345c4
AL
597 return 0;
598}
599
85c6e4fa 600PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
5607c388
MA
601{
602 int dom, bus;
603 unsigned slot;
604
1ef7a2a2
DG
605 if (!root) {
606 fprintf(stderr, "No primary PCI bus\n");
607 return NULL;
608 }
609
b645000e
S
610 assert(!root->parent_dev);
611
5607c388
MA
612 if (!devaddr) {
613 *devfnp = -1;
1ef7a2a2 614 return pci_find_bus_nr(root, 0);
5607c388
MA
615 }
616
43c945f1 617 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
5607c388
MA
618 return NULL;
619 }
620
1ef7a2a2
DG
621 if (dom != 0) {
622 fprintf(stderr, "No support for non-zero PCI domains\n");
623 return NULL;
624 }
625
6ff534b6 626 *devfnp = PCI_DEVFN(slot, 0);
1ef7a2a2 627 return pci_find_bus_nr(root, bus);
5607c388
MA
628}
629
bd4b65ee
MT
630static void pci_init_cmask(PCIDevice *dev)
631{
632 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
633 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
634 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
635 dev->cmask[PCI_REVISION_ID] = 0xff;
636 dev->cmask[PCI_CLASS_PROG] = 0xff;
637 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
638 dev->cmask[PCI_HEADER_TYPE] = 0xff;
639 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
640}
641
b7ee1603
MT
642static void pci_init_wmask(PCIDevice *dev)
643{
a9f49946
IY
644 int config_size = pci_config_size(dev);
645
b7ee1603
MT
646 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
647 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 648 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT
649 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
650 PCI_COMMAND_INTX_DISABLE);
b1aeb926
IY
651 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
652 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
653 }
3e21ffc9
IY
654
655 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
656 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT
657}
658
89d437df
IY
659static void pci_init_w1cmask(PCIDevice *dev)
660{
661 /*
f6bdfcc9 662 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY
663 * long as their value is hardwired to 0.
664 */
665 pci_set_word(dev->w1cmask + PCI_STATUS,
666 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
667 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
668 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
669}
670
d5f27e88 671static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY
672{
673 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
674 PCI_SEC_LETENCY_TIMER */
675 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
676
677 /* base and limit */
678 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
679 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
680 pci_set_word(d->wmask + PCI_MEMORY_BASE,
681 PCI_MEMORY_RANGE_MASK & 0xffff);
682 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
683 PCI_MEMORY_RANGE_MASK & 0xffff);
684 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
685 PCI_PREF_RANGE_MASK & 0xffff);
686 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
687 PCI_PREF_RANGE_MASK & 0xffff);
688
689 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
690 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
691
d5f27e88 692 /* Supported memory and i/o types */
68917102
MT
693 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
694 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT
695 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
696 PCI_PREF_RANGE_TYPE_64);
697 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
698 PCI_PREF_RANGE_TYPE_64);
699
45eb768c
MT
700 /*
701 * TODO: Bridges default to 10-bit VGA decoding but we currently only
702 * implement 16-bit decoding (no alias support).
703 */
f6bdfcc9
MT
704 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
705 PCI_BRIDGE_CTL_PARITY |
706 PCI_BRIDGE_CTL_SERR |
707 PCI_BRIDGE_CTL_ISA |
708 PCI_BRIDGE_CTL_VGA |
709 PCI_BRIDGE_CTL_VGA_16BIT |
710 PCI_BRIDGE_CTL_MASTER_ABORT |
711 PCI_BRIDGE_CTL_BUS_RESET |
712 PCI_BRIDGE_CTL_FAST_BACK |
713 PCI_BRIDGE_CTL_DISCARD |
714 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT
715 PCI_BRIDGE_CTL_DISCARD_SERR);
716 /* Below does not do anything as we never set this bit, put here for
717 * completeness. */
718 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
719 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 720 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 721 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT
722 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
723 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT
724 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
725 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY
726}
727
6eab3de1
IY
728static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
729{
730 uint8_t slot = PCI_SLOT(dev->devfn);
731 uint8_t func;
732
733 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
734 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
735 }
736
737 /*
b0cd712c 738 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY
739 * - all functions must set the bit to 1.
740 * Example: Intel X53
741 * - function 0 must set the bit, but the rest function (> 0)
742 * is allowed to leave the bit to 0.
743 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
744 *
745 * So OS (at least Linux) checks the bit of only function 0,
746 * and doesn't see the bit of function > 0.
747 *
748 * The below check allows both interpretation.
749 */
750 if (PCI_FUNC(dev->devfn)) {
751 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
752 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
753 /* function 0 should set multifunction bit */
754 error_report("PCI: single function device can't be populated "
755 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
756 return -1;
757 }
758 return 0;
759 }
760
761 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
762 return 0;
763 }
764 /* function 0 indicates single function, so function > 0 must be NULL */
765 for (func = 1; func < PCI_FUNC_MAX; ++func) {
766 if (bus->devices[PCI_DEVFN(slot, func)]) {
767 error_report("PCI: %x.0 indicates single function, "
768 "but %x.%x is already populated.",
769 slot, slot, func);
770 return -1;
771 }
772 }
773 return 0;
774}
775
a9f49946
IY
776static void pci_config_alloc(PCIDevice *pci_dev)
777{
778 int config_size = pci_config_size(pci_dev);
779
7267c094
AL
780 pci_dev->config = g_malloc0(config_size);
781 pci_dev->cmask = g_malloc0(config_size);
782 pci_dev->wmask = g_malloc0(config_size);
783 pci_dev->w1cmask = g_malloc0(config_size);
784 pci_dev->used = g_malloc0(config_size);
a9f49946
IY
785}
786
787static void pci_config_free(PCIDevice *pci_dev)
788{
7267c094
AL
789 g_free(pci_dev->config);
790 g_free(pci_dev->cmask);
791 g_free(pci_dev->wmask);
792 g_free(pci_dev->w1cmask);
793 g_free(pci_dev->used);
a9f49946
IY
794}
795
30607764
MA
796static void do_pci_unregister_device(PCIDevice *pci_dev)
797{
798 pci_dev->bus->devices[pci_dev->devfn] = NULL;
799 pci_config_free(pci_dev);
800
801 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA
802}
803
69b91039 804/* -1 for devfn means auto assign */
6b1b92d3 805static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
40021f08 806 const char *name, int devfn)
69b91039 807{
40021f08
AL
808 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
809 PCIConfigReadFunc *config_read = pc->config_read;
810 PCIConfigWriteFunc *config_write = pc->config_write;
e00387d5 811 AddressSpace *dma_as;
113f89df 812
69b91039 813 if (devfn < 0) {
b47b0706 814 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 815 devfn += PCI_FUNC_MAX) {
30468f78 816 if (!bus->devices[devfn])
69b91039
FB
817 goto found;
818 }
3709c1b7 819 error_report("PCI: no slot/function available for %s, all in use", name);
09e3acc6 820 return NULL;
69b91039 821 found: ;
07b7d053 822 } else if (bus->devices[devfn]) {
3709c1b7
DB
823 error_report("PCI: slot %d function %d not available for %s, in use by %s",
824 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
09e3acc6 825 return NULL;
69b91039 826 }
e00387d5 827
30468f78 828 pci_dev->bus = bus;
efc8188e 829 pci_dev->devfn = devfn;
9eda7d37 830 dma_as = pci_device_iommu_address_space(pci_dev);
24addbc7 831
40c5dce9
PB
832 memory_region_init_alias(&pci_dev->bus_master_enable_region,
833 OBJECT(pci_dev), "bus master",
e00387d5
AK
834 dma_as->root, 0, memory_region_size(dma_as->root));
835 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
7dca8043
AK
836 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
837 name);
e00387d5 838
69b91039 839 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
d036bb21 840 pci_dev->irq_state = 0;
a9f49946 841 pci_config_alloc(pci_dev);
fb231628 842
40021f08
AL
843 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
844 pci_config_set_device_id(pci_dev->config, pc->device_id);
845 pci_config_set_revision(pci_dev->config, pc->revision);
846 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 847
40021f08
AL
848 if (!pc->is_bridge) {
849 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 850 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 851 pc->subsystem_vendor_id);
113f89df 852 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 853 pc->subsystem_id);
113f89df
IY
854 } else {
855 pci_set_default_subsystem_id(pci_dev);
856 }
857 } else {
858 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL
859 assert(!pc->subsystem_vendor_id);
860 assert(!pc->subsystem_id);
fb231628 861 }
bd4b65ee 862 pci_init_cmask(pci_dev);
b7ee1603 863 pci_init_wmask(pci_dev);
89d437df 864 pci_init_w1cmask(pci_dev);
40021f08 865 if (pc->is_bridge) {
d5f27e88 866 pci_init_mask_bridge(pci_dev);
fb231628 867 }
6eab3de1 868 if (pci_init_multifunction(bus, pci_dev)) {
30607764 869 do_pci_unregister_device(pci_dev);
6eab3de1
IY
870 return NULL;
871 }
0ac32c83
FB
872
873 if (!config_read)
874 config_read = pci_default_read_config;
875 if (!config_write)
876 config_write = pci_default_write_config;
69b91039
FB
877 pci_dev->config_read = config_read;
878 pci_dev->config_write = config_write;
30468f78 879 bus->devices[devfn] = pci_dev;
f16c4abf 880 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB
881 return pci_dev;
882}
883
5851e08c
AL
884static void pci_unregister_io_regions(PCIDevice *pci_dev)
885{
886 PCIIORegion *r;
887 int i;
888
889 for(i = 0; i < PCI_NUM_REGIONS; i++) {
890 r = &pci_dev->io_regions[i];
182f9c8a 891 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 892 continue;
03952339 893 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 894 }
e01fd687
AW
895
896 pci_unregister_vga(pci_dev);
5851e08c
AL
897}
898
a36a344d 899static int pci_unregister_device(DeviceState *dev)
5851e08c 900{
40021f08
AL
901 PCIDevice *pci_dev = PCI_DEVICE(dev);
902 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL
903
904 pci_unregister_io_regions(pci_dev);
230741dc 905 pci_del_option_rom(pci_dev);
7cf1b0fd 906
f90c2bcd
AW
907 if (pc->exit) {
908 pc->exit(pci_dev);
909 }
5851e08c 910
925fe64a 911 do_pci_unregister_device(pci_dev);
5851e08c
AL
912 return 0;
913}
914
e824b2cc
AK
915void pci_register_bar(PCIDevice *pci_dev, int region_num,
916 uint8_t type, MemoryRegion *memory)
69b91039
FB
917{
918 PCIIORegion *r;
d7ce493a 919 uint32_t addr;
5a9ff381 920 uint64_t wmask;
cfc0be25 921 pcibus_t size = memory_region_size(memory);
a4c20c6a 922
2bbb9c2f
IY
923 assert(region_num >= 0);
924 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a
AL
925 if (size & (size-1)) {
926 fprintf(stderr, "ERROR: PCI region size must be pow2 "
89e8b13c 927 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
a4c20c6a
AL
928 exit(1);
929 }
930
69b91039 931 r = &pci_dev->io_regions[region_num];
182f9c8a 932 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB
933 r->size = size;
934 r->type = type;
79ff8cb0 935 r->memory = NULL;
b7ee1603
MT
936
937 wmask = ~(size - 1);
b3b11697 938 addr = pci_bar(pci_dev, region_num);
d7ce493a 939 if (region_num == PCI_ROM_SLOT) {
ebabb67a 940 /* ROM enable bit is writable */
5330de09 941 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 942 }
b0ff8eb2 943 pci_set_long(pci_dev->config + addr, type);
14421258
IY
944 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
945 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
946 pci_set_quad(pci_dev->wmask + addr, wmask);
947 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
948 } else {
949 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
950 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
951 }
79ff8cb0 952 pci_dev->io_regions[region_num].memory = memory;
5968eca3 953 pci_dev->io_regions[region_num].address_space
cfc0be25 954 = type & PCI_BASE_ADDRESS_SPACE_IO
5968eca3
AK
955 ? pci_dev->bus->address_space_io
956 : pci_dev->bus->address_space_mem;
79ff8cb0
AK
957}
958
e01fd687
AW
959static void pci_update_vga(PCIDevice *pci_dev)
960{
961 uint16_t cmd;
962
963 if (!pci_dev->has_vga) {
964 return;
965 }
966
967 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
968
969 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
970 cmd & PCI_COMMAND_MEMORY);
971 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
972 cmd & PCI_COMMAND_IO);
973 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
974 cmd & PCI_COMMAND_IO);
975}
976
977void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
978 MemoryRegion *io_lo, MemoryRegion *io_hi)
979{
980 assert(!pci_dev->has_vga);
981
982 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
983 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
984 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
985 QEMU_PCI_VGA_MEM_BASE, mem, 1);
986
987 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
988 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
989 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
990 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
991
992 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
993 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
994 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
995 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
996 pci_dev->has_vga = true;
997
998 pci_update_vga(pci_dev);
999}
1000
1001void pci_unregister_vga(PCIDevice *pci_dev)
1002{
1003 if (!pci_dev->has_vga) {
1004 return;
1005 }
1006
1007 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1008 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1009 memory_region_del_subregion(pci_dev->bus->address_space_io,
1010 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1011 memory_region_del_subregion(pci_dev->bus->address_space_io,
1012 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1013 pci_dev->has_vga = false;
1014}
1015
16a96f28
AK
1016pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1017{
1018 return pci_dev->io_regions[region_num].addr;
1019}
1020
876a350d
MT
1021static pcibus_t pci_bar_address(PCIDevice *d,
1022 int reg, uint8_t type, pcibus_t size)
1023{
1024 pcibus_t new_addr, last_addr;
1025 int bar = pci_bar(d, reg);
1026 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1027
1028 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1029 if (!(cmd & PCI_COMMAND_IO)) {
1030 return PCI_BAR_UNMAPPED;
1031 }
1032 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1033 last_addr = new_addr + size - 1;
9f1a029a
HP
1034 /* Check if 32 bit BAR wraps around explicitly.
1035 * TODO: make priorities correct and remove this work around.
1036 */
1037 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
876a350d
MT
1038 return PCI_BAR_UNMAPPED;
1039 }
1040 return new_addr;
1041 }
1042
1043 if (!(cmd & PCI_COMMAND_MEMORY)) {
1044 return PCI_BAR_UNMAPPED;
1045 }
1046 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1047 new_addr = pci_get_quad(d->config + bar);
1048 } else {
1049 new_addr = pci_get_long(d->config + bar);
1050 }
1051 /* the ROM slot has a specific enable bit */
1052 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1053 return PCI_BAR_UNMAPPED;
1054 }
1055 new_addr &= ~(size - 1);
1056 last_addr = new_addr + size - 1;
1057 /* NOTE: we do not support wrapping */
1058 /* XXX: as we cannot support really dynamic
1059 mappings, we handle specific values as invalid
1060 mappings. */
1061 if (last_addr <= new_addr || new_addr == 0 ||
1062 last_addr == PCI_BAR_UNMAPPED) {
1063 return PCI_BAR_UNMAPPED;
1064 }
1065
1066 /* Now pcibus_t is 64bit.
1067 * Check if 32 bit BAR wraps around explicitly.
1068 * Without this, PC ide doesn't work well.
1069 * TODO: remove this work around.
1070 */
1071 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1072 return PCI_BAR_UNMAPPED;
1073 }
1074
1075 /*
1076 * OS is allowed to set BAR beyond its addressable
1077 * bits. For example, 32 bit OS can set 64bit bar
1078 * to >4G. Check it. TODO: we might need to support
1079 * it in the future for e.g. PAE.
1080 */
a8170e5e 1081 if (last_addr >= HWADDR_MAX) {
876a350d
MT
1082 return PCI_BAR_UNMAPPED;
1083 }
1084
1085 return new_addr;
1086}
1087
0ac32c83
FB
1088static void pci_update_mappings(PCIDevice *d)
1089{
1090 PCIIORegion *r;
876a350d 1091 int i;
7df32ca0 1092 pcibus_t new_addr;
3b46e624 1093
8a8696a3 1094 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1095 r = &d->io_regions[i];
a9688570
IY
1096
1097 /* this region isn't registered */
ec503442 1098 if (!r->size)
a9688570
IY
1099 continue;
1100
876a350d 1101 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY
1102
1103 /* This bar isn't changed */
7df32ca0 1104 if (new_addr == r->addr)
a9688570
IY
1105 continue;
1106
1107 /* now do the real mapping */
1108 if (r->addr != PCI_BAR_UNMAPPED) {
03952339 1109 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1110 }
a9688570
IY
1111 r->addr = new_addr;
1112 if (r->addr != PCI_BAR_UNMAPPED) {
8b881e77
AK
1113 memory_region_add_subregion_overlap(r->address_space,
1114 r->addr, r->memory, 1);
a9688570 1115 }
0ac32c83 1116 }
e01fd687
AW
1117
1118 pci_update_vga(d);
0ac32c83
FB
1119}
1120
a7b15a5c
MT
1121static inline int pci_irq_disabled(PCIDevice *d)
1122{
1123 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1124}
1125
1126/* Called after interrupt disabled field update in config space,
1127 * assert/deassert interrupts if necessary.
1128 * Gets original interrupt disable bit value (before update). */
1129static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1130{
1131 int i, disabled = pci_irq_disabled(d);
1132 if (disabled == was_irq_disabled)
1133 return;
1134 for (i = 0; i < PCI_NUM_PINS; ++i) {
1135 int state = pci_irq_state(d, i);
1136 pci_change_irq_level(d, i, disabled ? -state : state);
1137 }
1138}
1139
5fafdf24 1140uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1141 uint32_t address, int len)
69b91039 1142{
5029fe12 1143 uint32_t val = 0;
42e4126b 1144
5029fe12
IY
1145 memcpy(&val, d->config + address, len);
1146 return le32_to_cpu(val);
0ac32c83
FB
1147}
1148
d7efb7e0 1149void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1150{
a7b15a5c 1151 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1152 uint32_t val = val_in;
0ac32c83 1153
42e4126b 1154 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1155 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY
1156 uint8_t w1cmask = d->w1cmask[addr + i];
1157 assert(!(wmask & w1cmask));
91011d4f 1158 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1159 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1160 }
260c0cd3 1161 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY
1162 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1163 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1164 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1165 pci_update_mappings(d);
a7b15a5c 1166
1c380f94 1167 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1168 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK
1169 memory_region_set_enabled(&d->bus_master_enable_region,
1170 pci_get_word(d->config + PCI_COMMAND)
1171 & PCI_COMMAND_MASTER);
1172 }
95d65800 1173
d7efb7e0
KO
1174 msi_write_config(d, addr, val_in, l);
1175 msix_write_config(d, addr, val_in, l);
69b91039
FB
1176}
1177
502a5395
PB
1178/***********************************************************/
1179/* generic PCI irq support */
30468f78 1180
502a5395 1181/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1182static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1183{
a60380a5 1184 PCIDevice *pci_dev = opaque;
80b3ada7 1185 int change;
3b46e624 1186
d036bb21 1187 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB
1188 if (!change)
1189 return;
d2b59317 1190
d036bb21 1191 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1192 pci_update_irq_status(pci_dev);
a7b15a5c
MT
1193 if (pci_irq_disabled(pci_dev))
1194 return;
d036bb21 1195 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB
1196}
1197
d98f08f5
MA
1198static inline int pci_intx(PCIDevice *pci_dev)
1199{
1200 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1201}
1202
1203qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1204{
1205 int intx = pci_intx(pci_dev);
1206
1207 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1208}
1209
1210void pci_set_irq(PCIDevice *pci_dev, int level)
1211{
1212 int intx = pci_intx(pci_dev);
1213 pci_irq_handler(pci_dev, intx, level);
1214}
1215
3afa9bb4
MT
1216/* Special hooks used by device assignment */
1217void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1218{
0889464a 1219 assert(pci_bus_is_root(bus));
3afa9bb4
MT
1220 bus->route_intx_to_irq = route_intx_to_irq;
1221}
1222
1223PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1224{
1225 PCIBus *bus;
1226
1227 do {
1228 bus = dev->bus;
1229 pin = bus->map_irq(dev, pin);
1230 dev = bus->parent_dev;
1231 } while (dev);
05c0621e
AW
1232
1233 if (!bus->route_intx_to_irq) {
312fd5f2 1234 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW
1235 object_get_typename(OBJECT(bus->qbus.parent)));
1236 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1237 }
1238
3afa9bb4 1239 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK
1240}
1241
d6e65d54
AW
1242bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1243{
1244 return old->mode != new->mode || old->irq != new->irq;
1245}
1246
0ae16251
JK
1247void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1248{
1249 PCIDevice *dev;
1250 PCIBus *sec;
1251 int i;
1252
1253 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1254 dev = bus->devices[i];
1255 if (dev && dev->intx_routing_notifier) {
1256 dev->intx_routing_notifier(dev);
1257 }
e5368f0d
AW
1258 }
1259
1260 QLIST_FOREACH(sec, &bus->child, sibling) {
1261 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK
1262 }
1263}
1264
1265void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1266 PCIINTxRoutingNotifier notifier)
1267{
1268 dev->intx_routing_notifier = notifier;
69b91039
FB
1269}
1270
91e56159
IY
1271/*
1272 * PCI-to-PCI bridge specification
1273 * 9.1: Interrupt routing. Table 9-1
1274 *
1275 * the PCI Express Base Specification, Revision 2.1
1276 * 2.2.8.1: INTx interrutp signaling - Rules
1277 * the Implementation Note
1278 * Table 2-20
1279 */
1280/*
1281 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1282 * 0-origin unlike PCI interrupt pin register.
1283 */
1284int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1285{
1286 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1287}
1288
502a5395
PB
1289/***********************************************************/
1290/* monitor info on PCI */
0ac32c83 1291
6650ee6d
PB
1292typedef struct {
1293 uint16_t class;
1294 const char *desc;
5e0259e7
GN
1295 const char *fw_name;
1296 uint16_t fw_ign_bits;
6650ee6d
PB
1297} pci_class_desc;
1298
09bc878a 1299static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1300{
5e0259e7
GN
1301 { 0x0001, "VGA controller", "display"},
1302 { 0x0100, "SCSI controller", "scsi"},
1303 { 0x0101, "IDE controller", "ide"},
1304 { 0x0102, "Floppy controller", "fdc"},
1305 { 0x0103, "IPI controller", "ipi"},
1306 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS
1307 { 0x0106, "SATA controller"},
1308 { 0x0107, "SAS controller"},
1309 { 0x0180, "Storage controller"},
5e0259e7
GN
1310 { 0x0200, "Ethernet controller", "ethernet"},
1311 { 0x0201, "Token Ring controller", "token-ring"},
1312 { 0x0202, "FDDI controller", "fddi"},
1313 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1314 { 0x0280, "Network controller"},
5e0259e7 1315 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS
1316 { 0x0301, "XGA controller"},
1317 { 0x0302, "3D controller"},
1318 { 0x0380, "Display controller"},
5e0259e7
GN
1319 { 0x0400, "Video controller", "video"},
1320 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1321 { 0x0402, "Phone"},
602ef4d9 1322 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1323 { 0x0480, "Multimedia controller"},
5e0259e7
GN
1324 { 0x0500, "RAM controller", "memory"},
1325 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1326 { 0x0580, "Memory controller"},
5e0259e7
GN
1327 { 0x0600, "Host bridge", "host"},
1328 { 0x0601, "ISA bridge", "isa"},
1329 { 0x0602, "EISA bridge", "eisa"},
1330 { 0x0603, "MC bridge", "mca"},
4c41425d 1331 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN
1332 { 0x0605, "PCMCIA bridge", "pcmcia"},
1333 { 0x0606, "NUBUS bridge", "nubus"},
1334 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS
1335 { 0x0608, "RACEWAY bridge"},
1336 { 0x0680, "Bridge"},
5e0259e7
GN
1337 { 0x0700, "Serial port", "serial"},
1338 { 0x0701, "Parallel port", "parallel"},
1339 { 0x0800, "Interrupt controller", "interrupt-controller"},
1340 { 0x0801, "DMA controller", "dma-controller"},
1341 { 0x0802, "Timer", "timer"},
1342 { 0x0803, "RTC", "rtc"},
1343 { 0x0900, "Keyboard", "keyboard"},
1344 { 0x0901, "Pen", "pen"},
1345 { 0x0902, "Mouse", "mouse"},
1346 { 0x0A00, "Dock station", "dock", 0x00ff},
1347 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1348 { 0x0c00, "Fireware contorller", "fireware"},
1349 { 0x0c01, "Access bus controller", "access-bus"},
1350 { 0x0c02, "SSA controller", "ssa"},
1351 { 0x0c03, "USB controller", "usb"},
1352 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1353 { 0x0c05, "SMBus"},
6650ee6d
PB
1354 { 0, NULL}
1355};
1356
163c8a59 1357static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP
1358 void (*fn)(PCIBus *b, PCIDevice *d,
1359 void *opaque),
1360 void *opaque)
30468f78 1361{
163c8a59
LC
1362 PCIDevice *d;
1363 int devfn;
30468f78 1364
163c8a59
LC
1365 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1366 d = bus->devices[devfn];
1367 if (d) {
7aa8cbb9 1368 fn(bus, d, opaque);
163c8a59
LC
1369 }
1370 }
1371}
1372
1373void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP
1374 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1375 void *opaque)
163c8a59 1376{
d662210a 1377 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC
1378
1379 if (bus) {
7aa8cbb9 1380 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC
1381 }
1382}
1383
79627472 1384static const pci_class_desc *get_class_desc(int class)
163c8a59 1385{
79627472 1386 const pci_class_desc *desc;
163c8a59 1387
79627472
LC
1388 desc = pci_class_descriptions;
1389 while (desc->desc && class != desc->class) {
1390 desc++;
30468f78 1391 }
b4dccd8d 1392
79627472
LC
1393 return desc;
1394}
14421258 1395
79627472 1396static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1397
79627472
LC
1398static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1399{
1400 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1401 int i;
163c8a59 1402
79627472
LC
1403 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1404 const PCIIORegion *r = &dev->io_regions[i];
1405 PciMemoryRegionList *region;
1406
1407 if (!r->size) {
1408 continue;
502a5395 1409 }
163c8a59 1410
79627472
LC
1411 region = g_malloc0(sizeof(*region));
1412 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1413
79627472
LC
1414 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1415 region->value->type = g_strdup("io");
1416 } else {
1417 region->value->type = g_strdup("memory");
1418 region->value->has_prefetch = true;
1419 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1420 region->value->has_mem_type_64 = true;
1421 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1422 }
163c8a59 1423
79627472
LC
1424 region->value->bar = i;
1425 region->value->address = r->addr;
1426 region->value->size = r->size;
163c8a59 1427
79627472
LC
1428 /* XXX: waiting for the qapi to support GSList */
1429 if (!cur_item) {
1430 head = cur_item = region;
1431 } else {
1432 cur_item->next = region;
1433 cur_item = region;
163c8a59 1434 }
80b3ada7 1435 }
384d8876 1436
79627472 1437 return head;
163c8a59
LC
1438}
1439
79627472
LC
1440static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1441 int bus_num)
163c8a59 1442{
79627472 1443 PciBridgeInfo *info;
163c8a59 1444
79627472 1445 info = g_malloc0(sizeof(*info));
163c8a59 1446
79627472
LC
1447 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1448 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1449 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1450
79627472
LC
1451 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1452 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1453 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1454
79627472
LC
1455 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1456 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1457 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1458
79627472
LC
1459 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1460 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1461 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1462
79627472 1463 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1464 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC
1465 if (child_bus) {
1466 info->has_devices = true;
1467 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1468 }
163c8a59
LC
1469 }
1470
79627472 1471 return info;
163c8a59
LC
1472}
1473
79627472
LC
1474static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1475 int bus_num)
163c8a59 1476{
79627472
LC
1477 const pci_class_desc *desc;
1478 PciDeviceInfo *info;
b5937f29 1479 uint8_t type;
79627472 1480 int class;
163c8a59 1481
79627472
LC
1482 info = g_malloc0(sizeof(*info));
1483 info->bus = bus_num;
1484 info->slot = PCI_SLOT(dev->devfn);
1485 info->function = PCI_FUNC(dev->devfn);
1486
1487 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
6f88009e 1488 info->class_info.q_class = class;
79627472
LC
1489 desc = get_class_desc(class);
1490 if (desc->desc) {
1491 info->class_info.has_desc = true;
1492 info->class_info.desc = g_strdup(desc->desc);
1493 }
1494
1495 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1496 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1497 info->regions = qmp_query_pci_regions(dev);
1498 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC
1499
1500 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC
1501 info->has_irq = true;
1502 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC
1503 }
1504
b5937f29
IY
1505 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1506 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC
1507 info->has_pci_bridge = true;
1508 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
163c8a59
LC
1509 }
1510
79627472 1511 return info;
163c8a59
LC
1512}
1513
79627472 1514static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1515{
79627472 1516 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1517 PCIDevice *dev;
79627472 1518 int devfn;
163c8a59
LC
1519
1520 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1521 dev = bus->devices[devfn];
1522 if (dev) {
79627472
LC
1523 info = g_malloc0(sizeof(*info));
1524 info->value = qmp_query_pci_device(dev, bus, bus_num);
1525
1526 /* XXX: waiting for the qapi to support GSList */
1527 if (!cur_item) {
1528 head = cur_item = info;
1529 } else {
1530 cur_item->next = info;
1531 cur_item = info;
1532 }
163c8a59 1533 }
1074df4f 1534 }
163c8a59 1535
79627472 1536 return head;
1074df4f
IY
1537}
1538
79627472 1539static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1540{
79627472
LC
1541 PciInfo *info = NULL;
1542
d662210a 1543 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1544 if (bus) {
79627472
LC
1545 info = g_malloc0(sizeof(*info));
1546 info->bus = bus_num;
1547 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1548 }
163c8a59 1549
79627472 1550 return info;
f2aa58c6
FB
1551}
1552
79627472 1553PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1554{
79627472 1555 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1556 PCIHostState *host_bridge;
163c8a59 1557
7588e2b0 1558 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1559 info = g_malloc0(sizeof(*info));
7588e2b0 1560 info->value = qmp_query_pci_bus(host_bridge->bus, 0);
79627472
LC
1561
1562 /* XXX: waiting for the qapi to support GSList */
1563 if (!cur_item) {
1564 head = cur_item = info;
1565 } else {
1566 cur_item->next = info;
1567 cur_item = info;
163c8a59 1568 }
e822a52a 1569 }
163c8a59 1570
79627472 1571 return head;
77d4bc34 1572}
a41b2ff2 1573
cb457d76
AL
1574static const char * const pci_nic_models[] = {
1575 "ne2k_pci",
1576 "i82551",
1577 "i82557b",
1578 "i82559er",
1579 "rtl8139",
1580 "e1000",
1581 "pcnet",
1582 "virtio",
1583 NULL
1584};
1585
9d07d757
PB
1586static const char * const pci_nic_names[] = {
1587 "ne2k_pci",
1588 "i82551",
1589 "i82557b",
1590 "i82559er",
1591 "rtl8139",
1592 "e1000",
1593 "pcnet",
53c25cea 1594 "virtio-net-pci",
cb457d76
AL
1595 NULL
1596};
1597
a41b2ff2 1598/* Initialize a PCI NIC. */
33e66b86 1599/* FIXME callers should check for failure, but don't */
29b358f9
DG
1600PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
1601 const char *default_model,
5607c388 1602 const char *default_devaddr)
a41b2ff2 1603{
5607c388 1604 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
07caea31
MA
1605 PCIBus *bus;
1606 int devfn;
5607c388 1607 PCIDevice *pci_dev;
9d07d757 1608 DeviceState *dev;
cb457d76
AL
1609 int i;
1610
07caea31
MA
1611 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1612 if (i < 0)
1613 return NULL;
1614
29b358f9 1615 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
07caea31 1616 if (!bus) {
1ecda02b
MA
1617 error_report("Invalid PCI device address %s for device %s",
1618 devaddr, pci_nic_names[i]);
07caea31
MA
1619 return NULL;
1620 }
1621
499cf102 1622 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
9ee05825 1623 dev = &pci_dev->qdev;
1cc33683 1624 qdev_set_nic_properties(dev, nd);
07caea31
MA
1625 if (qdev_init(dev) < 0)
1626 return NULL;
9ee05825 1627 return pci_dev;
a41b2ff2
PB
1628}
1629
29b358f9
DG
1630PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1631 const char *default_model,
07caea31
MA
1632 const char *default_devaddr)
1633{
1634 PCIDevice *res;
1635
1636 if (qemu_show_nic_models(nd->model, pci_nic_models))
1637 exit(0);
1638
29b358f9 1639 res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
07caea31
MA
1640 if (!res)
1641 exit(1);
1642 return res;
1643}
1644
129d42fb
AJ
1645PCIDevice *pci_vga_init(PCIBus *bus)
1646{
1647 switch (vga_interface_type) {
1648 case VGA_CIRRUS:
1649 return pci_create_simple(bus, -1, "cirrus-vga");
1650 case VGA_QXL:
1651 return pci_create_simple(bus, -1, "qxl-vga");
1652 case VGA_STD:
1653 return pci_create_simple(bus, -1, "VGA");
1654 case VGA_VMWARE:
1655 return pci_create_simple(bus, -1, "vmware-svga");
1656 case VGA_NONE:
1657 default: /* Other non-PCI types. Checking for unsupported types is already
1658 done in vl.c. */
1659 return NULL;
1660 }
1661}
1662
929176c3
MT
1663/* Whether a given bus number is in range of the secondary
1664 * bus of the given bridge device. */
1665static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1666{
1667 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1668 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1669 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1670 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1671}
1672
d662210a 1673static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 1674{
470e6363 1675 PCIBus *sec;
3ae80618 1676
470e6363 1677 if (!bus) {
e822a52a 1678 return NULL;
470e6363 1679 }
3ae80618 1680
e822a52a
IY
1681 if (pci_bus_num(bus) == bus_num) {
1682 return bus;
1683 }
1684
929176c3 1685 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 1686 if (!pci_bus_is_root(bus) &&
929176c3
MT
1687 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1688 return NULL;
1689 }
1690
e822a52a 1691 /* try child bus */
929176c3
MT
1692 for (; bus; bus = sec) {
1693 QLIST_FOREACH(sec, &bus->child, sibling) {
0889464a 1694 assert(!pci_bus_is_root(sec));
929176c3
MT
1695 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1696 return sec;
1697 }
1698 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1699 break;
c021f8e6 1700 }
e822a52a
IY
1701 }
1702 }
1703
1704 return NULL;
3ae80618
AL
1705}
1706
eb0acfdd
MT
1707void pci_for_each_bus_depth_first(PCIBus *bus,
1708 void *(*begin)(PCIBus *bus, void *parent_state),
1709 void (*end)(PCIBus *bus, void *state),
1710 void *parent_state)
1711{
1712 PCIBus *sec;
1713 void *state;
1714
1715 if (!bus) {
1716 return;
1717 }
1718
1719 if (begin) {
1720 state = begin(bus, parent_state);
1721 } else {
1722 state = parent_state;
1723 }
1724
1725 QLIST_FOREACH(sec, &bus->child, sibling) {
1726 pci_for_each_bus_depth_first(sec, begin, end, state);
1727 }
1728
1729 if (end) {
1730 end(bus, state);
1731 }
1732}
1733
1734
5256d8bf 1735PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 1736{
d662210a 1737 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL
1738
1739 if (!bus)
1740 return NULL;
1741
5256d8bf 1742 return bus->devices[devfn];
3ae80618
AL
1743}
1744
d307af79 1745static int pci_qdev_init(DeviceState *qdev)
6b1b92d3
PB
1746{
1747 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 1748 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
6b1b92d3 1749 PCIBus *bus;
113f89df 1750 int rc;
ab85ceb1 1751 bool is_default_rom;
6b1b92d3 1752
a9f49946 1753 /* initialize cap_present for pci_is_express() and pci_config_size() */
40021f08 1754 if (pc->is_express) {
a9f49946
IY
1755 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1756 }
1757
fef7fbc9 1758 bus = PCI_BUS(qdev_get_parent_bus(qdev));
6e008585
AL
1759 pci_dev = do_pci_register_device(pci_dev, bus,
1760 object_get_typename(OBJECT(qdev)),
1761 pci_dev->devfn);
09e3acc6
GH
1762 if (pci_dev == NULL)
1763 return -1;
2897ae02 1764
40021f08
AL
1765 if (pc->init) {
1766 rc = pc->init(pci_dev);
c2afc922
IY
1767 if (rc != 0) {
1768 do_pci_unregister_device(pci_dev);
1769 return rc;
1770 }
925fe64a 1771 }
8c52c8f3
GH
1772
1773 /* rom loading */
ab85ceb1 1774 is_default_rom = false;
40021f08
AL
1775 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1776 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW
1777 is_default_rom = true;
1778 }
1779 pci_add_option_rom(pci_dev, is_default_rom);
8c52c8f3 1780
ee995ffb
GH
1781 return 0;
1782}
1783
49823868
IY
1784PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1785 const char *name)
6b1b92d3
PB
1786{
1787 DeviceState *dev;
1788
02e2da45 1789 dev = qdev_create(&bus->qbus, name);
09f1bbcd 1790 qdev_prop_set_int32(dev, "addr", devfn);
49823868 1791 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 1792 return PCI_DEVICE(dev);
71077c1c 1793}
6b1b92d3 1794
49823868
IY
1795PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1796 bool multifunction,
1797 const char *name)
71077c1c 1798{
49823868 1799 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 1800 qdev_init_nofail(&dev->qdev);
71077c1c 1801 return dev;
6b1b92d3 1802}
6f4cbd39 1803
49823868
IY
1804PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1805{
1806 return pci_create_multifunction(bus, devfn, false, name);
1807}
1808
1809PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1810{
1811 return pci_create_simple_multifunction(bus, devfn, false, name);
1812}
1813
b56d701f 1814static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT
1815{
1816 int offset = PCI_CONFIG_HEADER_SIZE;
1817 int i;
b56d701f 1818 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT
1819 if (pdev->used[i])
1820 offset = i + 1;
1821 else if (i - offset + 1 == size)
1822 return offset;
b56d701f 1823 }
6f4cbd39
MT
1824 return 0;
1825}
1826
1827static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1828 uint8_t *prev_p)
1829{
1830 uint8_t next, prev;
1831
1832 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1833 return 0;
1834
1835 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1836 prev = next + PCI_CAP_LIST_NEXT)
1837 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1838 break;
1839
1840 if (prev_p)
1841 *prev_p = prev;
1842 return next;
1843}
1844
c9abe111
JK
1845static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1846{
1847 uint8_t next, prev, found = 0;
1848
1849 if (!(pdev->used[offset])) {
1850 return 0;
1851 }
1852
1853 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1854
1855 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1856 prev = next + PCI_CAP_LIST_NEXT) {
1857 if (next <= offset && next > found) {
1858 found = next;
1859 }
1860 }
1861 return found;
1862}
1863
ab85ceb1
SW
1864/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1865 This is needed for an option rom which is used for more than one device. */
1866static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1867{
1868 uint16_t vendor_id;
1869 uint16_t device_id;
1870 uint16_t rom_vendor_id;
1871 uint16_t rom_device_id;
1872 uint16_t rom_magic;
1873 uint16_t pcir_offset;
1874 uint8_t checksum;
1875
1876 /* Words in rom data are little endian (like in PCI configuration),
1877 so they can be read / written with pci_get_word / pci_set_word. */
1878
1879 /* Only a valid rom will be patched. */
1880 rom_magic = pci_get_word(ptr);
1881 if (rom_magic != 0xaa55) {
1882 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1883 return;
1884 }
1885 pcir_offset = pci_get_word(ptr + 0x18);
1886 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1887 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1888 return;
1889 }
1890
1891 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1892 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1893 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1894 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1895
1896 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1897 vendor_id, device_id, rom_vendor_id, rom_device_id);
1898
1899 checksum = ptr[6];
1900
1901 if (vendor_id != rom_vendor_id) {
1902 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1903 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1904 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1905 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1906 ptr[6] = checksum;
1907 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1908 }
1909
1910 if (device_id != rom_device_id) {
1911 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1912 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1913 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1914 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1915 ptr[6] = checksum;
1916 pci_set_word(ptr + pcir_offset + 6, device_id);
1917 }
1918}
1919
c2039bd0 1920/* Add an option rom for the device */
ab85ceb1 1921static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
c2039bd0
AL
1922{
1923 int size;
1924 char *path;
1925 void *ptr;
1724f049 1926 char name[32];
4be9f0d1 1927 const VMStateDescription *vmsd;
c2039bd0 1928
8c52c8f3
GH
1929 if (!pdev->romfile)
1930 return 0;
1931 if (strlen(pdev->romfile) == 0)
1932 return 0;
1933
88169ddf
GH
1934 if (!pdev->rom_bar) {
1935 /*
1936 * Load rom via fw_cfg instead of creating a rom bar,
1937 * for 0.11 compatibility.
1938 */
1939 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1940 if (class == 0x0300) {
1941 rom_add_vga(pdev->romfile);
1942 } else {
2e55e842 1943 rom_add_option(pdev->romfile, -1);
88169ddf
GH
1944 }
1945 return 0;
1946 }
1947
8c52c8f3 1948 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 1949 if (path == NULL) {
7267c094 1950 path = g_strdup(pdev->romfile);
c2039bd0
AL
1951 }
1952
1953 size = get_image_size(path);
8c52c8f3 1954 if (size < 0) {
1ecda02b 1955 error_report("%s: failed to find romfile \"%s\"",
8c7f3dd0
SH
1956 __func__, pdev->romfile);
1957 g_free(path);
1958 return -1;
1959 } else if (size == 0) {
1960 error_report("%s: ignoring empty romfile \"%s\"",
1961 __func__, pdev->romfile);
7267c094 1962 g_free(path);
8c52c8f3
GH
1963 return -1;
1964 }
c2039bd0
AL
1965 if (size & (size - 1)) {
1966 size = 1 << qemu_fls(size);
1967 }
1968
4be9f0d1
AL
1969 vmsd = qdev_get_vmsd(DEVICE(pdev));
1970
1971 if (vmsd) {
1972 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1973 } else {
f79f2bfc 1974 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 1975 }
14caaf7f 1976 pdev->has_rom = true;
49946538 1977 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort);
c5705a77 1978 vmstate_register_ram(&pdev->rom, &pdev->qdev);
14caaf7f 1979 ptr = memory_region_get_ram_ptr(&pdev->rom);
c2039bd0 1980 load_image(path, ptr);
7267c094 1981 g_free(path);
c2039bd0 1982
ab85ceb1
SW
1983 if (is_default_rom) {
1984 /* Only the default rom images will be patched (if needed). */
1985 pci_patch_ids(pdev, ptr, size);
1986 }
1987
e824b2cc 1988 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL
1989
1990 return 0;
1991}
1992
230741dc
AW
1993static void pci_del_option_rom(PCIDevice *pdev)
1994{
14caaf7f 1995 if (!pdev->has_rom)
230741dc
AW
1996 return;
1997
c5705a77 1998 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 1999 pdev->has_rom = false;
230741dc
AW
2000}
2001
ca77089d
IY
2002/*
2003 * if !offset
2004 * Reserve space and add capability to the linked list in pci config space
2005 *
2006 * if offset = 0,
2007 * Find and reserve space and add capability to the linked list
2008 * in pci config space */
2009int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2010 uint8_t offset, uint8_t size)
cd9aa33e
LE
2011{
2012 int ret;
2013 Error *local_err = NULL;
2014
2015 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2016 if (local_err) {
2017 assert(ret < 0);
2018 error_report("%s", error_get_pretty(local_err));
2019 error_free(local_err);
2020 } else {
2021 /* success implies a positive offset in config space */
2022 assert(ret > 0);
2023 }
2024 return ret;
2025}
2026
2027int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2028 uint8_t offset, uint8_t size,
2029 Error **errp)
6f4cbd39 2030{
ca77089d 2031 uint8_t *config;
c9abe111
JK
2032 int i, overlapping_cap;
2033
ca77089d
IY
2034 if (!offset) {
2035 offset = pci_find_space(pdev, size);
2036 if (!offset) {
cd9aa33e 2037 error_setg(errp, "out of PCI config space");
ca77089d
IY
2038 return -ENOSPC;
2039 }
c9abe111
JK
2040 } else {
2041 /* Verify that capabilities don't overlap. Note: device assignment
2042 * depends on this check to verify that the device is not broken.
2043 * Should never trigger for emulated devices, but it's helpful
2044 * for debugging these. */
2045 for (i = offset; i < offset + size; i++) {
2046 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2047 if (overlapping_cap) {
cd9aa33e
LE
2048 error_setg(errp, "%s:%02x:%02x.%x "
2049 "Attempt to add PCI capability %x at offset "
2050 "%x overlaps existing capability %x at offset %x",
2051 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2052 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2053 cap_id, offset, overlapping_cap, i);
c9abe111
JK
2054 return -EINVAL;
2055 }
2056 }
ca77089d
IY
2057 }
2058
2059 config = pdev->config + offset;
6f4cbd39
MT
2060 config[PCI_CAP_LIST_ID] = cap_id;
2061 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2062 pdev->config[PCI_CAPABILITY_LIST] = offset;
2063 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2064 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT
2065 /* Make capability read-only by default */
2066 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT
2067 /* Check capability by default */
2068 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT
2069 return offset;
2070}
2071
2072/* Unlink capability from the pci config space. */
2073void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2074{
2075 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2076 if (!offset)
2077 return;
2078 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2079 /* Make capability writable again */
6f4cbd39 2080 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2081 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT
2082 /* Clear cmask as device-specific registers can't be checked */
2083 memset(pdev->cmask + offset, 0, size);
e26631b7 2084 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT
2085
2086 if (!pdev->config[PCI_CAPABILITY_LIST])
2087 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2088}
2089
6f4cbd39
MT
2090uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2091{
2092 return pci_find_capability_list(pdev, cap_id, NULL);
2093}
10c4c98a
GH
2094
2095static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2096{
2097 PCIDevice *d = (PCIDevice *)dev;
2098 const pci_class_desc *desc;
2099 char ctxt[64];
2100 PCIIORegion *r;
2101 int i, class;
2102
b0ff8eb2 2103 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH
2104 desc = pci_class_descriptions;
2105 while (desc->desc && class != desc->class)
2106 desc++;
2107 if (desc->desc) {
2108 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2109 } else {
2110 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2111 }
2112
2113 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2114 "pci id %04x:%04x (sub %04x:%04x)\n",
7f5feab4 2115 indent, "", ctxt, pci_bus_num(d->bus),
e822a52a 2116 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY
2117 pci_get_word(d->config + PCI_VENDOR_ID),
2118 pci_get_word(d->config + PCI_DEVICE_ID),
2119 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2120 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH
2121 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2122 r = &d->io_regions[i];
2123 if (!r->size)
2124 continue;
89e8b13c
IY
2125 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2126 " [0x%"FMT_PCIBUS"]\n",
2127 indent, "",
0392a017 2128 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH
2129 r->addr, r->addr + r->size - 1);
2130 }
2131}
03587182 2132
5e0259e7
GN
2133static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2134{
2135 PCIDevice *d = (PCIDevice *)dev;
2136 const char *name = NULL;
2137 const pci_class_desc *desc = pci_class_descriptions;
2138 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2139
2140 while (desc->desc &&
2141 (class & ~desc->fw_ign_bits) !=
2142 (desc->class & ~desc->fw_ign_bits)) {
2143 desc++;
2144 }
2145
2146 if (desc->desc) {
2147 name = desc->fw_name;
2148 }
2149
2150 if (name) {
2151 pstrcpy(buf, len, name);
2152 } else {
2153 snprintf(buf, len, "pci%04x,%04x",
2154 pci_get_word(d->config + PCI_VENDOR_ID),
2155 pci_get_word(d->config + PCI_DEVICE_ID));
2156 }
2157
2158 return buf;
2159}
2160
2161static char *pcibus_get_fw_dev_path(DeviceState *dev)
2162{
2163 PCIDevice *d = (PCIDevice *)dev;
2164 char path[50], name[33];
2165 int off;
2166
2167 off = snprintf(path, sizeof(path), "%s@%x",
2168 pci_dev_fw_name(dev, name, sizeof name),
2169 PCI_SLOT(d->devfn));
2170 if (PCI_FUNC(d->devfn))
2171 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2172 return g_strdup(path);
5e0259e7
GN
2173}
2174
4f43c1ff
AW
2175static char *pcibus_get_dev_path(DeviceState *dev)
2176{
a6a7005d
MT
2177 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2178 PCIDevice *t;
2179 int slot_depth;
2180 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2181 * 00 is added here to make this format compatible with
2182 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2183 * Slot.Function list specifies the slot and function numbers for all
2184 * devices on the path from root to the specific device. */
568f0690
DG
2185 const char *root_bus_path;
2186 int root_bus_len;
2991181a 2187 char slot[] = ":SS.F";
2991181a 2188 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT
2189 int path_len;
2190 char *path, *p;
2991181a 2191 int s;
a6a7005d 2192
568f0690
DG
2193 root_bus_path = pci_root_bus_path(d);
2194 root_bus_len = strlen(root_bus_path);
2195
a6a7005d
MT
2196 /* Calculate # of slots on path between device and root. */;
2197 slot_depth = 0;
2198 for (t = d; t; t = t->bus->parent_dev) {
2199 ++slot_depth;
2200 }
2201
568f0690 2202 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT
2203
2204 /* Allocate memory, fill in the terminating null byte. */
7267c094 2205 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT
2206 path[path_len] = '\0';
2207
568f0690 2208 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT
2209
2210 /* Fill in slot numbers. We walk up from device to root, so need to print
2211 * them in the reverse order, last to first. */
2212 p = path + path_len;
2213 for (t = d; t; t = t->bus->parent_dev) {
2214 p -= slot_len;
2991181a 2215 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2216 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT
2217 assert(s == slot_len);
2218 memcpy(p, slot, slot_len);
a6a7005d
MT
2219 }
2220
2221 return path;
4f43c1ff
AW
2222}
2223
f3006dd1
IY
2224static int pci_qdev_find_recursive(PCIBus *bus,
2225 const char *id, PCIDevice **pdev)
2226{
2227 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2228 if (!qdev) {
2229 return -ENODEV;
2230 }
2231
2232 /* roughly check if given qdev is pci device */
4be9f0d1 2233 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2234 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY
2235 return 0;
2236 }
2237 return -EINVAL;
2238}
2239
2240int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2241{
7588e2b0 2242 PCIHostState *host_bridge;
f3006dd1
IY
2243 int rc = -ENODEV;
2244
7588e2b0
DG
2245 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2246 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY
2247 if (!tmp) {
2248 rc = 0;
2249 break;
2250 }
2251 if (tmp != -ENODEV) {
2252 rc = tmp;
2253 }
2254 }
2255
2256 return rc;
2257}
f5e6fed8
AK
2258
2259MemoryRegion *pci_address_space(PCIDevice *dev)
2260{
2261 return dev->bus->address_space_mem;
2262}
e11d6439
RH
2263
2264MemoryRegion *pci_address_space_io(PCIDevice *dev)
2265{
2266 return dev->bus->address_space_io;
2267}
40021f08 2268
39bffca2
AL
2269static void pci_device_class_init(ObjectClass *klass, void *data)
2270{
2271 DeviceClass *k = DEVICE_CLASS(klass);
2272 k->init = pci_qdev_init;
39bffca2 2273 k->exit = pci_unregister_device;
0d936928 2274 k->bus_type = TYPE_PCI_BUS;
bce54474 2275 k->props = pci_props;
39bffca2
AL
2276}
2277
9eda7d37
AK
2278AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2279{
2280 PCIBus *bus = PCI_BUS(dev->bus);
2281
2282 if (bus->iommu_fn) {
2283 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
2284 }
2285
2286 if (bus->parent_dev) {
2287 /** We are ignoring the bus master DMA bit of the bridge
2288 * as it would complicate things such as VFIO for no good reason */
2289 return pci_device_iommu_address_space(bus->parent_dev);
2290 }
2291
2292 return &address_space_memory;
2293}
2294
e00387d5 2295void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2296{
e00387d5
AK
2297 bus->iommu_fn = fn;
2298 bus->iommu_opaque = opaque;
5fa45de5
DG
2299}
2300
43864069
MT
2301static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2302{
2303 Range *range = opaque;
2304 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2305 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2306 int i;
43864069
MT
2307
2308 if (!(cmd & PCI_COMMAND_MEMORY)) {
2309 return;
2310 }
2311
2312 if (pc->is_bridge) {
2313 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2314 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2315
2316 base = MAX(base, 0x1ULL << 32);
2317
2318 if (limit >= base) {
2319 Range pref_range;
2320 pref_range.begin = base;
2321 pref_range.end = limit + 1;
2322 range_extend(range, &pref_range);
2323 }
2324 }
77d6f4ea
MT
2325 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2326 PCIIORegion *r = &dev->io_regions[i];
43864069
MT
2327 Range region_range;
2328
77d6f4ea
MT
2329 if (!r->size ||
2330 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2331 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2332 continue;
2333 }
2334 region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2335 region_range.end = region_range.begin + r->size;
2336
2337 if (region_range.begin == PCI_BAR_UNMAPPED) {
43864069
MT
2338 continue;
2339 }
43864069
MT
2340
2341 region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2342
2343 if (region_range.end - 1 >= region_range.begin) {
2344 range_extend(range, &region_range);
2345 }
2346 }
2347}
2348
2349void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2350{
2351 range->begin = range->end = 0;
2352 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2353}
2354
8c43a6f0 2355static const TypeInfo pci_device_type_info = {
40021f08
AL
2356 .name = TYPE_PCI_DEVICE,
2357 .parent = TYPE_DEVICE,
2358 .instance_size = sizeof(PCIDevice),
2359 .abstract = true,
2360 .class_size = sizeof(PCIDeviceClass),
39bffca2 2361 .class_init = pci_device_class_init,
40021f08
AL
2362};
2363
83f7d43a 2364static void pci_register_types(void)
40021f08 2365{
0d936928 2366 type_register_static(&pci_bus_info);
3a861c46 2367 type_register_static(&pcie_bus_info);
40021f08
AL
2368 type_register_static(&pci_device_type_info);
2369}
2370
83f7d43a 2371type_init(pci_register_types)