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Commit | Line | Data |
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69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c759b24f MT |
24 | #include "hw/hw.h" |
25 | #include "hw/pci/pci.h" | |
26 | #include "hw/pci/pci_bridge.h" | |
06aac7bd | 27 | #include "hw/pci/pci_bus.h" |
568f0690 | 28 | #include "hw/pci/pci_host.h" |
83c9089e | 29 | #include "monitor/monitor.h" |
1422e32d | 30 | #include "net/net.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
c759b24f | 32 | #include "hw/loader.h" |
1de7afc9 | 33 | #include "qemu/range.h" |
79627472 | 34 | #include "qmp-commands.h" |
7828d750 | 35 | #include "trace.h" |
c759b24f MT |
36 | #include "hw/pci/msi.h" |
37 | #include "hw/pci/msix.h" | |
022c62cb | 38 | #include "exec/address-spaces.h" |
5e954943 | 39 | #include "hw/hotplug.h" |
69b91039 FB |
40 | |
41 | //#define DEBUG_PCI | |
d8d2e079 | 42 | #ifdef DEBUG_PCI |
2e49d64a | 43 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
44 | #else |
45 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
46 | #endif | |
69b91039 | 47 | |
10c4c98a | 48 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 49 | static char *pcibus_get_dev_path(DeviceState *dev); |
5e0259e7 | 50 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
dcc20931 | 51 | static void pcibus_reset(BusState *qbus); |
10c4c98a | 52 | |
3cb75a7c PB |
53 | static Property pci_props[] = { |
54 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), | |
55 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), | |
56 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), | |
57 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, | |
58 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
59 | DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, | |
60 | QEMU_PCI_CAP_SERR_BITNR, true), | |
61 | DEFINE_PROP_END_OF_LIST() | |
62 | }; | |
63 | ||
d2f69df7 BD |
64 | static const VMStateDescription vmstate_pcibus = { |
65 | .name = "PCIBUS", | |
66 | .version_id = 1, | |
67 | .minimum_version_id = 1, | |
d49805ae | 68 | .fields = (VMStateField[]) { |
d2f69df7 BD |
69 | VMSTATE_INT32_EQUAL(nirq, PCIBus), |
70 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, | |
71 | nirq, 0, vmstate_info_int32, | |
72 | int32_t), | |
73 | VMSTATE_END_OF_LIST() | |
74 | } | |
75 | }; | |
76 | ||
77 | static void pci_bus_realize(BusState *qbus, Error **errp) | |
78 | { | |
79 | PCIBus *bus = PCI_BUS(qbus); | |
80 | ||
81 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); | |
82 | } | |
83 | ||
84 | static void pci_bus_unrealize(BusState *qbus, Error **errp) | |
85 | { | |
86 | PCIBus *bus = PCI_BUS(qbus); | |
87 | ||
88 | vmstate_unregister(NULL, &vmstate_pcibus, bus); | |
89 | } | |
90 | ||
ce6a28ee MA |
91 | static bool pcibus_is_root(PCIBus *bus) |
92 | { | |
93 | return !bus->parent_dev; | |
94 | } | |
95 | ||
602141d9 MA |
96 | static int pcibus_num(PCIBus *bus) |
97 | { | |
98 | if (pcibus_is_root(bus)) { | |
99 | return 0; /* pci host bridge */ | |
100 | } | |
101 | return bus->parent_dev->config[PCI_SECONDARY_BUS]; | |
102 | } | |
103 | ||
6a3042b2 MA |
104 | static uint16_t pcibus_numa_node(PCIBus *bus) |
105 | { | |
106 | return NUMA_NODE_UNASSIGNED; | |
107 | } | |
108 | ||
0d936928 AL |
109 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
110 | { | |
111 | BusClass *k = BUS_CLASS(klass); | |
ce6a28ee | 112 | PCIBusClass *pbc = PCI_BUS_CLASS(klass); |
0d936928 AL |
113 | |
114 | k->print_dev = pcibus_dev_print; | |
115 | k->get_dev_path = pcibus_get_dev_path; | |
116 | k->get_fw_dev_path = pcibus_get_fw_dev_path; | |
d2f69df7 BD |
117 | k->realize = pci_bus_realize; |
118 | k->unrealize = pci_bus_unrealize; | |
0d936928 | 119 | k->reset = pcibus_reset; |
ce6a28ee MA |
120 | |
121 | pbc->is_root = pcibus_is_root; | |
602141d9 | 122 | pbc->bus_num = pcibus_num; |
6a3042b2 | 123 | pbc->numa_node = pcibus_numa_node; |
0d936928 AL |
124 | } |
125 | ||
126 | static const TypeInfo pci_bus_info = { | |
127 | .name = TYPE_PCI_BUS, | |
128 | .parent = TYPE_BUS, | |
129 | .instance_size = sizeof(PCIBus), | |
ce6a28ee | 130 | .class_size = sizeof(PCIBusClass), |
0d936928 | 131 | .class_init = pci_bus_class_init, |
30468f78 | 132 | }; |
69b91039 | 133 | |
3a861c46 AW |
134 | static const TypeInfo pcie_bus_info = { |
135 | .name = TYPE_PCIE_BUS, | |
136 | .parent = TYPE_PCI_BUS, | |
137 | }; | |
138 | ||
d662210a | 139 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
1941d19c | 140 | static void pci_update_mappings(PCIDevice *d); |
d98f08f5 | 141 | static void pci_irq_handler(void *opaque, int irq_num, int level); |
133e9b22 | 142 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); |
230741dc | 143 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 144 | |
d350d97d AL |
145 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
146 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a | 147 | |
7588e2b0 | 148 | static QLIST_HEAD(, PCIHostState) pci_host_bridges; |
30468f78 | 149 | |
cf8c704d | 150 | int pci_bar(PCIDevice *d, int reg) |
5330de09 | 151 | { |
b3b11697 IY |
152 | uint8_t type; |
153 | ||
154 | if (reg != PCI_ROM_SLOT) | |
155 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
156 | ||
157 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
158 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
159 | } |
160 | ||
d036bb21 MT |
161 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
162 | { | |
163 | return (d->irq_state >> irq_num) & 0x1; | |
164 | } | |
165 | ||
166 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
167 | { | |
168 | d->irq_state &= ~(0x1 << irq_num); | |
169 | d->irq_state |= level << irq_num; | |
170 | } | |
171 | ||
172 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
173 | { | |
174 | PCIBus *bus; | |
175 | for (;;) { | |
176 | bus = pci_dev->bus; | |
177 | irq_num = bus->map_irq(pci_dev, irq_num); | |
178 | if (bus->set_irq) | |
179 | break; | |
180 | pci_dev = bus->parent_dev; | |
181 | } | |
182 | bus->irq_count[irq_num] += change; | |
183 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
184 | } | |
185 | ||
9ddf8437 IY |
186 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
187 | { | |
188 | assert(irq_num >= 0); | |
189 | assert(irq_num < bus->nirq); | |
190 | return !!bus->irq_count[irq_num]; | |
191 | } | |
192 | ||
f9bf77dd MT |
193 | /* Update interrupt status bit in config space on interrupt |
194 | * state change. */ | |
195 | static void pci_update_irq_status(PCIDevice *dev) | |
196 | { | |
197 | if (dev->irq_state) { | |
198 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
199 | } else { | |
200 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
201 | } | |
202 | } | |
203 | ||
4c92325b IY |
204 | void pci_device_deassert_intx(PCIDevice *dev) |
205 | { | |
206 | int i; | |
207 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
d98f08f5 | 208 | pci_irq_handler(dev, i, 0); |
4c92325b IY |
209 | } |
210 | } | |
211 | ||
dcc20931 | 212 | static void pci_do_device_reset(PCIDevice *dev) |
5330de09 | 213 | { |
c0b1905b | 214 | int r; |
6fc4925b | 215 | |
4c92325b | 216 | pci_device_deassert_intx(dev); |
58b59014 CR |
217 | assert(dev->irq_state == 0); |
218 | ||
ebabb67a | 219 | /* Clear all writable bits */ |
99443c21 | 220 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
f9aebe2e MT |
221 | pci_get_word(dev->wmask + PCI_COMMAND) | |
222 | pci_get_word(dev->w1cmask + PCI_COMMAND)); | |
89d437df IY |
223 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
224 | pci_get_word(dev->wmask + PCI_STATUS) | | |
225 | pci_get_word(dev->w1cmask + PCI_STATUS)); | |
c0b1905b MT |
226 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
227 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
228 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
229 | PCIIORegion *region = &dev->io_regions[r]; |
230 | if (!region->size) { | |
c0b1905b MT |
231 | continue; |
232 | } | |
71ebd6dc IY |
233 | |
234 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
235 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
236 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
237 | } else { | |
238 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
239 | } | |
c0b1905b MT |
240 | } |
241 | pci_update_mappings(dev); | |
cbd2d434 JK |
242 | |
243 | msi_reset(dev); | |
244 | msix_reset(dev); | |
5330de09 MT |
245 | } |
246 | ||
dcc20931 PB |
247 | /* |
248 | * This function is called on #RST and FLR. | |
249 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set | |
250 | */ | |
251 | void pci_device_reset(PCIDevice *dev) | |
252 | { | |
253 | qdev_reset_all(&dev->qdev); | |
254 | pci_do_device_reset(dev); | |
255 | } | |
256 | ||
9bb33586 IY |
257 | /* |
258 | * Trigger pci bus reset under a given bus. | |
dcc20931 PB |
259 | * Called via qbus_reset_all on RST# assert, after the devices |
260 | * have been reset qdev_reset_all-ed already. | |
9bb33586 | 261 | */ |
dcc20931 | 262 | static void pcibus_reset(BusState *qbus) |
6eaa6847 | 263 | { |
81e3e75b | 264 | PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); |
6eaa6847 GN |
265 | int i; |
266 | ||
5330de09 MT |
267 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
268 | if (bus->devices[i]) { | |
dcc20931 | 269 | pci_do_device_reset(bus->devices[i]); |
5330de09 | 270 | } |
6eaa6847 | 271 | } |
9bb33586 | 272 | |
9bdbbfc3 PB |
273 | for (i = 0; i < bus->nirq; i++) { |
274 | assert(bus->irq_count[i] == 0); | |
275 | } | |
9bb33586 IY |
276 | } |
277 | ||
7588e2b0 | 278 | static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) |
e822a52a | 279 | { |
7588e2b0 DG |
280 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); |
281 | ||
282 | QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); | |
e822a52a IY |
283 | } |
284 | ||
1ef7a2a2 | 285 | PCIBus *pci_find_primary_bus(void) |
e822a52a | 286 | { |
9bc47305 | 287 | PCIBus *primary_bus = NULL; |
7588e2b0 | 288 | PCIHostState *host; |
e822a52a | 289 | |
7588e2b0 | 290 | QLIST_FOREACH(host, &pci_host_bridges, next) { |
9bc47305 DG |
291 | if (primary_bus) { |
292 | /* We have multiple root buses, refuse to select a primary */ | |
293 | return NULL; | |
e822a52a | 294 | } |
9bc47305 | 295 | primary_bus = host->bus; |
e822a52a IY |
296 | } |
297 | ||
9bc47305 | 298 | return primary_bus; |
e822a52a IY |
299 | } |
300 | ||
c473d18d | 301 | PCIBus *pci_device_root_bus(const PCIDevice *d) |
e075e788 | 302 | { |
c473d18d | 303 | PCIBus *bus = d->bus; |
e075e788 | 304 | |
ce6a28ee MA |
305 | while (!pci_bus_is_root(bus)) { |
306 | d = bus->parent_dev; | |
307 | assert(d != NULL); | |
308 | ||
e075e788 IY |
309 | bus = d->bus; |
310 | } | |
311 | ||
c473d18d DG |
312 | return bus; |
313 | } | |
314 | ||
568f0690 | 315 | const char *pci_root_bus_path(PCIDevice *dev) |
c473d18d | 316 | { |
568f0690 DG |
317 | PCIBus *rootbus = pci_device_root_bus(dev); |
318 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); | |
319 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); | |
c473d18d | 320 | |
568f0690 DG |
321 | assert(host_bridge->bus == rootbus); |
322 | ||
323 | if (hc->root_bus_path) { | |
324 | return (*hc->root_bus_path)(host_bridge, rootbus); | |
e075e788 IY |
325 | } |
326 | ||
568f0690 | 327 | return rootbus->qbus.name; |
e075e788 IY |
328 | } |
329 | ||
4fec6404 | 330 | static void pci_bus_init(PCIBus *bus, DeviceState *parent, |
1e39101c | 331 | const char *name, |
aee97b84 AK |
332 | MemoryRegion *address_space_mem, |
333 | MemoryRegion *address_space_io, | |
1e39101c | 334 | uint8_t devfn_min) |
30468f78 | 335 | { |
6fa84913 | 336 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 337 | bus->devfn_min = devfn_min; |
5968eca3 AK |
338 | bus->address_space_mem = address_space_mem; |
339 | bus->address_space_io = address_space_io; | |
e822a52a IY |
340 | |
341 | /* host bridge */ | |
342 | QLIST_INIT(&bus->child); | |
2b8cc89a | 343 | |
7588e2b0 | 344 | pci_host_bus_register(bus, parent); |
21eea4b3 GH |
345 | } |
346 | ||
8c0bf9e2 AW |
347 | bool pci_bus_is_express(PCIBus *bus) |
348 | { | |
349 | return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); | |
350 | } | |
351 | ||
0889464a AW |
352 | bool pci_bus_is_root(PCIBus *bus) |
353 | { | |
ce6a28ee | 354 | return PCI_BUS_GET_CLASS(bus)->is_root(bus); |
0889464a AW |
355 | } |
356 | ||
dd301ca6 | 357 | void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
4fec6404 PB |
358 | const char *name, |
359 | MemoryRegion *address_space_mem, | |
360 | MemoryRegion *address_space_io, | |
60a0e443 | 361 | uint8_t devfn_min, const char *typename) |
4fec6404 | 362 | { |
fb17dfe0 | 363 | qbus_create_inplace(bus, bus_size, typename, parent, name); |
4fec6404 PB |
364 | pci_bus_init(bus, parent, name, address_space_mem, |
365 | address_space_io, devfn_min); | |
366 | } | |
367 | ||
1e39101c | 368 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
aee97b84 AK |
369 | MemoryRegion *address_space_mem, |
370 | MemoryRegion *address_space_io, | |
60a0e443 | 371 | uint8_t devfn_min, const char *typename) |
21eea4b3 GH |
372 | { |
373 | PCIBus *bus; | |
374 | ||
60a0e443 | 375 | bus = PCI_BUS(qbus_create(typename, parent, name)); |
4fec6404 PB |
376 | pci_bus_init(bus, parent, name, address_space_mem, |
377 | address_space_io, devfn_min); | |
21eea4b3 GH |
378 | return bus; |
379 | } | |
380 | ||
381 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
382 | void *irq_opaque, int nirq) | |
383 | { | |
384 | bus->set_irq = set_irq; | |
385 | bus->map_irq = map_irq; | |
386 | bus->irq_opaque = irq_opaque; | |
387 | bus->nirq = nirq; | |
7267c094 | 388 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
21eea4b3 GH |
389 | } |
390 | ||
391 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, | |
392 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 393 | void *irq_opaque, |
aee97b84 AK |
394 | MemoryRegion *address_space_mem, |
395 | MemoryRegion *address_space_io, | |
60a0e443 | 396 | uint8_t devfn_min, int nirq, const char *typename) |
21eea4b3 GH |
397 | { |
398 | PCIBus *bus; | |
399 | ||
aee97b84 | 400 | bus = pci_bus_new(parent, name, address_space_mem, |
60a0e443 | 401 | address_space_io, devfn_min, typename); |
21eea4b3 | 402 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
30468f78 FB |
403 | return bus; |
404 | } | |
69b91039 | 405 | |
502a5395 PB |
406 | int pci_bus_num(PCIBus *s) |
407 | { | |
602141d9 | 408 | return PCI_BUS_GET_CLASS(s)->bus_num(s); |
502a5395 PB |
409 | } |
410 | ||
6a3042b2 MA |
411 | int pci_bus_numa_node(PCIBus *bus) |
412 | { | |
413 | return PCI_BUS_GET_CLASS(bus)->numa_node(bus); | |
502a5395 PB |
414 | } |
415 | ||
73534f2f | 416 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 417 | { |
73534f2f | 418 | PCIDevice *s = container_of(pv, PCIDevice, config); |
e78e9ae4 | 419 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); |
a9f49946 | 420 | uint8_t *config; |
52fc1d83 AZ |
421 | int i; |
422 | ||
a9f49946 | 423 | assert(size == pci_config_size(s)); |
7267c094 | 424 | config = g_malloc(size); |
a9f49946 IY |
425 | |
426 | qemu_get_buffer(f, config, size); | |
427 | for (i = 0; i < size; ++i) { | |
f9aebe2e MT |
428 | if ((config[i] ^ s->config[i]) & |
429 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { | |
7267c094 | 430 | g_free(config); |
bd4b65ee | 431 | return -EINVAL; |
a9f49946 IY |
432 | } |
433 | } | |
434 | memcpy(s->config, config, size); | |
bd4b65ee | 435 | |
1941d19c | 436 | pci_update_mappings(s); |
e78e9ae4 | 437 | if (pc->is_bridge) { |
f055e96b | 438 | PCIBridge *b = PCI_BRIDGE(s); |
e78e9ae4 DK |
439 | pci_bridge_update_mappings(b); |
440 | } | |
52fc1d83 | 441 | |
4ea375bf GH |
442 | memory_region_set_enabled(&s->bus_master_enable_region, |
443 | pci_get_word(s->config + PCI_COMMAND) | |
444 | & PCI_COMMAND_MASTER); | |
445 | ||
7267c094 | 446 | g_free(config); |
30ca2aab FB |
447 | return 0; |
448 | } | |
449 | ||
73534f2f | 450 | /* just put buffer */ |
84e2e3eb | 451 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 452 | { |
dbe73d7f | 453 | const uint8_t **v = pv; |
a9f49946 | 454 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 455 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
456 | } |
457 | ||
458 | static VMStateInfo vmstate_info_pci_config = { | |
459 | .name = "pci config", | |
460 | .get = get_pci_config_device, | |
461 | .put = put_pci_config_device, | |
462 | }; | |
463 | ||
d036bb21 MT |
464 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
465 | { | |
c3f8f611 | 466 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
467 | uint32_t irq_state[PCI_NUM_PINS]; |
468 | int i; | |
469 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
470 | irq_state[i] = qemu_get_be32(f); | |
471 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
472 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
473 | irq_state[i]); | |
474 | return -EINVAL; | |
475 | } | |
476 | } | |
477 | ||
478 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
479 | pci_set_irq_state(s, i, irq_state[i]); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
486 | { | |
487 | int i; | |
c3f8f611 | 488 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
489 | |
490 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
491 | qemu_put_be32(f, pci_irq_state(s, i)); | |
492 | } | |
493 | } | |
494 | ||
495 | static VMStateInfo vmstate_info_pci_irq_state = { | |
496 | .name = "pci irq state", | |
497 | .get = get_pci_irq_state, | |
498 | .put = put_pci_irq_state, | |
499 | }; | |
500 | ||
73534f2f JQ |
501 | const VMStateDescription vmstate_pci_device = { |
502 | .name = "PCIDevice", | |
503 | .version_id = 2, | |
504 | .minimum_version_id = 1, | |
d49805ae | 505 | .fields = (VMStateField[]) { |
3476436a | 506 | VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), |
a9f49946 IY |
507 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
508 | vmstate_info_pci_config, | |
509 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
510 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
511 | vmstate_info_pci_irq_state, | |
512 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
513 | VMSTATE_END_OF_LIST() |
514 | } | |
515 | }; | |
516 | ||
517 | const VMStateDescription vmstate_pcie_device = { | |
1de53459 | 518 | .name = "PCIEDevice", |
a9f49946 IY |
519 | .version_id = 2, |
520 | .minimum_version_id = 1, | |
d49805ae | 521 | .fields = (VMStateField[]) { |
3476436a | 522 | VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), |
a9f49946 IY |
523 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
524 | vmstate_info_pci_config, | |
525 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
526 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
527 | vmstate_info_pci_irq_state, | |
528 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
529 | VMSTATE_END_OF_LIST() |
530 | } | |
531 | }; | |
532 | ||
a9f49946 IY |
533 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
534 | { | |
535 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
536 | } | |
537 | ||
73534f2f JQ |
538 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
539 | { | |
f9bf77dd MT |
540 | /* Clear interrupt status bit: it is implicit |
541 | * in irq_state which we are saving. | |
542 | * This makes us compatible with old devices | |
543 | * which never set or clear this bit. */ | |
544 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
8118f095 | 545 | vmstate_save_state(f, pci_get_vmstate(s), s, NULL); |
f9bf77dd MT |
546 | /* Restore the interrupt status bit. */ |
547 | pci_update_irq_status(s); | |
73534f2f JQ |
548 | } |
549 | ||
550 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
551 | { | |
f9bf77dd MT |
552 | int ret; |
553 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
554 | /* Restore the interrupt status bit. */ | |
555 | pci_update_irq_status(s); | |
556 | return ret; | |
73534f2f JQ |
557 | } |
558 | ||
5e434f4e | 559 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 560 | { |
5e434f4e IY |
561 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
562 | pci_default_sub_vendor_id); | |
563 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
564 | pci_default_sub_device_id); | |
d350d97d AL |
565 | } |
566 | ||
880345c4 | 567 | /* |
43c945f1 IY |
568 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
569 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 570 | */ |
6dbcb819 MA |
571 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
572 | unsigned int *slotp, unsigned int *funcp) | |
880345c4 AL |
573 | { |
574 | const char *p; | |
575 | char *e; | |
576 | unsigned long val; | |
577 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
578 | unsigned int slot = 0; |
579 | unsigned int func = 0; | |
880345c4 AL |
580 | |
581 | p = addr; | |
582 | val = strtoul(p, &e, 16); | |
583 | if (e == p) | |
584 | return -1; | |
585 | if (*e == ':') { | |
586 | bus = val; | |
587 | p = e + 1; | |
588 | val = strtoul(p, &e, 16); | |
589 | if (e == p) | |
590 | return -1; | |
591 | if (*e == ':') { | |
592 | dom = bus; | |
593 | bus = val; | |
594 | p = e + 1; | |
595 | val = strtoul(p, &e, 16); | |
596 | if (e == p) | |
597 | return -1; | |
598 | } | |
599 | } | |
600 | ||
880345c4 AL |
601 | slot = val; |
602 | ||
43c945f1 IY |
603 | if (funcp != NULL) { |
604 | if (*e != '.') | |
605 | return -1; | |
606 | ||
607 | p = e + 1; | |
608 | val = strtoul(p, &e, 16); | |
609 | if (e == p) | |
610 | return -1; | |
611 | ||
612 | func = val; | |
613 | } | |
614 | ||
615 | /* if funcp == NULL func is 0 */ | |
616 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
617 | return -1; | |
618 | ||
880345c4 AL |
619 | if (*e) |
620 | return -1; | |
621 | ||
880345c4 AL |
622 | *domp = dom; |
623 | *busp = bus; | |
624 | *slotp = slot; | |
43c945f1 IY |
625 | if (funcp != NULL) |
626 | *funcp = func; | |
880345c4 AL |
627 | return 0; |
628 | } | |
629 | ||
6dbcb819 MA |
630 | static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, |
631 | const char *devaddr) | |
5607c388 MA |
632 | { |
633 | int dom, bus; | |
634 | unsigned slot; | |
635 | ||
1ef7a2a2 DG |
636 | if (!root) { |
637 | fprintf(stderr, "No primary PCI bus\n"); | |
638 | return NULL; | |
639 | } | |
640 | ||
b645000e S |
641 | assert(!root->parent_dev); |
642 | ||
5607c388 MA |
643 | if (!devaddr) { |
644 | *devfnp = -1; | |
1ef7a2a2 | 645 | return pci_find_bus_nr(root, 0); |
5607c388 MA |
646 | } |
647 | ||
43c945f1 | 648 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
649 | return NULL; |
650 | } | |
651 | ||
1ef7a2a2 DG |
652 | if (dom != 0) { |
653 | fprintf(stderr, "No support for non-zero PCI domains\n"); | |
654 | return NULL; | |
655 | } | |
656 | ||
6ff534b6 | 657 | *devfnp = PCI_DEVFN(slot, 0); |
1ef7a2a2 | 658 | return pci_find_bus_nr(root, bus); |
5607c388 MA |
659 | } |
660 | ||
bd4b65ee MT |
661 | static void pci_init_cmask(PCIDevice *dev) |
662 | { | |
663 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
664 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
665 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
666 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
667 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
668 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
669 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
670 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
671 | } | |
672 | ||
b7ee1603 MT |
673 | static void pci_init_wmask(PCIDevice *dev) |
674 | { | |
a9f49946 IY |
675 | int config_size = pci_config_size(dev); |
676 | ||
b7ee1603 MT |
677 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
678 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 679 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
680 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
681 | PCI_COMMAND_INTX_DISABLE); | |
b1aeb926 IY |
682 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
683 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); | |
684 | } | |
3e21ffc9 IY |
685 | |
686 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
687 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
688 | } |
689 | ||
89d437df IY |
690 | static void pci_init_w1cmask(PCIDevice *dev) |
691 | { | |
692 | /* | |
f6bdfcc9 | 693 | * Note: It's okay to set w1cmask even for readonly bits as |
89d437df IY |
694 | * long as their value is hardwired to 0. |
695 | */ | |
696 | pci_set_word(dev->w1cmask + PCI_STATUS, | |
697 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | | |
698 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | | |
699 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); | |
700 | } | |
701 | ||
d5f27e88 | 702 | static void pci_init_mask_bridge(PCIDevice *d) |
fb231628 IY |
703 | { |
704 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
705 | PCI_SEC_LETENCY_TIMER */ | |
706 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
707 | ||
708 | /* base and limit */ | |
709 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
710 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
711 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
712 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
713 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
714 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
715 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
716 | PCI_PREF_RANGE_MASK & 0xffff); | |
717 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
718 | PCI_PREF_RANGE_MASK & 0xffff); | |
719 | ||
720 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
721 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
722 | ||
d5f27e88 | 723 | /* Supported memory and i/o types */ |
68917102 MT |
724 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
725 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; | |
d5f27e88 MT |
726 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
727 | PCI_PREF_RANGE_TYPE_64); | |
728 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, | |
729 | PCI_PREF_RANGE_TYPE_64); | |
730 | ||
45eb768c MT |
731 | /* |
732 | * TODO: Bridges default to 10-bit VGA decoding but we currently only | |
733 | * implement 16-bit decoding (no alias support). | |
734 | */ | |
f6bdfcc9 MT |
735 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
736 | PCI_BRIDGE_CTL_PARITY | | |
737 | PCI_BRIDGE_CTL_SERR | | |
738 | PCI_BRIDGE_CTL_ISA | | |
739 | PCI_BRIDGE_CTL_VGA | | |
740 | PCI_BRIDGE_CTL_VGA_16BIT | | |
741 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
742 | PCI_BRIDGE_CTL_BUS_RESET | | |
743 | PCI_BRIDGE_CTL_FAST_BACK | | |
744 | PCI_BRIDGE_CTL_DISCARD | | |
745 | PCI_BRIDGE_CTL_SEC_DISCARD | | |
f6bdfcc9 MT |
746 | PCI_BRIDGE_CTL_DISCARD_SERR); |
747 | /* Below does not do anything as we never set this bit, put here for | |
748 | * completeness. */ | |
749 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, | |
750 | PCI_BRIDGE_CTL_DISCARD_STATUS); | |
d5f27e88 | 751 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
15ab7a75 | 752 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
d5f27e88 MT |
753 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
754 | PCI_PREF_RANGE_TYPE_MASK); | |
15ab7a75 MT |
755 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
756 | PCI_PREF_RANGE_TYPE_MASK); | |
fb231628 IY |
757 | } |
758 | ||
133e9b22 | 759 | static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) |
6eab3de1 IY |
760 | { |
761 | uint8_t slot = PCI_SLOT(dev->devfn); | |
762 | uint8_t func; | |
763 | ||
764 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
765 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
766 | } | |
767 | ||
768 | /* | |
b0cd712c | 769 | * multifunction bit is interpreted in two ways as follows. |
6eab3de1 IY |
770 | * - all functions must set the bit to 1. |
771 | * Example: Intel X53 | |
772 | * - function 0 must set the bit, but the rest function (> 0) | |
773 | * is allowed to leave the bit to 0. | |
774 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
775 | * | |
776 | * So OS (at least Linux) checks the bit of only function 0, | |
777 | * and doesn't see the bit of function > 0. | |
778 | * | |
779 | * The below check allows both interpretation. | |
780 | */ | |
781 | if (PCI_FUNC(dev->devfn)) { | |
782 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
783 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
784 | /* function 0 should set multifunction bit */ | |
133e9b22 MA |
785 | error_setg(errp, "PCI: single function device can't be populated " |
786 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
787 | return; | |
6eab3de1 | 788 | } |
133e9b22 | 789 | return; |
6eab3de1 IY |
790 | } |
791 | ||
792 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
133e9b22 | 793 | return; |
6eab3de1 IY |
794 | } |
795 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
796 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
797 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
133e9b22 MA |
798 | error_setg(errp, "PCI: %x.0 indicates single function, " |
799 | "but %x.%x is already populated.", | |
800 | slot, slot, func); | |
801 | return; | |
6eab3de1 IY |
802 | } |
803 | } | |
6eab3de1 IY |
804 | } |
805 | ||
a9f49946 IY |
806 | static void pci_config_alloc(PCIDevice *pci_dev) |
807 | { | |
808 | int config_size = pci_config_size(pci_dev); | |
809 | ||
7267c094 AL |
810 | pci_dev->config = g_malloc0(config_size); |
811 | pci_dev->cmask = g_malloc0(config_size); | |
812 | pci_dev->wmask = g_malloc0(config_size); | |
813 | pci_dev->w1cmask = g_malloc0(config_size); | |
814 | pci_dev->used = g_malloc0(config_size); | |
a9f49946 IY |
815 | } |
816 | ||
817 | static void pci_config_free(PCIDevice *pci_dev) | |
818 | { | |
7267c094 AL |
819 | g_free(pci_dev->config); |
820 | g_free(pci_dev->cmask); | |
821 | g_free(pci_dev->wmask); | |
822 | g_free(pci_dev->w1cmask); | |
823 | g_free(pci_dev->used); | |
a9f49946 IY |
824 | } |
825 | ||
30607764 MA |
826 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
827 | { | |
828 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
829 | pci_config_free(pci_dev); | |
830 | ||
831 | address_space_destroy(&pci_dev->bus_master_as); | |
30607764 MA |
832 | } |
833 | ||
69b91039 | 834 | /* -1 for devfn means auto assign */ |
6b1b92d3 | 835 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
133e9b22 MA |
836 | const char *name, int devfn, |
837 | Error **errp) | |
69b91039 | 838 | { |
40021f08 AL |
839 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
840 | PCIConfigReadFunc *config_read = pc->config_read; | |
841 | PCIConfigWriteFunc *config_write = pc->config_write; | |
133e9b22 | 842 | Error *local_err = NULL; |
e00387d5 | 843 | AddressSpace *dma_as; |
113f89df | 844 | |
69b91039 | 845 | if (devfn < 0) { |
b47b0706 | 846 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 847 | devfn += PCI_FUNC_MAX) { |
30468f78 | 848 | if (!bus->devices[devfn]) |
69b91039 FB |
849 | goto found; |
850 | } | |
133e9b22 MA |
851 | error_setg(errp, "PCI: no slot/function available for %s, all in use", |
852 | name); | |
09e3acc6 | 853 | return NULL; |
69b91039 | 854 | found: ; |
07b7d053 | 855 | } else if (bus->devices[devfn]) { |
133e9b22 MA |
856 | error_setg(errp, "PCI: slot %d function %d not available for %s," |
857 | " in use by %s", | |
858 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, | |
859 | bus->devices[devfn]->name); | |
09e3acc6 | 860 | return NULL; |
69b91039 | 861 | } |
e00387d5 | 862 | |
30468f78 | 863 | pci_dev->bus = bus; |
efc8188e | 864 | pci_dev->devfn = devfn; |
9eda7d37 | 865 | dma_as = pci_device_iommu_address_space(pci_dev); |
24addbc7 | 866 | |
40c5dce9 PB |
867 | memory_region_init_alias(&pci_dev->bus_master_enable_region, |
868 | OBJECT(pci_dev), "bus master", | |
e00387d5 AK |
869 | dma_as->root, 0, memory_region_size(dma_as->root)); |
870 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); | |
7dca8043 AK |
871 | address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, |
872 | name); | |
e00387d5 | 873 | |
69b91039 | 874 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); |
d036bb21 | 875 | pci_dev->irq_state = 0; |
a9f49946 | 876 | pci_config_alloc(pci_dev); |
fb231628 | 877 | |
40021f08 AL |
878 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
879 | pci_config_set_device_id(pci_dev->config, pc->device_id); | |
880 | pci_config_set_revision(pci_dev->config, pc->revision); | |
881 | pci_config_set_class(pci_dev->config, pc->class_id); | |
113f89df | 882 | |
40021f08 AL |
883 | if (!pc->is_bridge) { |
884 | if (pc->subsystem_vendor_id || pc->subsystem_id) { | |
113f89df | 885 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
40021f08 | 886 | pc->subsystem_vendor_id); |
113f89df | 887 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
40021f08 | 888 | pc->subsystem_id); |
113f89df IY |
889 | } else { |
890 | pci_set_default_subsystem_id(pci_dev); | |
891 | } | |
892 | } else { | |
893 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ | |
40021f08 AL |
894 | assert(!pc->subsystem_vendor_id); |
895 | assert(!pc->subsystem_id); | |
fb231628 | 896 | } |
bd4b65ee | 897 | pci_init_cmask(pci_dev); |
b7ee1603 | 898 | pci_init_wmask(pci_dev); |
89d437df | 899 | pci_init_w1cmask(pci_dev); |
40021f08 | 900 | if (pc->is_bridge) { |
d5f27e88 | 901 | pci_init_mask_bridge(pci_dev); |
fb231628 | 902 | } |
133e9b22 MA |
903 | pci_init_multifunction(bus, pci_dev, &local_err); |
904 | if (local_err) { | |
905 | error_propagate(errp, local_err); | |
30607764 | 906 | do_pci_unregister_device(pci_dev); |
6eab3de1 IY |
907 | return NULL; |
908 | } | |
0ac32c83 FB |
909 | |
910 | if (!config_read) | |
911 | config_read = pci_default_read_config; | |
912 | if (!config_write) | |
913 | config_write = pci_default_write_config; | |
69b91039 FB |
914 | pci_dev->config_read = config_read; |
915 | pci_dev->config_write = config_write; | |
30468f78 | 916 | bus->devices[devfn] = pci_dev; |
f16c4abf | 917 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
918 | return pci_dev; |
919 | } | |
920 | ||
5851e08c AL |
921 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
922 | { | |
923 | PCIIORegion *r; | |
924 | int i; | |
925 | ||
926 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
927 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 928 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 929 | continue; |
03952339 | 930 | memory_region_del_subregion(r->address_space, r->memory); |
5851e08c | 931 | } |
e01fd687 AW |
932 | |
933 | pci_unregister_vga(pci_dev); | |
5851e08c AL |
934 | } |
935 | ||
133e9b22 | 936 | static void pci_qdev_unrealize(DeviceState *dev, Error **errp) |
5851e08c | 937 | { |
40021f08 AL |
938 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
939 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); | |
5851e08c AL |
940 | |
941 | pci_unregister_io_regions(pci_dev); | |
230741dc | 942 | pci_del_option_rom(pci_dev); |
7cf1b0fd | 943 | |
f90c2bcd AW |
944 | if (pc->exit) { |
945 | pc->exit(pci_dev); | |
946 | } | |
5851e08c | 947 | |
925fe64a | 948 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
949 | } |
950 | ||
e824b2cc AK |
951 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
952 | uint8_t type, MemoryRegion *memory) | |
69b91039 FB |
953 | { |
954 | PCIIORegion *r; | |
d7ce493a | 955 | uint32_t addr; |
5a9ff381 | 956 | uint64_t wmask; |
cfc0be25 | 957 | pcibus_t size = memory_region_size(memory); |
a4c20c6a | 958 | |
2bbb9c2f IY |
959 | assert(region_num >= 0); |
960 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
961 | if (size & (size-1)) { |
962 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 963 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
964 | exit(1); |
965 | } | |
966 | ||
69b91039 | 967 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 968 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 FB |
969 | r->size = size; |
970 | r->type = type; | |
79ff8cb0 | 971 | r->memory = NULL; |
b7ee1603 MT |
972 | |
973 | wmask = ~(size - 1); | |
b3b11697 | 974 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 975 | if (region_num == PCI_ROM_SLOT) { |
ebabb67a | 976 | /* ROM enable bit is writable */ |
5330de09 | 977 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 978 | } |
b0ff8eb2 | 979 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
980 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
981 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
982 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
983 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
984 | } else { | |
985 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
986 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
987 | } | |
79ff8cb0 | 988 | pci_dev->io_regions[region_num].memory = memory; |
5968eca3 | 989 | pci_dev->io_regions[region_num].address_space |
cfc0be25 | 990 | = type & PCI_BASE_ADDRESS_SPACE_IO |
5968eca3 AK |
991 | ? pci_dev->bus->address_space_io |
992 | : pci_dev->bus->address_space_mem; | |
79ff8cb0 AK |
993 | } |
994 | ||
e01fd687 AW |
995 | static void pci_update_vga(PCIDevice *pci_dev) |
996 | { | |
997 | uint16_t cmd; | |
998 | ||
999 | if (!pci_dev->has_vga) { | |
1000 | return; | |
1001 | } | |
1002 | ||
1003 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
1004 | ||
1005 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], | |
1006 | cmd & PCI_COMMAND_MEMORY); | |
1007 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], | |
1008 | cmd & PCI_COMMAND_IO); | |
1009 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], | |
1010 | cmd & PCI_COMMAND_IO); | |
1011 | } | |
1012 | ||
1013 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, | |
1014 | MemoryRegion *io_lo, MemoryRegion *io_hi) | |
1015 | { | |
1016 | assert(!pci_dev->has_vga); | |
1017 | ||
1018 | assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); | |
1019 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; | |
1020 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, | |
1021 | QEMU_PCI_VGA_MEM_BASE, mem, 1); | |
1022 | ||
1023 | assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); | |
1024 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; | |
1025 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
1026 | QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); | |
1027 | ||
1028 | assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); | |
1029 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; | |
1030 | memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, | |
1031 | QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); | |
1032 | pci_dev->has_vga = true; | |
1033 | ||
1034 | pci_update_vga(pci_dev); | |
1035 | } | |
1036 | ||
1037 | void pci_unregister_vga(PCIDevice *pci_dev) | |
1038 | { | |
1039 | if (!pci_dev->has_vga) { | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | memory_region_del_subregion(pci_dev->bus->address_space_mem, | |
1044 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); | |
1045 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
1046 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); | |
1047 | memory_region_del_subregion(pci_dev->bus->address_space_io, | |
1048 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); | |
1049 | pci_dev->has_vga = false; | |
1050 | } | |
1051 | ||
16a96f28 AK |
1052 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
1053 | { | |
1054 | return pci_dev->io_regions[region_num].addr; | |
1055 | } | |
1056 | ||
876a350d MT |
1057 | static pcibus_t pci_bar_address(PCIDevice *d, |
1058 | int reg, uint8_t type, pcibus_t size) | |
1059 | { | |
1060 | pcibus_t new_addr, last_addr; | |
1061 | int bar = pci_bar(d, reg); | |
1062 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
1063 | ||
1064 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1065 | if (!(cmd & PCI_COMMAND_IO)) { | |
1066 | return PCI_BAR_UNMAPPED; | |
1067 | } | |
1068 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
1069 | last_addr = new_addr + size - 1; | |
9f1a029a HP |
1070 | /* Check if 32 bit BAR wraps around explicitly. |
1071 | * TODO: make priorities correct and remove this work around. | |
1072 | */ | |
1073 | if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { | |
876a350d MT |
1074 | return PCI_BAR_UNMAPPED; |
1075 | } | |
1076 | return new_addr; | |
1077 | } | |
1078 | ||
1079 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
1080 | return PCI_BAR_UNMAPPED; | |
1081 | } | |
1082 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
1083 | new_addr = pci_get_quad(d->config + bar); | |
1084 | } else { | |
1085 | new_addr = pci_get_long(d->config + bar); | |
1086 | } | |
1087 | /* the ROM slot has a specific enable bit */ | |
1088 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
1089 | return PCI_BAR_UNMAPPED; | |
1090 | } | |
1091 | new_addr &= ~(size - 1); | |
1092 | last_addr = new_addr + size - 1; | |
1093 | /* NOTE: we do not support wrapping */ | |
1094 | /* XXX: as we cannot support really dynamic | |
1095 | mappings, we handle specific values as invalid | |
1096 | mappings. */ | |
1097 | if (last_addr <= new_addr || new_addr == 0 || | |
1098 | last_addr == PCI_BAR_UNMAPPED) { | |
1099 | return PCI_BAR_UNMAPPED; | |
1100 | } | |
1101 | ||
1102 | /* Now pcibus_t is 64bit. | |
1103 | * Check if 32 bit BAR wraps around explicitly. | |
1104 | * Without this, PC ide doesn't work well. | |
1105 | * TODO: remove this work around. | |
1106 | */ | |
1107 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
1108 | return PCI_BAR_UNMAPPED; | |
1109 | } | |
1110 | ||
1111 | /* | |
1112 | * OS is allowed to set BAR beyond its addressable | |
1113 | * bits. For example, 32 bit OS can set 64bit bar | |
1114 | * to >4G. Check it. TODO: we might need to support | |
1115 | * it in the future for e.g. PAE. | |
1116 | */ | |
a8170e5e | 1117 | if (last_addr >= HWADDR_MAX) { |
876a350d MT |
1118 | return PCI_BAR_UNMAPPED; |
1119 | } | |
1120 | ||
1121 | return new_addr; | |
1122 | } | |
1123 | ||
0ac32c83 FB |
1124 | static void pci_update_mappings(PCIDevice *d) |
1125 | { | |
1126 | PCIIORegion *r; | |
876a350d | 1127 | int i; |
7df32ca0 | 1128 | pcibus_t new_addr; |
3b46e624 | 1129 | |
8a8696a3 | 1130 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 1131 | r = &d->io_regions[i]; |
a9688570 IY |
1132 | |
1133 | /* this region isn't registered */ | |
ec503442 | 1134 | if (!r->size) |
a9688570 IY |
1135 | continue; |
1136 | ||
876a350d | 1137 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 IY |
1138 | |
1139 | /* This bar isn't changed */ | |
7df32ca0 | 1140 | if (new_addr == r->addr) |
a9688570 IY |
1141 | continue; |
1142 | ||
1143 | /* now do the real mapping */ | |
1144 | if (r->addr != PCI_BAR_UNMAPPED) { | |
7828d750 DK |
1145 | trace_pci_update_mappings_del(d, pci_bus_num(d->bus), |
1146 | PCI_FUNC(d->devfn), | |
1147 | PCI_SLOT(d->devfn), | |
1148 | i, r->addr, r->size); | |
03952339 | 1149 | memory_region_del_subregion(r->address_space, r->memory); |
0ac32c83 | 1150 | } |
a9688570 IY |
1151 | r->addr = new_addr; |
1152 | if (r->addr != PCI_BAR_UNMAPPED) { | |
7828d750 DK |
1153 | trace_pci_update_mappings_add(d, pci_bus_num(d->bus), |
1154 | PCI_FUNC(d->devfn), | |
1155 | PCI_SLOT(d->devfn), | |
1156 | i, r->addr, r->size); | |
8b881e77 AK |
1157 | memory_region_add_subregion_overlap(r->address_space, |
1158 | r->addr, r->memory, 1); | |
a9688570 | 1159 | } |
0ac32c83 | 1160 | } |
e01fd687 AW |
1161 | |
1162 | pci_update_vga(d); | |
0ac32c83 FB |
1163 | } |
1164 | ||
a7b15a5c MT |
1165 | static inline int pci_irq_disabled(PCIDevice *d) |
1166 | { | |
1167 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
1168 | } | |
1169 | ||
1170 | /* Called after interrupt disabled field update in config space, | |
1171 | * assert/deassert interrupts if necessary. | |
1172 | * Gets original interrupt disable bit value (before update). */ | |
1173 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
1174 | { | |
1175 | int i, disabled = pci_irq_disabled(d); | |
1176 | if (disabled == was_irq_disabled) | |
1177 | return; | |
1178 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
1179 | int state = pci_irq_state(d, i); | |
1180 | pci_change_irq_level(d, i, disabled ? -state : state); | |
1181 | } | |
1182 | } | |
1183 | ||
5fafdf24 | 1184 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 1185 | uint32_t address, int len) |
69b91039 | 1186 | { |
5029fe12 | 1187 | uint32_t val = 0; |
42e4126b | 1188 | |
5029fe12 IY |
1189 | memcpy(&val, d->config + address, len); |
1190 | return le32_to_cpu(val); | |
0ac32c83 FB |
1191 | } |
1192 | ||
d7efb7e0 | 1193 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) |
0ac32c83 | 1194 | { |
a7b15a5c | 1195 | int i, was_irq_disabled = pci_irq_disabled(d); |
d7efb7e0 | 1196 | uint32_t val = val_in; |
0ac32c83 | 1197 | |
42e4126b | 1198 | for (i = 0; i < l; val >>= 8, ++i) { |
91011d4f | 1199 | uint8_t wmask = d->wmask[addr + i]; |
92ba5f51 IY |
1200 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1201 | assert(!(wmask & w1cmask)); | |
91011d4f | 1202 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1203 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1204 | } |
260c0cd3 | 1205 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1206 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1207 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1208 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1209 | pci_update_mappings(d); |
a7b15a5c | 1210 | |
1c380f94 | 1211 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
a7b15a5c | 1212 | pci_update_irq_disabled(d, was_irq_disabled); |
1c380f94 AK |
1213 | memory_region_set_enabled(&d->bus_master_enable_region, |
1214 | pci_get_word(d->config + PCI_COMMAND) | |
1215 | & PCI_COMMAND_MASTER); | |
1216 | } | |
95d65800 | 1217 | |
d7efb7e0 KO |
1218 | msi_write_config(d, addr, val_in, l); |
1219 | msix_write_config(d, addr, val_in, l); | |
69b91039 FB |
1220 | } |
1221 | ||
502a5395 PB |
1222 | /***********************************************************/ |
1223 | /* generic PCI irq support */ | |
30468f78 | 1224 | |
502a5395 | 1225 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d98f08f5 | 1226 | static void pci_irq_handler(void *opaque, int irq_num, int level) |
69b91039 | 1227 | { |
a60380a5 | 1228 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1229 | int change; |
3b46e624 | 1230 | |
d036bb21 | 1231 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1232 | if (!change) |
1233 | return; | |
d2b59317 | 1234 | |
d036bb21 | 1235 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1236 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1237 | if (pci_irq_disabled(pci_dev)) |
1238 | return; | |
d036bb21 | 1239 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1240 | } |
1241 | ||
d98f08f5 MA |
1242 | static inline int pci_intx(PCIDevice *pci_dev) |
1243 | { | |
1244 | return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; | |
1245 | } | |
1246 | ||
1247 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev) | |
1248 | { | |
1249 | int intx = pci_intx(pci_dev); | |
1250 | ||
1251 | return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); | |
1252 | } | |
1253 | ||
1254 | void pci_set_irq(PCIDevice *pci_dev, int level) | |
1255 | { | |
1256 | int intx = pci_intx(pci_dev); | |
1257 | pci_irq_handler(pci_dev, intx, level); | |
1258 | } | |
1259 | ||
3afa9bb4 MT |
1260 | /* Special hooks used by device assignment */ |
1261 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) | |
1262 | { | |
0889464a | 1263 | assert(pci_bus_is_root(bus)); |
3afa9bb4 MT |
1264 | bus->route_intx_to_irq = route_intx_to_irq; |
1265 | } | |
1266 | ||
1267 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) | |
1268 | { | |
1269 | PCIBus *bus; | |
1270 | ||
1271 | do { | |
1272 | bus = dev->bus; | |
1273 | pin = bus->map_irq(dev, pin); | |
1274 | dev = bus->parent_dev; | |
1275 | } while (dev); | |
05c0621e AW |
1276 | |
1277 | if (!bus->route_intx_to_irq) { | |
312fd5f2 | 1278 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", |
05c0621e AW |
1279 | object_get_typename(OBJECT(bus->qbus.parent))); |
1280 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; | |
1281 | } | |
1282 | ||
3afa9bb4 | 1283 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
0ae16251 JK |
1284 | } |
1285 | ||
d6e65d54 AW |
1286 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1287 | { | |
1288 | return old->mode != new->mode || old->irq != new->irq; | |
1289 | } | |
1290 | ||
0ae16251 JK |
1291 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1292 | { | |
1293 | PCIDevice *dev; | |
1294 | PCIBus *sec; | |
1295 | int i; | |
1296 | ||
1297 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1298 | dev = bus->devices[i]; | |
1299 | if (dev && dev->intx_routing_notifier) { | |
1300 | dev->intx_routing_notifier(dev); | |
1301 | } | |
e5368f0d AW |
1302 | } |
1303 | ||
1304 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1305 | pci_bus_fire_intx_routing_notifier(sec); | |
0ae16251 JK |
1306 | } |
1307 | } | |
1308 | ||
1309 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, | |
1310 | PCIINTxRoutingNotifier notifier) | |
1311 | { | |
1312 | dev->intx_routing_notifier = notifier; | |
69b91039 FB |
1313 | } |
1314 | ||
91e56159 IY |
1315 | /* |
1316 | * PCI-to-PCI bridge specification | |
1317 | * 9.1: Interrupt routing. Table 9-1 | |
1318 | * | |
1319 | * the PCI Express Base Specification, Revision 2.1 | |
1320 | * 2.2.8.1: INTx interrutp signaling - Rules | |
1321 | * the Implementation Note | |
1322 | * Table 2-20 | |
1323 | */ | |
1324 | /* | |
1325 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD | |
1326 | * 0-origin unlike PCI interrupt pin register. | |
1327 | */ | |
1328 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) | |
1329 | { | |
1330 | return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; | |
1331 | } | |
1332 | ||
502a5395 PB |
1333 | /***********************************************************/ |
1334 | /* monitor info on PCI */ | |
0ac32c83 | 1335 | |
6650ee6d PB |
1336 | typedef struct { |
1337 | uint16_t class; | |
1338 | const char *desc; | |
5e0259e7 GN |
1339 | const char *fw_name; |
1340 | uint16_t fw_ign_bits; | |
6650ee6d PB |
1341 | } pci_class_desc; |
1342 | ||
09bc878a | 1343 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1344 | { |
5e0259e7 GN |
1345 | { 0x0001, "VGA controller", "display"}, |
1346 | { 0x0100, "SCSI controller", "scsi"}, | |
1347 | { 0x0101, "IDE controller", "ide"}, | |
1348 | { 0x0102, "Floppy controller", "fdc"}, | |
1349 | { 0x0103, "IPI controller", "ipi"}, | |
1350 | { 0x0104, "RAID controller", "raid"}, | |
dcb5b19a TS |
1351 | { 0x0106, "SATA controller"}, |
1352 | { 0x0107, "SAS controller"}, | |
1353 | { 0x0180, "Storage controller"}, | |
5e0259e7 GN |
1354 | { 0x0200, "Ethernet controller", "ethernet"}, |
1355 | { 0x0201, "Token Ring controller", "token-ring"}, | |
1356 | { 0x0202, "FDDI controller", "fddi"}, | |
1357 | { 0x0203, "ATM controller", "atm"}, | |
dcb5b19a | 1358 | { 0x0280, "Network controller"}, |
5e0259e7 | 1359 | { 0x0300, "VGA controller", "display", 0x00ff}, |
dcb5b19a TS |
1360 | { 0x0301, "XGA controller"}, |
1361 | { 0x0302, "3D controller"}, | |
1362 | { 0x0380, "Display controller"}, | |
5e0259e7 GN |
1363 | { 0x0400, "Video controller", "video"}, |
1364 | { 0x0401, "Audio controller", "sound"}, | |
dcb5b19a | 1365 | { 0x0402, "Phone"}, |
602ef4d9 | 1366 | { 0x0403, "Audio controller", "sound"}, |
dcb5b19a | 1367 | { 0x0480, "Multimedia controller"}, |
5e0259e7 GN |
1368 | { 0x0500, "RAM controller", "memory"}, |
1369 | { 0x0501, "Flash controller", "flash"}, | |
dcb5b19a | 1370 | { 0x0580, "Memory controller"}, |
5e0259e7 GN |
1371 | { 0x0600, "Host bridge", "host"}, |
1372 | { 0x0601, "ISA bridge", "isa"}, | |
1373 | { 0x0602, "EISA bridge", "eisa"}, | |
1374 | { 0x0603, "MC bridge", "mca"}, | |
4c41425d | 1375 | { 0x0604, "PCI bridge", "pci-bridge"}, |
5e0259e7 GN |
1376 | { 0x0605, "PCMCIA bridge", "pcmcia"}, |
1377 | { 0x0606, "NUBUS bridge", "nubus"}, | |
1378 | { 0x0607, "CARDBUS bridge", "cardbus"}, | |
dcb5b19a TS |
1379 | { 0x0608, "RACEWAY bridge"}, |
1380 | { 0x0680, "Bridge"}, | |
5e0259e7 GN |
1381 | { 0x0700, "Serial port", "serial"}, |
1382 | { 0x0701, "Parallel port", "parallel"}, | |
1383 | { 0x0800, "Interrupt controller", "interrupt-controller"}, | |
1384 | { 0x0801, "DMA controller", "dma-controller"}, | |
1385 | { 0x0802, "Timer", "timer"}, | |
1386 | { 0x0803, "RTC", "rtc"}, | |
1387 | { 0x0900, "Keyboard", "keyboard"}, | |
1388 | { 0x0901, "Pen", "pen"}, | |
1389 | { 0x0902, "Mouse", "mouse"}, | |
1390 | { 0x0A00, "Dock station", "dock", 0x00ff}, | |
1391 | { 0x0B00, "i386 cpu", "cpu", 0x00ff}, | |
1392 | { 0x0c00, "Fireware contorller", "fireware"}, | |
1393 | { 0x0c01, "Access bus controller", "access-bus"}, | |
1394 | { 0x0c02, "SSA controller", "ssa"}, | |
1395 | { 0x0c03, "USB controller", "usb"}, | |
1396 | { 0x0c04, "Fibre channel controller", "fibre-channel"}, | |
f7748569 | 1397 | { 0x0c05, "SMBus"}, |
6650ee6d PB |
1398 | { 0, NULL} |
1399 | }; | |
1400 | ||
163c8a59 | 1401 | static void pci_for_each_device_under_bus(PCIBus *bus, |
7aa8cbb9 AP |
1402 | void (*fn)(PCIBus *b, PCIDevice *d, |
1403 | void *opaque), | |
1404 | void *opaque) | |
30468f78 | 1405 | { |
163c8a59 LC |
1406 | PCIDevice *d; |
1407 | int devfn; | |
30468f78 | 1408 | |
163c8a59 LC |
1409 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1410 | d = bus->devices[devfn]; | |
1411 | if (d) { | |
7aa8cbb9 | 1412 | fn(bus, d, opaque); |
163c8a59 LC |
1413 | } |
1414 | } | |
1415 | } | |
1416 | ||
1417 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
7aa8cbb9 AP |
1418 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1419 | void *opaque) | |
163c8a59 | 1420 | { |
d662210a | 1421 | bus = pci_find_bus_nr(bus, bus_num); |
163c8a59 LC |
1422 | |
1423 | if (bus) { | |
7aa8cbb9 | 1424 | pci_for_each_device_under_bus(bus, fn, opaque); |
163c8a59 LC |
1425 | } |
1426 | } | |
1427 | ||
79627472 | 1428 | static const pci_class_desc *get_class_desc(int class) |
163c8a59 | 1429 | { |
79627472 | 1430 | const pci_class_desc *desc; |
163c8a59 | 1431 | |
79627472 LC |
1432 | desc = pci_class_descriptions; |
1433 | while (desc->desc && class != desc->class) { | |
1434 | desc++; | |
30468f78 | 1435 | } |
b4dccd8d | 1436 | |
79627472 LC |
1437 | return desc; |
1438 | } | |
14421258 | 1439 | |
79627472 | 1440 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
163c8a59 | 1441 | |
79627472 LC |
1442 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1443 | { | |
1444 | PciMemoryRegionList *head = NULL, *cur_item = NULL; | |
1445 | int i; | |
163c8a59 | 1446 | |
79627472 LC |
1447 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1448 | const PCIIORegion *r = &dev->io_regions[i]; | |
1449 | PciMemoryRegionList *region; | |
1450 | ||
1451 | if (!r->size) { | |
1452 | continue; | |
502a5395 | 1453 | } |
163c8a59 | 1454 | |
79627472 LC |
1455 | region = g_malloc0(sizeof(*region)); |
1456 | region->value = g_malloc0(sizeof(*region->value)); | |
163c8a59 | 1457 | |
79627472 LC |
1458 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1459 | region->value->type = g_strdup("io"); | |
1460 | } else { | |
1461 | region->value->type = g_strdup("memory"); | |
1462 | region->value->has_prefetch = true; | |
1463 | region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1464 | region->value->has_mem_type_64 = true; | |
1465 | region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
d5e4acf7 | 1466 | } |
163c8a59 | 1467 | |
79627472 LC |
1468 | region->value->bar = i; |
1469 | region->value->address = r->addr; | |
1470 | region->value->size = r->size; | |
163c8a59 | 1471 | |
79627472 LC |
1472 | /* XXX: waiting for the qapi to support GSList */ |
1473 | if (!cur_item) { | |
1474 | head = cur_item = region; | |
1475 | } else { | |
1476 | cur_item->next = region; | |
1477 | cur_item = region; | |
163c8a59 | 1478 | } |
80b3ada7 | 1479 | } |
384d8876 | 1480 | |
79627472 | 1481 | return head; |
163c8a59 LC |
1482 | } |
1483 | ||
79627472 LC |
1484 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1485 | int bus_num) | |
163c8a59 | 1486 | { |
79627472 | 1487 | PciBridgeInfo *info; |
9fa02cd1 | 1488 | PciMemoryRange *range; |
163c8a59 | 1489 | |
9fa02cd1 | 1490 | info = g_new0(PciBridgeInfo, 1); |
163c8a59 | 1491 | |
9fa02cd1 EB |
1492 | info->bus = g_new0(PciBusInfo, 1); |
1493 | info->bus->number = dev->config[PCI_PRIMARY_BUS]; | |
1494 | info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; | |
1495 | info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; | |
163c8a59 | 1496 | |
9fa02cd1 EB |
1497 | range = info->bus->io_range = g_new0(PciMemoryRange, 1); |
1498 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
1499 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); | |
163c8a59 | 1500 | |
9fa02cd1 EB |
1501 | range = info->bus->memory_range = g_new0(PciMemoryRange, 1); |
1502 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
1503 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
163c8a59 | 1504 | |
9fa02cd1 EB |
1505 | range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); |
1506 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
1507 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
163c8a59 | 1508 | |
79627472 | 1509 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
d662210a | 1510 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
79627472 LC |
1511 | if (child_bus) { |
1512 | info->has_devices = true; | |
1513 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); | |
1514 | } | |
163c8a59 LC |
1515 | } |
1516 | ||
79627472 | 1517 | return info; |
163c8a59 LC |
1518 | } |
1519 | ||
79627472 LC |
1520 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1521 | int bus_num) | |
163c8a59 | 1522 | { |
79627472 LC |
1523 | const pci_class_desc *desc; |
1524 | PciDeviceInfo *info; | |
b5937f29 | 1525 | uint8_t type; |
79627472 | 1526 | int class; |
163c8a59 | 1527 | |
9fa02cd1 | 1528 | info = g_new0(PciDeviceInfo, 1); |
79627472 LC |
1529 | info->bus = bus_num; |
1530 | info->slot = PCI_SLOT(dev->devfn); | |
1531 | info->function = PCI_FUNC(dev->devfn); | |
1532 | ||
9fa02cd1 | 1533 | info->class_info = g_new0(PciDeviceClass, 1); |
79627472 | 1534 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
9fa02cd1 | 1535 | info->class_info->q_class = class; |
79627472 LC |
1536 | desc = get_class_desc(class); |
1537 | if (desc->desc) { | |
9fa02cd1 EB |
1538 | info->class_info->has_desc = true; |
1539 | info->class_info->desc = g_strdup(desc->desc); | |
79627472 LC |
1540 | } |
1541 | ||
9fa02cd1 EB |
1542 | info->id = g_new0(PciDeviceId, 1); |
1543 | info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); | |
1544 | info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); | |
79627472 LC |
1545 | info->regions = qmp_query_pci_regions(dev); |
1546 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); | |
163c8a59 LC |
1547 | |
1548 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
79627472 LC |
1549 | info->has_irq = true; |
1550 | info->irq = dev->config[PCI_INTERRUPT_LINE]; | |
163c8a59 LC |
1551 | } |
1552 | ||
b5937f29 IY |
1553 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1554 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
79627472 LC |
1555 | info->has_pci_bridge = true; |
1556 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); | |
163c8a59 LC |
1557 | } |
1558 | ||
79627472 | 1559 | return info; |
163c8a59 LC |
1560 | } |
1561 | ||
79627472 | 1562 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
384d8876 | 1563 | { |
79627472 | 1564 | PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
163c8a59 | 1565 | PCIDevice *dev; |
79627472 | 1566 | int devfn; |
163c8a59 LC |
1567 | |
1568 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1569 | dev = bus->devices[devfn]; | |
1570 | if (dev) { | |
79627472 LC |
1571 | info = g_malloc0(sizeof(*info)); |
1572 | info->value = qmp_query_pci_device(dev, bus, bus_num); | |
1573 | ||
1574 | /* XXX: waiting for the qapi to support GSList */ | |
1575 | if (!cur_item) { | |
1576 | head = cur_item = info; | |
1577 | } else { | |
1578 | cur_item->next = info; | |
1579 | cur_item = info; | |
1580 | } | |
163c8a59 | 1581 | } |
1074df4f | 1582 | } |
163c8a59 | 1583 | |
79627472 | 1584 | return head; |
1074df4f IY |
1585 | } |
1586 | ||
79627472 | 1587 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1074df4f | 1588 | { |
79627472 LC |
1589 | PciInfo *info = NULL; |
1590 | ||
d662210a | 1591 | bus = pci_find_bus_nr(bus, bus_num); |
502a5395 | 1592 | if (bus) { |
79627472 LC |
1593 | info = g_malloc0(sizeof(*info)); |
1594 | info->bus = bus_num; | |
1595 | info->devices = qmp_query_pci_devices(bus, bus_num); | |
f2aa58c6 | 1596 | } |
163c8a59 | 1597 | |
79627472 | 1598 | return info; |
f2aa58c6 FB |
1599 | } |
1600 | ||
79627472 | 1601 | PciInfoList *qmp_query_pci(Error **errp) |
f2aa58c6 | 1602 | { |
79627472 | 1603 | PciInfoList *info, *head = NULL, *cur_item = NULL; |
7588e2b0 | 1604 | PCIHostState *host_bridge; |
163c8a59 | 1605 | |
7588e2b0 | 1606 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
79627472 | 1607 | info = g_malloc0(sizeof(*info)); |
cb2ed8b3 MA |
1608 | info->value = qmp_query_pci_bus(host_bridge->bus, |
1609 | pci_bus_num(host_bridge->bus)); | |
79627472 LC |
1610 | |
1611 | /* XXX: waiting for the qapi to support GSList */ | |
1612 | if (!cur_item) { | |
1613 | head = cur_item = info; | |
1614 | } else { | |
1615 | cur_item->next = info; | |
1616 | cur_item = info; | |
163c8a59 | 1617 | } |
e822a52a | 1618 | } |
163c8a59 | 1619 | |
79627472 | 1620 | return head; |
77d4bc34 | 1621 | } |
a41b2ff2 | 1622 | |
cb457d76 AL |
1623 | static const char * const pci_nic_models[] = { |
1624 | "ne2k_pci", | |
1625 | "i82551", | |
1626 | "i82557b", | |
1627 | "i82559er", | |
1628 | "rtl8139", | |
1629 | "e1000", | |
1630 | "pcnet", | |
1631 | "virtio", | |
1632 | NULL | |
1633 | }; | |
1634 | ||
9d07d757 PB |
1635 | static const char * const pci_nic_names[] = { |
1636 | "ne2k_pci", | |
1637 | "i82551", | |
1638 | "i82557b", | |
1639 | "i82559er", | |
1640 | "rtl8139", | |
1641 | "e1000", | |
1642 | "pcnet", | |
53c25cea | 1643 | "virtio-net-pci", |
cb457d76 AL |
1644 | NULL |
1645 | }; | |
1646 | ||
a41b2ff2 | 1647 | /* Initialize a PCI NIC. */ |
51f7cb97 | 1648 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
6dbcb819 | 1649 | const char *default_model, |
51f7cb97 | 1650 | const char *default_devaddr) |
a41b2ff2 | 1651 | { |
5607c388 | 1652 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
558ecef2 | 1653 | Error *err = NULL; |
07caea31 | 1654 | PCIBus *bus; |
5607c388 | 1655 | PCIDevice *pci_dev; |
9d07d757 | 1656 | DeviceState *dev; |
51f7cb97 | 1657 | int devfn; |
cb457d76 AL |
1658 | int i; |
1659 | ||
51f7cb97 TH |
1660 | if (qemu_show_nic_models(nd->model, pci_nic_models)) { |
1661 | exit(0); | |
1662 | } | |
1663 | ||
07caea31 | 1664 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
51f7cb97 TH |
1665 | if (i < 0) { |
1666 | exit(1); | |
1667 | } | |
07caea31 | 1668 | |
29b358f9 | 1669 | bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); |
07caea31 | 1670 | if (!bus) { |
1ecda02b MA |
1671 | error_report("Invalid PCI device address %s for device %s", |
1672 | devaddr, pci_nic_names[i]); | |
51f7cb97 | 1673 | exit(1); |
07caea31 MA |
1674 | } |
1675 | ||
499cf102 | 1676 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1677 | dev = &pci_dev->qdev; |
1cc33683 | 1678 | qdev_set_nic_properties(dev, nd); |
558ecef2 MA |
1679 | |
1680 | object_property_set_bool(OBJECT(dev), true, "realized", &err); | |
1681 | if (err) { | |
51f7cb97 | 1682 | error_report_err(err); |
558ecef2 | 1683 | object_unparent(OBJECT(dev)); |
07caea31 | 1684 | exit(1); |
558ecef2 | 1685 | } |
51f7cb97 TH |
1686 | |
1687 | return pci_dev; | |
07caea31 MA |
1688 | } |
1689 | ||
129d42fb AJ |
1690 | PCIDevice *pci_vga_init(PCIBus *bus) |
1691 | { | |
1692 | switch (vga_interface_type) { | |
1693 | case VGA_CIRRUS: | |
1694 | return pci_create_simple(bus, -1, "cirrus-vga"); | |
1695 | case VGA_QXL: | |
1696 | return pci_create_simple(bus, -1, "qxl-vga"); | |
1697 | case VGA_STD: | |
1698 | return pci_create_simple(bus, -1, "VGA"); | |
1699 | case VGA_VMWARE: | |
1700 | return pci_create_simple(bus, -1, "vmware-svga"); | |
a94f0c5c GH |
1701 | case VGA_VIRTIO: |
1702 | return pci_create_simple(bus, -1, "virtio-vga"); | |
129d42fb AJ |
1703 | case VGA_NONE: |
1704 | default: /* Other non-PCI types. Checking for unsupported types is already | |
1705 | done in vl.c. */ | |
1706 | return NULL; | |
1707 | } | |
1708 | } | |
1709 | ||
929176c3 MT |
1710 | /* Whether a given bus number is in range of the secondary |
1711 | * bus of the given bridge device. */ | |
1712 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) | |
1713 | { | |
1714 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & | |
1715 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && | |
09e5b819 | 1716 | dev->config[PCI_SECONDARY_BUS] <= bus_num && |
929176c3 MT |
1717 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; |
1718 | } | |
1719 | ||
09e5b819 MA |
1720 | /* Whether a given bus number is in a range of a root bus */ |
1721 | static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) | |
1722 | { | |
1723 | int i; | |
1724 | ||
1725 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { | |
1726 | PCIDevice *dev = bus->devices[i]; | |
1727 | ||
1728 | if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { | |
1729 | if (pci_secondary_bus_in_range(dev, bus_num)) { | |
1730 | return true; | |
1731 | } | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | return false; | |
1736 | } | |
1737 | ||
d662210a | 1738 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
3ae80618 | 1739 | { |
470e6363 | 1740 | PCIBus *sec; |
3ae80618 | 1741 | |
470e6363 | 1742 | if (!bus) { |
e822a52a | 1743 | return NULL; |
470e6363 | 1744 | } |
3ae80618 | 1745 | |
e822a52a IY |
1746 | if (pci_bus_num(bus) == bus_num) { |
1747 | return bus; | |
1748 | } | |
1749 | ||
929176c3 | 1750 | /* Consider all bus numbers in range for the host pci bridge. */ |
0889464a | 1751 | if (!pci_bus_is_root(bus) && |
929176c3 MT |
1752 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
1753 | return NULL; | |
1754 | } | |
1755 | ||
e822a52a | 1756 | /* try child bus */ |
929176c3 MT |
1757 | for (; bus; bus = sec) { |
1758 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
09e5b819 | 1759 | if (pci_bus_num(sec) == bus_num) { |
929176c3 MT |
1760 | return sec; |
1761 | } | |
09e5b819 MA |
1762 | /* PXB buses assumed to be children of bus 0 */ |
1763 | if (pci_bus_is_root(sec)) { | |
1764 | if (pci_root_bus_in_range(sec, bus_num)) { | |
1765 | break; | |
1766 | } | |
1767 | } else { | |
1768 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { | |
1769 | break; | |
1770 | } | |
c021f8e6 | 1771 | } |
e822a52a IY |
1772 | } |
1773 | } | |
1774 | ||
1775 | return NULL; | |
3ae80618 AL |
1776 | } |
1777 | ||
eb0acfdd MT |
1778 | void pci_for_each_bus_depth_first(PCIBus *bus, |
1779 | void *(*begin)(PCIBus *bus, void *parent_state), | |
1780 | void (*end)(PCIBus *bus, void *state), | |
1781 | void *parent_state) | |
1782 | { | |
1783 | PCIBus *sec; | |
1784 | void *state; | |
1785 | ||
1786 | if (!bus) { | |
1787 | return; | |
1788 | } | |
1789 | ||
1790 | if (begin) { | |
1791 | state = begin(bus, parent_state); | |
1792 | } else { | |
1793 | state = parent_state; | |
1794 | } | |
1795 | ||
1796 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1797 | pci_for_each_bus_depth_first(sec, begin, end, state); | |
1798 | } | |
1799 | ||
1800 | if (end) { | |
1801 | end(bus, state); | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | ||
5256d8bf | 1806 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
3ae80618 | 1807 | { |
d662210a | 1808 | bus = pci_find_bus_nr(bus, bus_num); |
3ae80618 AL |
1809 | |
1810 | if (!bus) | |
1811 | return NULL; | |
1812 | ||
5256d8bf | 1813 | return bus->devices[devfn]; |
3ae80618 AL |
1814 | } |
1815 | ||
133e9b22 | 1816 | static void pci_qdev_realize(DeviceState *qdev, Error **errp) |
6b1b92d3 PB |
1817 | { |
1818 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
40021f08 | 1819 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
133e9b22 | 1820 | Error *local_err = NULL; |
6b1b92d3 | 1821 | PCIBus *bus; |
ab85ceb1 | 1822 | bool is_default_rom; |
6b1b92d3 | 1823 | |
a9f49946 | 1824 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
40021f08 | 1825 | if (pc->is_express) { |
a9f49946 IY |
1826 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1827 | } | |
1828 | ||
fef7fbc9 | 1829 | bus = PCI_BUS(qdev_get_parent_bus(qdev)); |
6e008585 AL |
1830 | pci_dev = do_pci_register_device(pci_dev, bus, |
1831 | object_get_typename(OBJECT(qdev)), | |
133e9b22 | 1832 | pci_dev->devfn, errp); |
09e3acc6 | 1833 | if (pci_dev == NULL) |
133e9b22 | 1834 | return; |
2897ae02 | 1835 | |
7ee6c1e1 MA |
1836 | if (pc->realize) { |
1837 | pc->realize(pci_dev, &local_err); | |
1838 | if (local_err) { | |
1839 | error_propagate(errp, local_err); | |
c2afc922 | 1840 | do_pci_unregister_device(pci_dev); |
133e9b22 | 1841 | return; |
c2afc922 | 1842 | } |
925fe64a | 1843 | } |
8c52c8f3 GH |
1844 | |
1845 | /* rom loading */ | |
ab85ceb1 | 1846 | is_default_rom = false; |
40021f08 AL |
1847 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1848 | pci_dev->romfile = g_strdup(pc->romfile); | |
ab85ceb1 SW |
1849 | is_default_rom = true; |
1850 | } | |
178e785f | 1851 | |
133e9b22 MA |
1852 | pci_add_option_rom(pci_dev, is_default_rom, &local_err); |
1853 | if (local_err) { | |
1854 | error_propagate(errp, local_err); | |
1855 | pci_qdev_unrealize(DEVICE(pci_dev), NULL); | |
1856 | return; | |
178e785f | 1857 | } |
ee995ffb GH |
1858 | } |
1859 | ||
7ee6c1e1 MA |
1860 | static void pci_default_realize(PCIDevice *dev, Error **errp) |
1861 | { | |
1862 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
1863 | ||
1864 | if (pc->init) { | |
1865 | if (pc->init(dev) < 0) { | |
1866 | error_setg(errp, "Device initialization failed"); | |
1867 | return; | |
1868 | } | |
1869 | } | |
1870 | } | |
1871 | ||
49823868 IY |
1872 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1873 | const char *name) | |
6b1b92d3 PB |
1874 | { |
1875 | DeviceState *dev; | |
1876 | ||
02e2da45 | 1877 | dev = qdev_create(&bus->qbus, name); |
09f1bbcd | 1878 | qdev_prop_set_int32(dev, "addr", devfn); |
49823868 | 1879 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
40021f08 | 1880 | return PCI_DEVICE(dev); |
71077c1c | 1881 | } |
6b1b92d3 | 1882 | |
49823868 IY |
1883 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1884 | bool multifunction, | |
1885 | const char *name) | |
71077c1c | 1886 | { |
49823868 | 1887 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1888 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1889 | return dev; |
6b1b92d3 | 1890 | } |
6f4cbd39 | 1891 | |
49823868 IY |
1892 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1893 | { | |
1894 | return pci_create_multifunction(bus, devfn, false, name); | |
1895 | } | |
1896 | ||
1897 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1898 | { | |
1899 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1900 | } | |
1901 | ||
b56d701f | 1902 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
6f4cbd39 MT |
1903 | { |
1904 | int offset = PCI_CONFIG_HEADER_SIZE; | |
1905 | int i; | |
b56d701f | 1906 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
6f4cbd39 MT |
1907 | if (pdev->used[i]) |
1908 | offset = i + 1; | |
1909 | else if (i - offset + 1 == size) | |
1910 | return offset; | |
b56d701f | 1911 | } |
6f4cbd39 MT |
1912 | return 0; |
1913 | } | |
1914 | ||
1915 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1916 | uint8_t *prev_p) | |
1917 | { | |
1918 | uint8_t next, prev; | |
1919 | ||
1920 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1921 | return 0; | |
1922 | ||
1923 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1924 | prev = next + PCI_CAP_LIST_NEXT) | |
1925 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1926 | break; | |
1927 | ||
1928 | if (prev_p) | |
1929 | *prev_p = prev; | |
1930 | return next; | |
1931 | } | |
1932 | ||
c9abe111 JK |
1933 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
1934 | { | |
1935 | uint8_t next, prev, found = 0; | |
1936 | ||
1937 | if (!(pdev->used[offset])) { | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); | |
1942 | ||
1943 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1944 | prev = next + PCI_CAP_LIST_NEXT) { | |
1945 | if (next <= offset && next > found) { | |
1946 | found = next; | |
1947 | } | |
1948 | } | |
1949 | return found; | |
1950 | } | |
1951 | ||
ab85ceb1 SW |
1952 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
1953 | This is needed for an option rom which is used for more than one device. */ | |
1954 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) | |
1955 | { | |
1956 | uint16_t vendor_id; | |
1957 | uint16_t device_id; | |
1958 | uint16_t rom_vendor_id; | |
1959 | uint16_t rom_device_id; | |
1960 | uint16_t rom_magic; | |
1961 | uint16_t pcir_offset; | |
1962 | uint8_t checksum; | |
1963 | ||
1964 | /* Words in rom data are little endian (like in PCI configuration), | |
1965 | so they can be read / written with pci_get_word / pci_set_word. */ | |
1966 | ||
1967 | /* Only a valid rom will be patched. */ | |
1968 | rom_magic = pci_get_word(ptr); | |
1969 | if (rom_magic != 0xaa55) { | |
1970 | PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); | |
1971 | return; | |
1972 | } | |
1973 | pcir_offset = pci_get_word(ptr + 0x18); | |
1974 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { | |
1975 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); | |
1976 | return; | |
1977 | } | |
1978 | ||
1979 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1980 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1981 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); | |
1982 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); | |
1983 | ||
1984 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, | |
1985 | vendor_id, device_id, rom_vendor_id, rom_device_id); | |
1986 | ||
1987 | checksum = ptr[6]; | |
1988 | ||
1989 | if (vendor_id != rom_vendor_id) { | |
1990 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ | |
1991 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); | |
1992 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); | |
1993 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
1994 | ptr[6] = checksum; | |
1995 | pci_set_word(ptr + pcir_offset + 4, vendor_id); | |
1996 | } | |
1997 | ||
1998 | if (device_id != rom_device_id) { | |
1999 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ | |
2000 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); | |
2001 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); | |
2002 | PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); | |
2003 | ptr[6] = checksum; | |
2004 | pci_set_word(ptr + pcir_offset + 6, device_id); | |
2005 | } | |
2006 | } | |
2007 | ||
c2039bd0 | 2008 | /* Add an option rom for the device */ |
133e9b22 MA |
2009 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, |
2010 | Error **errp) | |
c2039bd0 AL |
2011 | { |
2012 | int size; | |
2013 | char *path; | |
2014 | void *ptr; | |
1724f049 | 2015 | char name[32]; |
4be9f0d1 | 2016 | const VMStateDescription *vmsd; |
c2039bd0 | 2017 | |
8c52c8f3 | 2018 | if (!pdev->romfile) |
133e9b22 | 2019 | return; |
8c52c8f3 | 2020 | if (strlen(pdev->romfile) == 0) |
133e9b22 | 2021 | return; |
8c52c8f3 | 2022 | |
88169ddf GH |
2023 | if (!pdev->rom_bar) { |
2024 | /* | |
2025 | * Load rom via fw_cfg instead of creating a rom bar, | |
2026 | * for 0.11 compatibility. | |
2027 | */ | |
2028 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
db80c7b9 MA |
2029 | |
2030 | /* | |
2031 | * Hot-plugged devices can't use the option ROM | |
2032 | * if the rom bar is disabled. | |
2033 | */ | |
2034 | if (DEVICE(pdev)->hotplugged) { | |
133e9b22 MA |
2035 | error_setg(errp, "Hot-plugged device without ROM bar" |
2036 | " can't have an option ROM"); | |
2037 | return; | |
db80c7b9 MA |
2038 | } |
2039 | ||
88169ddf GH |
2040 | if (class == 0x0300) { |
2041 | rom_add_vga(pdev->romfile); | |
2042 | } else { | |
2e55e842 | 2043 | rom_add_option(pdev->romfile, -1); |
88169ddf | 2044 | } |
133e9b22 | 2045 | return; |
88169ddf GH |
2046 | } |
2047 | ||
8c52c8f3 | 2048 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 2049 | if (path == NULL) { |
7267c094 | 2050 | path = g_strdup(pdev->romfile); |
c2039bd0 AL |
2051 | } |
2052 | ||
2053 | size = get_image_size(path); | |
8c52c8f3 | 2054 | if (size < 0) { |
133e9b22 | 2055 | error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); |
8c7f3dd0 | 2056 | g_free(path); |
133e9b22 | 2057 | return; |
8c7f3dd0 | 2058 | } else if (size == 0) { |
133e9b22 | 2059 | error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); |
7267c094 | 2060 | g_free(path); |
133e9b22 | 2061 | return; |
8c52c8f3 | 2062 | } |
c2039bd0 AL |
2063 | if (size & (size - 1)) { |
2064 | size = 1 << qemu_fls(size); | |
2065 | } | |
2066 | ||
4be9f0d1 AL |
2067 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
2068 | ||
2069 | if (vmsd) { | |
2070 | snprintf(name, sizeof(name), "%s.rom", vmsd->name); | |
2071 | } else { | |
f79f2bfc | 2072 | snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
4be9f0d1 | 2073 | } |
14caaf7f | 2074 | pdev->has_rom = true; |
49946538 | 2075 | memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort); |
c5705a77 | 2076 | vmstate_register_ram(&pdev->rom, &pdev->qdev); |
14caaf7f | 2077 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
c2039bd0 | 2078 | load_image(path, ptr); |
7267c094 | 2079 | g_free(path); |
c2039bd0 | 2080 | |
ab85ceb1 SW |
2081 | if (is_default_rom) { |
2082 | /* Only the default rom images will be patched (if needed). */ | |
2083 | pci_patch_ids(pdev, ptr, size); | |
2084 | } | |
2085 | ||
e824b2cc | 2086 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
c2039bd0 AL |
2087 | } |
2088 | ||
230741dc AW |
2089 | static void pci_del_option_rom(PCIDevice *pdev) |
2090 | { | |
14caaf7f | 2091 | if (!pdev->has_rom) |
230741dc AW |
2092 | return; |
2093 | ||
c5705a77 | 2094 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
14caaf7f | 2095 | pdev->has_rom = false; |
230741dc AW |
2096 | } |
2097 | ||
ca77089d IY |
2098 | /* |
2099 | * if !offset | |
2100 | * Reserve space and add capability to the linked list in pci config space | |
2101 | * | |
2102 | * if offset = 0, | |
2103 | * Find and reserve space and add capability to the linked list | |
2104 | * in pci config space */ | |
2105 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
2106 | uint8_t offset, uint8_t size) | |
cd9aa33e LE |
2107 | { |
2108 | int ret; | |
2109 | Error *local_err = NULL; | |
2110 | ||
2111 | ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err); | |
2112 | if (local_err) { | |
2113 | assert(ret < 0); | |
565f65d2 | 2114 | error_report_err(local_err); |
cd9aa33e LE |
2115 | } else { |
2116 | /* success implies a positive offset in config space */ | |
2117 | assert(ret > 0); | |
2118 | } | |
2119 | return ret; | |
2120 | } | |
2121 | ||
2122 | int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, | |
2123 | uint8_t offset, uint8_t size, | |
2124 | Error **errp) | |
6f4cbd39 | 2125 | { |
ca77089d | 2126 | uint8_t *config; |
c9abe111 JK |
2127 | int i, overlapping_cap; |
2128 | ||
ca77089d IY |
2129 | if (!offset) { |
2130 | offset = pci_find_space(pdev, size); | |
2131 | if (!offset) { | |
cd9aa33e | 2132 | error_setg(errp, "out of PCI config space"); |
ca77089d IY |
2133 | return -ENOSPC; |
2134 | } | |
c9abe111 JK |
2135 | } else { |
2136 | /* Verify that capabilities don't overlap. Note: device assignment | |
2137 | * depends on this check to verify that the device is not broken. | |
2138 | * Should never trigger for emulated devices, but it's helpful | |
2139 | * for debugging these. */ | |
2140 | for (i = offset; i < offset + size; i++) { | |
2141 | overlapping_cap = pci_find_capability_at_offset(pdev, i); | |
2142 | if (overlapping_cap) { | |
cd9aa33e LE |
2143 | error_setg(errp, "%s:%02x:%02x.%x " |
2144 | "Attempt to add PCI capability %x at offset " | |
2145 | "%x overlaps existing capability %x at offset %x", | |
2146 | pci_root_bus_path(pdev), pci_bus_num(pdev->bus), | |
2147 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2148 | cap_id, offset, overlapping_cap, i); | |
c9abe111 JK |
2149 | return -EINVAL; |
2150 | } | |
2151 | } | |
ca77089d IY |
2152 | } |
2153 | ||
2154 | config = pdev->config + offset; | |
6f4cbd39 MT |
2155 | config[PCI_CAP_LIST_ID] = cap_id; |
2156 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
2157 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
2158 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
e26631b7 | 2159 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2160 | /* Make capability read-only by default */ |
2161 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
2162 | /* Check capability by default */ |
2163 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
2164 | return offset; |
2165 | } | |
2166 | ||
2167 | /* Unlink capability from the pci config space. */ | |
2168 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
2169 | { | |
2170 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
2171 | if (!offset) | |
2172 | return; | |
2173 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
ebabb67a | 2174 | /* Make capability writable again */ |
6f4cbd39 | 2175 | memset(pdev->wmask + offset, 0xff, size); |
1a4f5971 | 2176 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
2177 | /* Clear cmask as device-specific registers can't be checked */ |
2178 | memset(pdev->cmask + offset, 0, size); | |
e26631b7 | 2179 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
6f4cbd39 MT |
2180 | |
2181 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
2182 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
2183 | } | |
2184 | ||
6f4cbd39 MT |
2185 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2186 | { | |
2187 | return pci_find_capability_list(pdev, cap_id, NULL); | |
2188 | } | |
10c4c98a GH |
2189 | |
2190 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
2191 | { | |
2192 | PCIDevice *d = (PCIDevice *)dev; | |
2193 | const pci_class_desc *desc; | |
2194 | char ctxt[64]; | |
2195 | PCIIORegion *r; | |
2196 | int i, class; | |
2197 | ||
b0ff8eb2 | 2198 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
2199 | desc = pci_class_descriptions; |
2200 | while (desc->desc && class != desc->class) | |
2201 | desc++; | |
2202 | if (desc->desc) { | |
2203 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
2204 | } else { | |
2205 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
2206 | } | |
2207 | ||
2208 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
2209 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
7f5feab4 | 2210 | indent, "", ctxt, pci_bus_num(d->bus), |
e822a52a | 2211 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
b0ff8eb2 IY |
2212 | pci_get_word(d->config + PCI_VENDOR_ID), |
2213 | pci_get_word(d->config + PCI_DEVICE_ID), | |
2214 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
2215 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
2216 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2217 | r = &d->io_regions[i]; | |
2218 | if (!r->size) | |
2219 | continue; | |
89e8b13c IY |
2220 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
2221 | " [0x%"FMT_PCIBUS"]\n", | |
2222 | indent, "", | |
0392a017 | 2223 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
2224 | r->addr, r->addr + r->size - 1); |
2225 | } | |
2226 | } | |
03587182 | 2227 | |
5e0259e7 GN |
2228 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2229 | { | |
2230 | PCIDevice *d = (PCIDevice *)dev; | |
2231 | const char *name = NULL; | |
2232 | const pci_class_desc *desc = pci_class_descriptions; | |
2233 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
2234 | ||
2235 | while (desc->desc && | |
2236 | (class & ~desc->fw_ign_bits) != | |
2237 | (desc->class & ~desc->fw_ign_bits)) { | |
2238 | desc++; | |
2239 | } | |
2240 | ||
2241 | if (desc->desc) { | |
2242 | name = desc->fw_name; | |
2243 | } | |
2244 | ||
2245 | if (name) { | |
2246 | pstrcpy(buf, len, name); | |
2247 | } else { | |
2248 | snprintf(buf, len, "pci%04x,%04x", | |
2249 | pci_get_word(d->config + PCI_VENDOR_ID), | |
2250 | pci_get_word(d->config + PCI_DEVICE_ID)); | |
2251 | } | |
2252 | ||
2253 | return buf; | |
2254 | } | |
2255 | ||
2256 | static char *pcibus_get_fw_dev_path(DeviceState *dev) | |
2257 | { | |
2258 | PCIDevice *d = (PCIDevice *)dev; | |
2259 | char path[50], name[33]; | |
2260 | int off; | |
2261 | ||
2262 | off = snprintf(path, sizeof(path), "%s@%x", | |
2263 | pci_dev_fw_name(dev, name, sizeof name), | |
2264 | PCI_SLOT(d->devfn)); | |
2265 | if (PCI_FUNC(d->devfn)) | |
2266 | snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); | |
a5cf8262 | 2267 | return g_strdup(path); |
5e0259e7 GN |
2268 | } |
2269 | ||
4f43c1ff AW |
2270 | static char *pcibus_get_dev_path(DeviceState *dev) |
2271 | { | |
a6a7005d MT |
2272 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2273 | PCIDevice *t; | |
2274 | int slot_depth; | |
2275 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. | |
2276 | * 00 is added here to make this format compatible with | |
2277 | * domain:Bus:Slot.Func for systems without nested PCI bridges. | |
2278 | * Slot.Function list specifies the slot and function numbers for all | |
2279 | * devices on the path from root to the specific device. */ | |
568f0690 DG |
2280 | const char *root_bus_path; |
2281 | int root_bus_len; | |
2991181a | 2282 | char slot[] = ":SS.F"; |
2991181a | 2283 | int slot_len = sizeof slot - 1 /* For '\0' */; |
a6a7005d MT |
2284 | int path_len; |
2285 | char *path, *p; | |
2991181a | 2286 | int s; |
a6a7005d | 2287 | |
568f0690 DG |
2288 | root_bus_path = pci_root_bus_path(d); |
2289 | root_bus_len = strlen(root_bus_path); | |
2290 | ||
a6a7005d MT |
2291 | /* Calculate # of slots on path between device and root. */; |
2292 | slot_depth = 0; | |
2293 | for (t = d; t; t = t->bus->parent_dev) { | |
2294 | ++slot_depth; | |
2295 | } | |
2296 | ||
568f0690 | 2297 | path_len = root_bus_len + slot_len * slot_depth; |
a6a7005d MT |
2298 | |
2299 | /* Allocate memory, fill in the terminating null byte. */ | |
7267c094 | 2300 | path = g_malloc(path_len + 1 /* For '\0' */); |
a6a7005d MT |
2301 | path[path_len] = '\0'; |
2302 | ||
568f0690 | 2303 | memcpy(path, root_bus_path, root_bus_len); |
a6a7005d MT |
2304 | |
2305 | /* Fill in slot numbers. We walk up from device to root, so need to print | |
2306 | * them in the reverse order, last to first. */ | |
2307 | p = path + path_len; | |
2308 | for (t = d; t; t = t->bus->parent_dev) { | |
2309 | p -= slot_len; | |
2991181a | 2310 | s = snprintf(slot, sizeof slot, ":%02x.%x", |
4c900518 | 2311 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2991181a MT |
2312 | assert(s == slot_len); |
2313 | memcpy(p, slot, slot_len); | |
a6a7005d MT |
2314 | } |
2315 | ||
2316 | return path; | |
4f43c1ff AW |
2317 | } |
2318 | ||
f3006dd1 IY |
2319 | static int pci_qdev_find_recursive(PCIBus *bus, |
2320 | const char *id, PCIDevice **pdev) | |
2321 | { | |
2322 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); | |
2323 | if (!qdev) { | |
2324 | return -ENODEV; | |
2325 | } | |
2326 | ||
2327 | /* roughly check if given qdev is pci device */ | |
4be9f0d1 | 2328 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
40021f08 | 2329 | *pdev = PCI_DEVICE(qdev); |
f3006dd1 IY |
2330 | return 0; |
2331 | } | |
2332 | return -EINVAL; | |
2333 | } | |
2334 | ||
2335 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) | |
2336 | { | |
7588e2b0 | 2337 | PCIHostState *host_bridge; |
f3006dd1 IY |
2338 | int rc = -ENODEV; |
2339 | ||
7588e2b0 DG |
2340 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
2341 | int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); | |
f3006dd1 IY |
2342 | if (!tmp) { |
2343 | rc = 0; | |
2344 | break; | |
2345 | } | |
2346 | if (tmp != -ENODEV) { | |
2347 | rc = tmp; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | return rc; | |
2352 | } | |
f5e6fed8 AK |
2353 | |
2354 | MemoryRegion *pci_address_space(PCIDevice *dev) | |
2355 | { | |
2356 | return dev->bus->address_space_mem; | |
2357 | } | |
e11d6439 RH |
2358 | |
2359 | MemoryRegion *pci_address_space_io(PCIDevice *dev) | |
2360 | { | |
2361 | return dev->bus->address_space_io; | |
2362 | } | |
40021f08 | 2363 | |
39bffca2 AL |
2364 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2365 | { | |
2366 | DeviceClass *k = DEVICE_CLASS(klass); | |
7ee6c1e1 MA |
2367 | PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass); |
2368 | ||
133e9b22 MA |
2369 | k->realize = pci_qdev_realize; |
2370 | k->unrealize = pci_qdev_unrealize; | |
0d936928 | 2371 | k->bus_type = TYPE_PCI_BUS; |
bce54474 | 2372 | k->props = pci_props; |
7ee6c1e1 | 2373 | pc->realize = pci_default_realize; |
39bffca2 AL |
2374 | } |
2375 | ||
9eda7d37 AK |
2376 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) |
2377 | { | |
2378 | PCIBus *bus = PCI_BUS(dev->bus); | |
2379 | ||
2380 | if (bus->iommu_fn) { | |
2381 | return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn); | |
2382 | } | |
2383 | ||
2384 | if (bus->parent_dev) { | |
2385 | /** We are ignoring the bus master DMA bit of the bridge | |
2386 | * as it would complicate things such as VFIO for no good reason */ | |
2387 | return pci_device_iommu_address_space(bus->parent_dev); | |
2388 | } | |
2389 | ||
2390 | return &address_space_memory; | |
2391 | } | |
2392 | ||
e00387d5 | 2393 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
5fa45de5 | 2394 | { |
e00387d5 AK |
2395 | bus->iommu_fn = fn; |
2396 | bus->iommu_opaque = opaque; | |
5fa45de5 DG |
2397 | } |
2398 | ||
43864069 MT |
2399 | static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) |
2400 | { | |
2401 | Range *range = opaque; | |
2402 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); | |
2403 | uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); | |
77d6f4ea | 2404 | int i; |
43864069 MT |
2405 | |
2406 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
2407 | return; | |
2408 | } | |
2409 | ||
2410 | if (pc->is_bridge) { | |
2411 | pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2412 | pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); | |
2413 | ||
2414 | base = MAX(base, 0x1ULL << 32); | |
2415 | ||
2416 | if (limit >= base) { | |
2417 | Range pref_range; | |
2418 | pref_range.begin = base; | |
2419 | pref_range.end = limit + 1; | |
2420 | range_extend(range, &pref_range); | |
2421 | } | |
2422 | } | |
77d6f4ea MT |
2423 | for (i = 0; i < PCI_NUM_REGIONS; ++i) { |
2424 | PCIIORegion *r = &dev->io_regions[i]; | |
43864069 MT |
2425 | Range region_range; |
2426 | ||
77d6f4ea MT |
2427 | if (!r->size || |
2428 | (r->type & PCI_BASE_ADDRESS_SPACE_IO) || | |
2429 | !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { | |
2430 | continue; | |
2431 | } | |
2432 | region_range.begin = pci_bar_address(dev, i, r->type, r->size); | |
2433 | region_range.end = region_range.begin + r->size; | |
2434 | ||
2435 | if (region_range.begin == PCI_BAR_UNMAPPED) { | |
43864069 MT |
2436 | continue; |
2437 | } | |
43864069 MT |
2438 | |
2439 | region_range.begin = MAX(region_range.begin, 0x1ULL << 32); | |
2440 | ||
2441 | if (region_range.end - 1 >= region_range.begin) { | |
2442 | range_extend(range, ®ion_range); | |
2443 | } | |
2444 | } | |
2445 | } | |
2446 | ||
2447 | void pci_bus_get_w64_range(PCIBus *bus, Range *range) | |
2448 | { | |
2449 | range->begin = range->end = 0; | |
2450 | pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); | |
2451 | } | |
2452 | ||
8c43a6f0 | 2453 | static const TypeInfo pci_device_type_info = { |
40021f08 AL |
2454 | .name = TYPE_PCI_DEVICE, |
2455 | .parent = TYPE_DEVICE, | |
2456 | .instance_size = sizeof(PCIDevice), | |
2457 | .abstract = true, | |
2458 | .class_size = sizeof(PCIDeviceClass), | |
39bffca2 | 2459 | .class_init = pci_device_class_init, |
40021f08 AL |
2460 | }; |
2461 | ||
83f7d43a | 2462 | static void pci_register_types(void) |
40021f08 | 2463 | { |
0d936928 | 2464 | type_register_static(&pci_bus_info); |
3a861c46 | 2465 | type_register_static(&pcie_bus_info); |
40021f08 AL |
2466 | type_register_static(&pci_device_type_info); |
2467 | } | |
2468 | ||
83f7d43a | 2469 | type_init(pci_register_types) |