]> git.proxmox.com Git - mirror_qemu.git/blame - hw/pci/pci.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pci: assert configuration access is within bounds
[mirror_qemu.git] / hw / pci / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5fafdf24 5 *
69b91039
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
97d5408f 25#include "qemu/osdep.h"
a8d25326 26#include "qemu-common.h"
64552b6b 27#include "hw/irq.h"
c759b24f
MT		 28#include "hw/pci/pci.h"
29#include "hw/pci/pci_bridge.h"
06aac7bd 30#include "hw/pci/pci_bus.h"
568f0690 31#include "hw/pci/pci_host.h"
a27bd6c7 32#include "hw/qdev-properties.h"
ca77ee28 33#include "migration/qemu-file-types.h"
d6454270 34#include "migration/vmstate.h"
83c9089e 35#include "monitor/monitor.h"
1422e32d 36#include "net/net.h"
b58c5c2d 37#include "sysemu/numa.h"
46517dd4 38#include "sysemu/sysemu.h"
c759b24f 39#include "hw/loader.h"
d49b6836 40#include "qemu/error-report.h"
1de7afc9 41#include "qemu/range.h"
7828d750 42#include "trace.h"
c759b24f
MT		 43#include "hw/pci/msi.h"
44#include "hw/pci/msix.h"
022c62cb 45#include "exec/address-spaces.h"
5e954943 46#include "hw/hotplug.h"
e4024630 47#include "hw/boards.h"
e688df6b 48#include "qapi/error.h"
112ed241 49#include "qapi/qapi-commands-misc.h"
f348b6d1 50#include "qemu/cutils.h"
69b91039
FB		 51
52//#define DEBUG_PCI
d8d2e079 53#ifdef DEBUG_PCI
2e49d64a 54# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
d8d2e079
IY		 55#else
56# define PCI_DPRINTF(format, ...) do { } while (0)
57#endif
69b91039 58
88c725c7
CH		 59bool pci_available = true;
60
10c4c98a 61static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
4f43c1ff 62static char *pcibus_get_dev_path(DeviceState *dev);
5e0259e7 63static char *pcibus_get_fw_dev_path(DeviceState *dev);
dcc20931 64static void pcibus_reset(BusState *qbus);
10c4c98a 65
3cb75a7c
PB		 66static Property pci_props[] = {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
68 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
69 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
70 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
6b449540
MT		 72 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
73 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
f03d8ea3
MA		 74 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
75 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
4f5b6a05
JF		 76 DEFINE_PROP_STRING("failover_pair_id", PCIDevice,
77 failover_pair_id),
3cb75a7c
PB		 78 DEFINE_PROP_END_OF_LIST()
79};
80
d2f69df7
BD		 81static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
d49805ae 85 .fields = (VMStateField[]) {
d2164ad3 86 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
d2f69df7
BD		 87 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
88 nirq, 0, vmstate_info_int32,
89 int32_t),
90 VMSTATE_END_OF_LIST()
91 }
92};
93
b86eacb8
MA		 94static void pci_init_bus_master(PCIDevice *pci_dev)
95{
96 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
97
98 memory_region_init_alias(&pci_dev->bus_master_enable_region,
99 OBJECT(pci_dev), "bus master",
100 dma_as->root, 0, memory_region_size(dma_as->root));
101 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
3716d590
JW		 102 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
103 &pci_dev->bus_master_enable_region);
b86eacb8
MA		 104}
105
106static void pcibus_machine_done(Notifier *notifier, void *data)
107{
108 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
109 int i;
110
111 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
112 if (bus->devices[i]) {
113 pci_init_bus_master(bus->devices[i]);
114 }
115 }
116}
117
d2f69df7
BD		 118static void pci_bus_realize(BusState *qbus, Error **errp)
119{
120 PCIBus *bus = PCI_BUS(qbus);
121
b86eacb8
MA		 122 bus->machine_done.notify = pcibus_machine_done;
123 qemu_add_machine_init_done_notifier(&bus->machine_done);
124
1df2c9a2 125 vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_pcibus, bus);
d2f69df7
BD		 126}
127
2f57db8a
DG		 128static void pcie_bus_realize(BusState *qbus, Error **errp)
129{
130 PCIBus *bus = PCI_BUS(qbus);
131
132 pci_bus_realize(qbus, errp);
133
134 /*
135 * A PCI-E bus can support extended config space if it's the root
136 * bus, or if the bus/bridge above it does as well
137 */
138 if (pci_bus_is_root(bus)) {
139 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
140 } else {
141 PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
142
143 if (pci_bus_allows_extended_config_space(parent_bus)) {
144 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
145 }
146 }
147}
148
b69c3c21 149static void pci_bus_unrealize(BusState *qbus)
d2f69df7
BD		 150{
151 PCIBus *bus = PCI_BUS(qbus);
152
b86eacb8
MA		 153 qemu_remove_machine_init_done_notifier(&bus->machine_done);
154
d2f69df7
BD		 155 vmstate_unregister(NULL, &vmstate_pcibus, bus);
156}
157
602141d9
MA		 158static int pcibus_num(PCIBus *bus)
159{
b0e5196a 160 if (pci_bus_is_root(bus)) {
602141d9
MA		 161 return 0; /* pci host bridge */
162 }
163 return bus->parent_dev->config[PCI_SECONDARY_BUS];
164}
165
6a3042b2
MA		 166static uint16_t pcibus_numa_node(PCIBus *bus)
167{
168 return NUMA_NODE_UNASSIGNED;
169}
170
0d936928
AL		 171static void pci_bus_class_init(ObjectClass *klass, void *data)
172{
173 BusClass *k = BUS_CLASS(klass);
ce6a28ee 174 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
0d936928
AL		 175
176 k->print_dev = pcibus_dev_print;
177 k->get_dev_path = pcibus_get_dev_path;
178 k->get_fw_dev_path = pcibus_get_fw_dev_path;
d2f69df7
BD		 179 k->realize = pci_bus_realize;
180 k->unrealize = pci_bus_unrealize;
0d936928 181 k->reset = pcibus_reset;
ce6a28ee 182
602141d9 183 pbc->bus_num = pcibus_num;
6a3042b2 184 pbc->numa_node = pcibus_numa_node;
0d936928
AL		 185}
186
187static const TypeInfo pci_bus_info = {
188 .name = TYPE_PCI_BUS,
189 .parent = TYPE_BUS,
190 .instance_size = sizeof(PCIBus),
ce6a28ee 191 .class_size = sizeof(PCIBusClass),
0d936928 192 .class_init = pci_bus_class_init,
30468f78 193};
69b91039 194
619f02ae
EH		 195static const TypeInfo pcie_interface_info = {
196 .name = INTERFACE_PCIE_DEVICE,
197 .parent = TYPE_INTERFACE,
198};
199
200static const TypeInfo conventional_pci_interface_info = {
201 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
202 .parent = TYPE_INTERFACE,
203};
204
1c685a90
GK		 205static void pcie_bus_class_init(ObjectClass *klass, void *data)
206{
2f57db8a 207 BusClass *k = BUS_CLASS(klass);
1c685a90 208
2f57db8a 209 k->realize = pcie_bus_realize;
1c685a90
GK		 210}
211
3a861c46
AW		 212static const TypeInfo pcie_bus_info = {
213 .name = TYPE_PCIE_BUS,
214 .parent = TYPE_PCI_BUS,
1c685a90 215 .class_init = pcie_bus_class_init,
3a861c46
AW		 216};
217
d662210a 218static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
1941d19c 219static void pci_update_mappings(PCIDevice *d);
d98f08f5 220static void pci_irq_handler(void *opaque, int irq_num, int level);
133e9b22 221static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
230741dc 222static void pci_del_option_rom(PCIDevice *pdev);
1941d19c 223
d350d97d
AL		 224static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
225static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
e822a52a 226
7588e2b0 227static QLIST_HEAD(, PCIHostState) pci_host_bridges;
30468f78 228
cf8c704d 229int pci_bar(PCIDevice *d, int reg)
5330de09 230{
b3b11697
IY		 231 uint8_t type;
232
233 if (reg != PCI_ROM_SLOT)
234 return PCI_BASE_ADDRESS_0 + reg * 4;
235
236 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
237 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
5330de09
MT		 238}
239
d036bb21
MT		 240static inline int pci_irq_state(PCIDevice *d, int irq_num)
241{
7d37435b 242 return (d->irq_state >> irq_num) & 0x1;
d036bb21
MT		 243}
244
245static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
246{
7d37435b
PB		 247 d->irq_state &= ~(0x1 << irq_num);
248 d->irq_state |= level << irq_num;
d036bb21
MT		 249}
250
251static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
252{
253 PCIBus *bus;
254 for (;;) {
fd56e061 255 bus = pci_get_bus(pci_dev);
d036bb21
MT		 256 irq_num = bus->map_irq(pci_dev, irq_num);
257 if (bus->set_irq)
258 break;
259 pci_dev = bus->parent_dev;
260 }
261 bus->irq_count[irq_num] += change;
262 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
263}
264
9ddf8437
IY		 265int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
266{
267 assert(irq_num >= 0);
268 assert(irq_num < bus->nirq);
269 return !!bus->irq_count[irq_num];
270}
271
f9bf77dd
MT		 272/* Update interrupt status bit in config space on interrupt
273 * state change. */
274static void pci_update_irq_status(PCIDevice *dev)
275{
276 if (dev->irq_state) {
277 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
278 } else {
279 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
280 }
281}
282
4c92325b
IY		 283void pci_device_deassert_intx(PCIDevice *dev)
284{
285 int i;
286 for (i = 0; i < PCI_NUM_PINS; ++i) {
d98f08f5 287 pci_irq_handler(dev, i, 0);
4c92325b
IY		 288 }
289}
290
dcc20931 291static void pci_do_device_reset(PCIDevice *dev)
5330de09 292{
c0b1905b 293 int r;
6fc4925b 294
4c92325b 295 pci_device_deassert_intx(dev);
58b59014
CR		 296 assert(dev->irq_state == 0);
297
ebabb67a 298 /* Clear all writable bits */
99443c21 299 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
f9aebe2e
MT		 300 pci_get_word(dev->wmask + PCI_COMMAND) |
301 pci_get_word(dev->w1cmask + PCI_COMMAND));
89d437df
IY		 302 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
303 pci_get_word(dev->wmask + PCI_STATUS) |
304 pci_get_word(dev->w1cmask + PCI_STATUS));
7ff81d63
BZ		 305 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
306 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE,
307 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) |
308 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE));
c0b1905b 309 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
c0b1905b 310 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
71ebd6dc
IY		 311 PCIIORegion *region = &dev->io_regions[r];
312 if (!region->size) {
c0b1905b
MT		 313 continue;
314 }
71ebd6dc
IY		 315
316 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
317 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
318 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
319 } else {
320 pci_set_long(dev->config + pci_bar(dev, r), region->type);
321 }
c0b1905b
MT		 322 }
323 pci_update_mappings(dev);
cbd2d434
JK		 324
325 msi_reset(dev);
326 msix_reset(dev);
5330de09
MT		 327}
328
dcc20931
PB		 329/*
330 * This function is called on #RST and FLR.
331 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
332 */
333void pci_device_reset(PCIDevice *dev)
334{
335 qdev_reset_all(&dev->qdev);
336 pci_do_device_reset(dev);
337}
338
9bb33586
IY		 339/*
340 * Trigger pci bus reset under a given bus.
dcc20931
PB		 341 * Called via qbus_reset_all on RST# assert, after the devices
342 * have been reset qdev_reset_all-ed already.
9bb33586 343 */
dcc20931 344static void pcibus_reset(BusState *qbus)
6eaa6847 345{
81e3e75b 346 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
6eaa6847
GN		 347 int i;
348
5330de09
MT		 349 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
350 if (bus->devices[i]) {
dcc20931 351 pci_do_device_reset(bus->devices[i]);
5330de09 352 }
6eaa6847 353 }
9bb33586 354
9bdbbfc3
PB		 355 for (i = 0; i < bus->nirq; i++) {
356 assert(bus->irq_count[i] == 0);
357 }
9bb33586
IY		 358}
359
3dbc01ae 360static void pci_host_bus_register(DeviceState *host)
e822a52a 361{
3dbc01ae 362 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
7588e2b0
DG		 363
364 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
e822a52a
IY		 365}
366
c13ee169
MR		 367static void pci_host_bus_unregister(DeviceState *host)
368{
369 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
370
371 QLIST_REMOVE(host_bridge, next);
372}
373
c473d18d 374PCIBus *pci_device_root_bus(const PCIDevice *d)
e075e788 375{
fd56e061 376 PCIBus *bus = pci_get_bus(d);
e075e788 377
ce6a28ee
MA		 378 while (!pci_bus_is_root(bus)) {
379 d = bus->parent_dev;
380 assert(d != NULL);
381
fd56e061 382 bus = pci_get_bus(d);
e075e788
IY		 383 }
384
c473d18d
DG		 385 return bus;
386}
387
568f0690 388const char *pci_root_bus_path(PCIDevice *dev)
c473d18d 389{
568f0690
DG		 390 PCIBus *rootbus = pci_device_root_bus(dev);
391 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
392 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
c473d18d 393
568f0690
DG		 394 assert(host_bridge->bus == rootbus);
395
396 if (hc->root_bus_path) {
397 return (*hc->root_bus_path)(host_bridge, rootbus);
e075e788
IY		 398 }
399
568f0690 400 return rootbus->qbus.name;
e075e788
IY		 401}
402
1115ff6d
DG		 403static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min)
30468f78 407{
6fa84913 408 assert(PCI_FUNC(devfn_min) == 0);
502a5395 409 bus->devfn_min = devfn_min;
8b884984 410 bus->slot_reserved_mask = 0x0;
5968eca3
AK		 411 bus->address_space_mem = address_space_mem;
412 bus->address_space_io = address_space_io;
b0e5196a 413 bus->flags |= PCI_BUS_IS_ROOT;
e822a52a
IY		 414
415 /* host bridge */
416 QLIST_INIT(&bus->child);
2b8cc89a 417
3dbc01ae 418 pci_host_bus_register(parent);
21eea4b3
GH		 419}
420
c13ee169
MR		 421static void pci_bus_uninit(PCIBus *bus)
422{
423 pci_host_bus_unregister(BUS(bus)->parent);
424}
425
8c0bf9e2
AW		 426bool pci_bus_is_express(PCIBus *bus)
427{
428 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
429}
430
1115ff6d
DG		 431void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
432 const char *name,
433 MemoryRegion *address_space_mem,
434 MemoryRegion *address_space_io,
435 uint8_t devfn_min, const char *typename)
4fec6404 436{
fb17dfe0 437 qbus_create_inplace(bus, bus_size, typename, parent, name);
1115ff6d
DG		 438 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
439 devfn_min);
4fec6404
PB		 440}
441
1115ff6d
DG		 442PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
443 MemoryRegion *address_space_mem,
444 MemoryRegion *address_space_io,
445 uint8_t devfn_min, const char *typename)
21eea4b3
GH		 446{
447 PCIBus *bus;
448
60a0e443 449 bus = PCI_BUS(qbus_create(typename, parent, name));
1115ff6d
DG		 450 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
451 devfn_min);
21eea4b3
GH		 452 return bus;
453}
454
c13ee169
MR		 455void pci_root_bus_cleanup(PCIBus *bus)
456{
457 pci_bus_uninit(bus);
07578b0a 458 /* the caller of the unplug hotplug handler will delete this device */
b69c3c21 459 object_property_set_bool(OBJECT(bus), false, "realized", &error_abort);
c13ee169
MR		 460}
461
21eea4b3
GH		 462void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
463 void *irq_opaque, int nirq)
464{
465 bus->set_irq = set_irq;
466 bus->map_irq = map_irq;
467 bus->irq_opaque = irq_opaque;
468 bus->nirq = nirq;
7267c094 469 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
21eea4b3
GH		 470}
471
c13ee169
MR		 472void pci_bus_irqs_cleanup(PCIBus *bus)
473{
474 bus->set_irq = NULL;
475 bus->map_irq = NULL;
476 bus->irq_opaque = NULL;
477 bus->nirq = 0;
478 g_free(bus->irq_count);
479}
480
1115ff6d
DG		 481PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
482 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
483 void *irq_opaque,
484 MemoryRegion *address_space_mem,
485 MemoryRegion *address_space_io,
486 uint8_t devfn_min, int nirq,
487 const char *typename)
21eea4b3
GH		 488{
489 PCIBus *bus;
490
1115ff6d
DG		 491 bus = pci_root_bus_new(parent, name, address_space_mem,
492 address_space_io, devfn_min, typename);
21eea4b3 493 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
30468f78
FB		 494 return bus;
495}
69b91039 496
c13ee169
MR		 497void pci_unregister_root_bus(PCIBus *bus)
498{
499 pci_bus_irqs_cleanup(bus);
500 pci_root_bus_cleanup(bus);
501}
502
502a5395
PB		 503int pci_bus_num(PCIBus *s)
504{
602141d9 505 return PCI_BUS_GET_CLASS(s)->bus_num(s);
502a5395
PB		 506}
507
6a3042b2
MA		 508int pci_bus_numa_node(PCIBus *bus)
509{
510 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
502a5395
PB		 511}
512
2c21ee76 513static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
03fee66f 514 const VMStateField *field)
30ca2aab 515{
73534f2f 516 PCIDevice *s = container_of(pv, PCIDevice, config);
e78e9ae4 517 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
a9f49946 518 uint8_t *config;
52fc1d83
AZ		 519 int i;
520
a9f49946 521 assert(size == pci_config_size(s));
7267c094 522 config = g_malloc(size);
a9f49946
IY		 523
524 qemu_get_buffer(f, config, size);
525 for (i = 0; i < size; ++i) {
f9aebe2e
MT		 526 if ((config[i] ^ s->config[i]) &
527 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
7c59364d
DDAG		 528 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
529 "cmask: %x wmask: %x w1cmask:%x", __func__,
530 i, config[i], s->config[i],
531 s->cmask[i], s->wmask[i], s->w1cmask[i]);
7267c094 532 g_free(config);
bd4b65ee 533 return -EINVAL;
a9f49946
IY		 534 }
535 }
536 memcpy(s->config, config, size);
bd4b65ee 537
1941d19c 538 pci_update_mappings(s);
e78e9ae4 539 if (pc->is_bridge) {
f055e96b 540 PCIBridge *b = PCI_BRIDGE(s);
e78e9ae4
DK		 541 pci_bridge_update_mappings(b);
542 }
52fc1d83 543
4ea375bf
GH		 544 memory_region_set_enabled(&s->bus_master_enable_region,
545 pci_get_word(s->config + PCI_COMMAND)
546 & PCI_COMMAND_MASTER);
547
7267c094 548 g_free(config);
30ca2aab
FB		 549 return 0;
550}
551
73534f2f 552/* just put buffer */
2c21ee76 553static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
03fee66f 554 const VMStateField *field, QJSON *vmdesc)
73534f2f 555{
dbe73d7f 556 const uint8_t **v = pv;
a9f49946 557 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
dbe73d7f 558 qemu_put_buffer(f, *v, size);
2c21ee76
JD		 559
560 return 0;
73534f2f
JQ		 561}
562
563static VMStateInfo vmstate_info_pci_config = {
564 .name = "pci config",
565 .get = get_pci_config_device,
566 .put = put_pci_config_device,
567};
568
2c21ee76 569static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
03fee66f 570 const VMStateField *field)
d036bb21 571{
c3f8f611 572 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 573 uint32_t irq_state[PCI_NUM_PINS];
574 int i;
575 for (i = 0; i < PCI_NUM_PINS; ++i) {
576 irq_state[i] = qemu_get_be32(f);
577 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
578 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
579 irq_state[i]);
580 return -EINVAL;
581 }
582 }
583
584 for (i = 0; i < PCI_NUM_PINS; ++i) {
585 pci_set_irq_state(s, i, irq_state[i]);
586 }
587
588 return 0;
589}
590
2c21ee76 591static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
03fee66f 592 const VMStateField *field, QJSON *vmdesc)
d036bb21
MT		 593{
594 int i;
c3f8f611 595 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
d036bb21
MT		 596
597 for (i = 0; i < PCI_NUM_PINS; ++i) {
598 qemu_put_be32(f, pci_irq_state(s, i));
599 }
2c21ee76
JD		 600
601 return 0;
d036bb21
MT		 602}
603
604static VMStateInfo vmstate_info_pci_irq_state = {
605 .name = "pci irq state",
606 .get = get_pci_irq_state,
607 .put = put_pci_irq_state,
608};
609
20daa90a
DDAG		 610static bool migrate_is_pcie(void *opaque, int version_id)
611{
612 return pci_is_express((PCIDevice *)opaque);
613}
614
615static bool migrate_is_not_pcie(void *opaque, int version_id)
616{
617 return !pci_is_express((PCIDevice *)opaque);
618}
619
73534f2f
JQ		 620const VMStateDescription vmstate_pci_device = {
621 .name = "PCIDevice",
622 .version_id = 2,
623 .minimum_version_id = 1,
d49805ae 624 .fields = (VMStateField[]) {
3476436a 625 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
20daa90a
DDAG		 626 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
627 migrate_is_not_pcie,
628 0, vmstate_info_pci_config,
a9f49946 629 PCI_CONFIG_SPACE_SIZE),
20daa90a
DDAG		 630 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
631 migrate_is_pcie,
632 0, vmstate_info_pci_config,
a9f49946 633 PCIE_CONFIG_SPACE_SIZE),
d036bb21 634 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
7d37435b
PB		 635 vmstate_info_pci_irq_state,
636 PCI_NUM_PINS * sizeof(int32_t)),
73534f2f
JQ		 637 VMSTATE_END_OF_LIST()
638 }
639};
640
a9f49946 641
73534f2f
JQ		 642void pci_device_save(PCIDevice *s, QEMUFile *f)
643{
f9bf77dd
MT		 644 /* Clear interrupt status bit: it is implicit
645 * in irq_state which we are saving.
646 * This makes us compatible with old devices
647 * which never set or clear this bit. */
648 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
20daa90a 649 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
f9bf77dd
MT		 650 /* Restore the interrupt status bit. */
651 pci_update_irq_status(s);
73534f2f
JQ		 652}
653
654int pci_device_load(PCIDevice *s, QEMUFile *f)
655{
f9bf77dd 656 int ret;
20daa90a 657 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
f9bf77dd
MT		 658 /* Restore the interrupt status bit. */
659 pci_update_irq_status(s);
660 return ret;
73534f2f
JQ		 661}
662
5e434f4e 663static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
d350d97d 664{
5e434f4e
IY		 665 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
666 pci_default_sub_vendor_id);
667 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
668 pci_default_sub_device_id);
d350d97d
AL		 669}
670
880345c4 671/*
43c945f1
IY		 672 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
673 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
880345c4 674 */
6dbcb819
MA		 675static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
676 unsigned int *slotp, unsigned int *funcp)
880345c4
AL		 677{
678 const char *p;
679 char *e;
680 unsigned long val;
681 unsigned long dom = 0, bus = 0;
43c945f1
IY		 682 unsigned int slot = 0;
683 unsigned int func = 0;
880345c4
AL		 684
685 p = addr;
686 val = strtoul(p, &e, 16);
687 if (e == p)
7d37435b 688 return -1;
880345c4 689 if (*e == ':') {
7d37435b
PB		 690 bus = val;
691 p = e + 1;
692 val = strtoul(p, &e, 16);
693 if (e == p)
694 return -1;
695 if (*e == ':') {
696 dom = bus;
697 bus = val;
698 p = e + 1;
699 val = strtoul(p, &e, 16);
700 if (e == p)
701 return -1;
702 }
880345c4
AL		 703 }
704
880345c4
AL		 705 slot = val;
706
43c945f1
IY		 707 if (funcp != NULL) {
708 if (*e != '.')
709 return -1;
710
711 p = e + 1;
712 val = strtoul(p, &e, 16);
713 if (e == p)
714 return -1;
715
716 func = val;
717 }
718
719 /* if funcp == NULL func is 0 */
720 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
7d37435b 721 return -1;
43c945f1 722
880345c4 723 if (*e)
7d37435b 724 return -1;
880345c4 725
880345c4
AL		 726 *domp = dom;
727 *busp = bus;
728 *slotp = slot;
43c945f1
IY		 729 if (funcp != NULL)
730 *funcp = func;
880345c4
AL		 731 return 0;
732}
733
bd4b65ee
MT		 734static void pci_init_cmask(PCIDevice *dev)
735{
736 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
737 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
738 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
739 dev->cmask[PCI_REVISION_ID] = 0xff;
740 dev->cmask[PCI_CLASS_PROG] = 0xff;
741 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
742 dev->cmask[PCI_HEADER_TYPE] = 0xff;
743 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
744}
745
b7ee1603
MT		 746static void pci_init_wmask(PCIDevice *dev)
747{
a9f49946
IY		 748 int config_size = pci_config_size(dev);
749
b7ee1603
MT		 750 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
751 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
67a51b48 752 pci_set_word(dev->wmask + PCI_COMMAND,
a7b15a5c
MT		 753 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
754 PCI_COMMAND_INTX_DISABLE);
2a4dbaf1 755 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
3e21ffc9
IY		 756
757 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
758 config_size - PCI_CONFIG_HEADER_SIZE);
b7ee1603
MT		 759}
760
89d437df
IY		 761static void pci_init_w1cmask(PCIDevice *dev)
762{
763 /*
f6bdfcc9 764 * Note: It's okay to set w1cmask even for readonly bits as
89d437df
IY		 765 * long as their value is hardwired to 0.
766 */
767 pci_set_word(dev->w1cmask + PCI_STATUS,
768 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
769 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
770 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
771}
772
d5f27e88 773static void pci_init_mask_bridge(PCIDevice *d)
fb231628
IY		 774{
775 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
776 PCI_SEC_LETENCY_TIMER */
777 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
778
779 /* base and limit */
780 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
781 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
782 pci_set_word(d->wmask + PCI_MEMORY_BASE,
783 PCI_MEMORY_RANGE_MASK & 0xffff);
784 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
785 PCI_MEMORY_RANGE_MASK & 0xffff);
786 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
787 PCI_PREF_RANGE_MASK & 0xffff);
788 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
789 PCI_PREF_RANGE_MASK & 0xffff);
790
791 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
792 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
793
d5f27e88 794 /* Supported memory and i/o types */
68917102
MT		 795 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
796 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
d5f27e88
MT		 797 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
798 PCI_PREF_RANGE_TYPE_64);
799 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
800 PCI_PREF_RANGE_TYPE_64);
801
45eb768c
MT		 802 /*
803 * TODO: Bridges default to 10-bit VGA decoding but we currently only
804 * implement 16-bit decoding (no alias support).
805 */
f6bdfcc9
MT		 806 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
807 PCI_BRIDGE_CTL_PARITY |
808 PCI_BRIDGE_CTL_SERR |
809 PCI_BRIDGE_CTL_ISA |
810 PCI_BRIDGE_CTL_VGA |
811 PCI_BRIDGE_CTL_VGA_16BIT |
812 PCI_BRIDGE_CTL_MASTER_ABORT |
813 PCI_BRIDGE_CTL_BUS_RESET |
814 PCI_BRIDGE_CTL_FAST_BACK |
815 PCI_BRIDGE_CTL_DISCARD |
816 PCI_BRIDGE_CTL_SEC_DISCARD |
f6bdfcc9
MT		 817 PCI_BRIDGE_CTL_DISCARD_SERR);
818 /* Below does not do anything as we never set this bit, put here for
819 * completeness. */
820 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
821 PCI_BRIDGE_CTL_DISCARD_STATUS);
d5f27e88 822 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
15ab7a75 823 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
d5f27e88
MT		 824 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
825 PCI_PREF_RANGE_TYPE_MASK);
15ab7a75
MT		 826 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
827 PCI_PREF_RANGE_TYPE_MASK);
fb231628
IY		 828}
829
133e9b22 830static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
6eab3de1
IY		 831{
832 uint8_t slot = PCI_SLOT(dev->devfn);
833 uint8_t func;
834
835 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
836 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
837 }
838
839 /*
b0cd712c 840 * multifunction bit is interpreted in two ways as follows.
6eab3de1
IY		 841 * - all functions must set the bit to 1.
842 * Example: Intel X53
843 * - function 0 must set the bit, but the rest function (> 0)
844 * is allowed to leave the bit to 0.
845 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
846 *
847 * So OS (at least Linux) checks the bit of only function 0,
848 * and doesn't see the bit of function > 0.
849 *
850 * The below check allows both interpretation.
851 */
852 if (PCI_FUNC(dev->devfn)) {
853 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
854 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
855 /* function 0 should set multifunction bit */
133e9b22
MA		 856 error_setg(errp, "PCI: single function device can't be populated "
857 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
858 return;
6eab3de1 859 }
133e9b22 860 return;
6eab3de1
IY		 861 }
862
863 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
133e9b22 864 return;
6eab3de1
IY		 865 }
866 /* function 0 indicates single function, so function > 0 must be NULL */
867 for (func = 1; func < PCI_FUNC_MAX; ++func) {
868 if (bus->devices[PCI_DEVFN(slot, func)]) {
133e9b22
MA		 869 error_setg(errp, "PCI: %x.0 indicates single function, "
870 "but %x.%x is already populated.",
871 slot, slot, func);
872 return;
6eab3de1
IY		 873 }
874 }
6eab3de1
IY		 875}
876
a9f49946
IY		 877static void pci_config_alloc(PCIDevice *pci_dev)
878{
879 int config_size = pci_config_size(pci_dev);
880
7267c094
AL		 881 pci_dev->config = g_malloc0(config_size);
882 pci_dev->cmask = g_malloc0(config_size);
883 pci_dev->wmask = g_malloc0(config_size);
884 pci_dev->w1cmask = g_malloc0(config_size);
885 pci_dev->used = g_malloc0(config_size);
a9f49946
IY		 886}
887
888static void pci_config_free(PCIDevice *pci_dev)
889{
7267c094
AL		 890 g_free(pci_dev->config);
891 g_free(pci_dev->cmask);
892 g_free(pci_dev->wmask);
893 g_free(pci_dev->w1cmask);
894 g_free(pci_dev->used);
a9f49946
IY		 895}
896
30607764
MA		 897static void do_pci_unregister_device(PCIDevice *pci_dev)
898{
fd56e061 899 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
30607764
MA		 900 pci_config_free(pci_dev);
901
193982c6
AK		 902 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
903 memory_region_del_subregion(&pci_dev->bus_master_container_region,
904 &pci_dev->bus_master_enable_region);
905 }
30607764 906 address_space_destroy(&pci_dev->bus_master_as);
30607764
MA		 907}
908
4a94b3aa
PX		 909/* Extract PCIReqIDCache into BDF format */
910static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
911{
912 uint8_t bus_n;
913 uint16_t result;
914
915 switch (cache->type) {
916 case PCI_REQ_ID_BDF:
917 result = pci_get_bdf(cache->dev);
918 break;
919 case PCI_REQ_ID_SECONDARY_BUS:
fd56e061 920 bus_n = pci_dev_bus_num(cache->dev);
4a94b3aa
PX		 921 result = PCI_BUILD_BDF(bus_n, 0);
922 break;
923 default:
eaf27fab 924 error_report("Invalid PCI requester ID cache type: %d",
4a94b3aa
PX		 925 cache->type);
926 exit(1);
927 break;
928 }
929
930 return result;
931}
932
933/* Parse bridges up to the root complex and return requester ID
934 * cache for specific device. For full PCIe topology, the cache
935 * result would be exactly the same as getting BDF of the device.
936 * However, several tricks are required when system mixed up with
937 * legacy PCI devices and PCIe-to-PCI bridges.
938 *
939 * Here we cache the proxy device (and type) not requester ID since
940 * bus number might change from time to time.
941 */
942static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
943{
944 PCIDevice *parent;
945 PCIReqIDCache cache = {
946 .dev = dev,
947 .type = PCI_REQ_ID_BDF,
948 };
949
fd56e061 950 while (!pci_bus_is_root(pci_get_bus(dev))) {
4a94b3aa 951 /* We are under PCI/PCIe bridges */
fd56e061 952 parent = pci_get_bus(dev)->parent_dev;
4a94b3aa
PX		 953 if (pci_is_express(parent)) {
954 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
955 /* When we pass through PCIe-to-PCI/PCIX bridges, we
956 * override the requester ID using secondary bus
957 * number of parent bridge with zeroed devfn
958 * (pcie-to-pci bridge spec chap 2.3). */
959 cache.type = PCI_REQ_ID_SECONDARY_BUS;
960 cache.dev = dev;
961 }
962 } else {
963 /* Legacy PCI, override requester ID with the bridge's
964 * BDF upstream. When the root complex connects to
965 * legacy PCI devices (including buses), it can only
966 * obtain requester ID info from directly attached
967 * devices. If devices are attached under bridges, only
968 * the requester ID of the bridge that is directly
969 * attached to the root complex can be recognized. */
970 cache.type = PCI_REQ_ID_BDF;
971 cache.dev = parent;
972 }
973 dev = parent;
974 }
975
976 return cache;
977}
978
979uint16_t pci_requester_id(PCIDevice *dev)
980{
981 return pci_req_id_cache_extract(&dev->requester_id_cache);
982}
983
9b717a3a
MCA		 984static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
985{
986 return !(bus->devices[devfn]);
987}
988
8b884984
MCA		 989static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
990{
991 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
992}
993
69b91039 994/* -1 for devfn means auto assign */
fd56e061 995static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
133e9b22
MA		 996 const char *name, int devfn,
997 Error **errp)
69b91039 998{
40021f08
AL		 999 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1000 PCIConfigReadFunc *config_read = pc->config_read;
1001 PCIConfigWriteFunc *config_write = pc->config_write;
133e9b22 1002 Error *local_err = NULL;
3f1e1478 1003 DeviceState *dev = DEVICE(pci_dev);
fd56e061 1004 PCIBus *bus = pci_get_bus(pci_dev);
3f1e1478 1005
0144f6f1
MA		 1006 /* Only pci bridges can be attached to extra PCI root buses */
1007 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
1008 error_setg(errp,
1009 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1010 bus->parent_dev->name);
1011 return NULL;
1012 }
113f89df 1013
69b91039 1014 if (devfn < 0) {
b47b0706 1015 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
6fa84913 1016 devfn += PCI_FUNC_MAX) {
8b884984
MCA		 1017 if (pci_bus_devfn_available(bus, devfn) &&
1018 !pci_bus_devfn_reserved(bus, devfn)) {
69b91039 1019 goto found;
9b717a3a 1020 }
69b91039 1021 }
8b884984
MCA		 1022 error_setg(errp, "PCI: no slot/function available for %s, all in use "
1023 "or reserved", name);
09e3acc6 1024 return NULL;
69b91039 1025 found: ;
8b884984
MCA		 1026 } else if (pci_bus_devfn_reserved(bus, devfn)) {
1027 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1028 " reserved",
1029 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1030 return NULL;
9b717a3a 1031 } else if (!pci_bus_devfn_available(bus, devfn)) {
133e9b22
MA		 1032 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1033 " in use by %s",
1034 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1035 bus->devices[devfn]->name);
09e3acc6 1036 return NULL;
3f1e1478
C		 1037 } else if (dev->hotplugged &&
1038 pci_get_function_0(pci_dev)) {
1039 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1040 " new func %s cannot be exposed to guest.",
d93ddfb1
MT		 1041 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1042 pci_get_function_0(pci_dev)->name,
3f1e1478
C		 1043 name);
1044
1045 return NULL;
69b91039 1046 }
e00387d5 1047
efc8188e 1048 pci_dev->devfn = devfn;
4a94b3aa 1049 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
d06bce95 1050 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
e00387d5 1051
3716d590
JW		 1052 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1053 "bus master container", UINT64_MAX);
1054 address_space_init(&pci_dev->bus_master_as,
1055 &pci_dev->bus_master_container_region, pci_dev->name);
1056
b86eacb8
MA		 1057 if (qdev_hotplug) {
1058 pci_init_bus_master(pci_dev);
1059 }
d036bb21 1060 pci_dev->irq_state = 0;
a9f49946 1061 pci_config_alloc(pci_dev);
fb231628 1062
40021f08
AL		 1063 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1064 pci_config_set_device_id(pci_dev->config, pc->device_id);
1065 pci_config_set_revision(pci_dev->config, pc->revision);
1066 pci_config_set_class(pci_dev->config, pc->class_id);
113f89df 1067
40021f08
AL		 1068 if (!pc->is_bridge) {
1069 if (pc->subsystem_vendor_id || pc->subsystem_id) {
113f89df 1070 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
40021f08 1071 pc->subsystem_vendor_id);
113f89df 1072 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
40021f08 1073 pc->subsystem_id);
113f89df
IY		 1074 } else {
1075 pci_set_default_subsystem_id(pci_dev);
1076 }
1077 } else {
1078 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
40021f08
AL		 1079 assert(!pc->subsystem_vendor_id);
1080 assert(!pc->subsystem_id);
fb231628 1081 }
bd4b65ee 1082 pci_init_cmask(pci_dev);
b7ee1603 1083 pci_init_wmask(pci_dev);
89d437df 1084 pci_init_w1cmask(pci_dev);
40021f08 1085 if (pc->is_bridge) {
d5f27e88 1086 pci_init_mask_bridge(pci_dev);
fb231628 1087 }
133e9b22
MA		 1088 pci_init_multifunction(bus, pci_dev, &local_err);
1089 if (local_err) {
1090 error_propagate(errp, local_err);
30607764 1091 do_pci_unregister_device(pci_dev);
6eab3de1
IY		 1092 return NULL;
1093 }
0ac32c83
FB		 1094
1095 if (!config_read)
1096 config_read = pci_default_read_config;
1097 if (!config_write)
1098 config_write = pci_default_write_config;
69b91039
FB		 1099 pci_dev->config_read = config_read;
1100 pci_dev->config_write = config_write;
30468f78 1101 bus->devices[devfn] = pci_dev;
f16c4abf 1102 pci_dev->version_id = 2; /* Current pci device vmstate version */
69b91039
FB		 1103 return pci_dev;
1104}
1105
5851e08c
AL		 1106static void pci_unregister_io_regions(PCIDevice *pci_dev)
1107{
1108 PCIIORegion *r;
1109 int i;
1110
1111 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1112 r = &pci_dev->io_regions[i];
182f9c8a 1113 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
5851e08c 1114 continue;
03952339 1115 memory_region_del_subregion(r->address_space, r->memory);
5851e08c 1116 }
e01fd687
AW		 1117
1118 pci_unregister_vga(pci_dev);
5851e08c
AL		 1119}
1120
b69c3c21 1121static void pci_qdev_unrealize(DeviceState *dev)
5851e08c 1122{
40021f08
AL		 1123 PCIDevice *pci_dev = PCI_DEVICE(dev);
1124 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
5851e08c
AL		 1125
1126 pci_unregister_io_regions(pci_dev);
230741dc 1127 pci_del_option_rom(pci_dev);
7cf1b0fd 1128
f90c2bcd
AW		 1129 if (pc->exit) {
1130 pc->exit(pci_dev);
1131 }
5851e08c 1132
3936161f 1133 pci_device_deassert_intx(pci_dev);
925fe64a 1134 do_pci_unregister_device(pci_dev);
5851e08c
AL		 1135}
1136
e824b2cc
AK		 1137void pci_register_bar(PCIDevice *pci_dev, int region_num,
1138 uint8_t type, MemoryRegion *memory)
69b91039
FB		 1139{
1140 PCIIORegion *r;
5178ecd8 1141 uint32_t addr; /* offset in pci config space */
5a9ff381 1142 uint64_t wmask;
cfc0be25 1143 pcibus_t size = memory_region_size(memory);
a4c20c6a 1144
2bbb9c2f
IY		 1145 assert(region_num >= 0);
1146 assert(region_num < PCI_NUM_REGIONS);
a4c20c6a 1147 if (size & (size-1)) {
0151abe4
AF		 1148 error_report("ERROR: PCI region size must be pow2 "
1149 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
a4c20c6a
AL		 1150 exit(1);
1151 }
1152
69b91039 1153 r = &pci_dev->io_regions[region_num];
182f9c8a 1154 r->addr = PCI_BAR_UNMAPPED;
69b91039
FB		 1155 r->size = size;
1156 r->type = type;
5178ecd8
C		 1157 r->memory = memory;
1158 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
fd56e061
DG		 1159 ? pci_get_bus(pci_dev)->address_space_io
1160 : pci_get_bus(pci_dev)->address_space_mem;
b7ee1603
MT		 1161
1162 wmask = ~(size - 1);
d7ce493a 1163 if (region_num == PCI_ROM_SLOT) {
ebabb67a 1164 /* ROM enable bit is writable */
5330de09 1165 wmask |= PCI_ROM_ADDRESS_ENABLE;
d7ce493a 1166 }
5178ecd8
C		 1167
1168 addr = pci_bar(pci_dev, region_num);
b0ff8eb2 1169 pci_set_long(pci_dev->config + addr, type);
5178ecd8 1170
14421258
IY		 1171 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1172 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1173 pci_set_quad(pci_dev->wmask + addr, wmask);
1174 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1175 } else {
1176 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1177 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1178 }
79ff8cb0
AK		 1179}
1180
e01fd687
AW		 1181static void pci_update_vga(PCIDevice *pci_dev)
1182{
1183 uint16_t cmd;
1184
1185 if (!pci_dev->has_vga) {
1186 return;
1187 }
1188
1189 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1190
1191 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1192 cmd & PCI_COMMAND_MEMORY);
1193 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1194 cmd & PCI_COMMAND_IO);
1195 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1196 cmd & PCI_COMMAND_IO);
1197}
1198
1199void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1200 MemoryRegion *io_lo, MemoryRegion *io_hi)
1201{
fd56e061
DG		 1202 PCIBus *bus = pci_get_bus(pci_dev);
1203
e01fd687
AW		 1204 assert(!pci_dev->has_vga);
1205
1206 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1207 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
fd56e061 1208 memory_region_add_subregion_overlap(bus->address_space_mem,
e01fd687
AW		 1209 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1210
1211 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1212 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
fd56e061 1213 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1214 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1215
1216 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1217 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
fd56e061 1218 memory_region_add_subregion_overlap(bus->address_space_io,
e01fd687
AW		 1219 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1220 pci_dev->has_vga = true;
1221
1222 pci_update_vga(pci_dev);
1223}
1224
1225void pci_unregister_vga(PCIDevice *pci_dev)
1226{
fd56e061
DG		 1227 PCIBus *bus = pci_get_bus(pci_dev);
1228
e01fd687
AW		 1229 if (!pci_dev->has_vga) {
1230 return;
1231 }
1232
fd56e061 1233 memory_region_del_subregion(bus->address_space_mem,
e01fd687 1234 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
fd56e061 1235 memory_region_del_subregion(bus->address_space_io,
e01fd687 1236 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
fd56e061 1237 memory_region_del_subregion(bus->address_space_io,
e01fd687
AW		 1238 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1239 pci_dev->has_vga = false;
1240}
1241
16a96f28
AK		 1242pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1243{
1244 return pci_dev->io_regions[region_num].addr;
1245}
1246
876a350d 1247static pcibus_t pci_bar_address(PCIDevice *d,
7d37435b 1248 int reg, uint8_t type, pcibus_t size)
876a350d
MT		 1249{
1250 pcibus_t new_addr, last_addr;
1251 int bar = pci_bar(d, reg);
1252 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
e4024630
LV		 1253 Object *machine = qdev_get_machine();
1254 ObjectClass *oc = object_get_class(machine);
1255 MachineClass *mc = MACHINE_CLASS(oc);
1256 bool allow_0_address = mc->pci_allow_0_address;
876a350d
MT		 1257
1258 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1259 if (!(cmd & PCI_COMMAND_IO)) {
1260 return PCI_BAR_UNMAPPED;
1261 }
1262 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1263 last_addr = new_addr + size - 1;
9f1a029a
HP		 1264 /* Check if 32 bit BAR wraps around explicitly.
1265 * TODO: make priorities correct and remove this work around.
1266 */
e4024630
LV		 1267 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1268 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1269 return PCI_BAR_UNMAPPED;
1270 }
1271 return new_addr;
1272 }
1273
1274 if (!(cmd & PCI_COMMAND_MEMORY)) {
1275 return PCI_BAR_UNMAPPED;
1276 }
1277 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1278 new_addr = pci_get_quad(d->config + bar);
1279 } else {
1280 new_addr = pci_get_long(d->config + bar);
1281 }
1282 /* the ROM slot has a specific enable bit */
1283 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1284 return PCI_BAR_UNMAPPED;
1285 }
1286 new_addr &= ~(size - 1);
1287 last_addr = new_addr + size - 1;
1288 /* NOTE: we do not support wrapping */
1289 /* XXX: as we cannot support really dynamic
1290 mappings, we handle specific values as invalid
1291 mappings. */
e4024630
LV		 1292 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1293 (!allow_0_address && new_addr == 0)) {
876a350d
MT		 1294 return PCI_BAR_UNMAPPED;
1295 }
1296
1297 /* Now pcibus_t is 64bit.
1298 * Check if 32 bit BAR wraps around explicitly.
1299 * Without this, PC ide doesn't work well.
1300 * TODO: remove this work around.
1301 */
1302 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1303 return PCI_BAR_UNMAPPED;
1304 }
1305
1306 /*
1307 * OS is allowed to set BAR beyond its addressable
1308 * bits. For example, 32 bit OS can set 64bit bar
1309 * to >4G. Check it. TODO: we might need to support
1310 * it in the future for e.g. PAE.
1311 */
a8170e5e 1312 if (last_addr >= HWADDR_MAX) {
876a350d
MT		 1313 return PCI_BAR_UNMAPPED;
1314 }
1315
1316 return new_addr;
1317}
1318
0ac32c83
FB		 1319static void pci_update_mappings(PCIDevice *d)
1320{
1321 PCIIORegion *r;
876a350d 1322 int i;
7df32ca0 1323 pcibus_t new_addr;
3b46e624 1324
8a8696a3 1325 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 1326 r = &d->io_regions[i];
a9688570
IY		 1327
1328 /* this region isn't registered */
ec503442 1329 if (!r->size)
a9688570
IY		 1330 continue;
1331
876a350d 1332 new_addr = pci_bar_address(d, i, r->type, r->size);
a9688570
IY		 1333
1334 /* This bar isn't changed */
7df32ca0 1335 if (new_addr == r->addr)
a9688570
IY		 1336 continue;
1337
1338 /* now do the real mapping */
1339 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1340 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
7828d750 1341 PCI_SLOT(d->devfn),
0f288f85 1342 PCI_FUNC(d->devfn),
7828d750 1343 i, r->addr, r->size);
03952339 1344 memory_region_del_subregion(r->address_space, r->memory);
0ac32c83 1345 }
a9688570
IY		 1346 r->addr = new_addr;
1347 if (r->addr != PCI_BAR_UNMAPPED) {
fd56e061 1348 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
7828d750 1349 PCI_SLOT(d->devfn),
0f288f85 1350 PCI_FUNC(d->devfn),
7828d750 1351 i, r->addr, r->size);
8b881e77
AK		 1352 memory_region_add_subregion_overlap(r->address_space,
1353 r->addr, r->memory, 1);
a9688570 1354 }
0ac32c83 1355 }
e01fd687
AW		 1356
1357 pci_update_vga(d);
0ac32c83
FB		 1358}
1359
a7b15a5c
MT		 1360static inline int pci_irq_disabled(PCIDevice *d)
1361{
1362 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1363}
1364
1365/* Called after interrupt disabled field update in config space,
1366 * assert/deassert interrupts if necessary.
1367 * Gets original interrupt disable bit value (before update). */
1368static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1369{
1370 int i, disabled = pci_irq_disabled(d);
1371 if (disabled == was_irq_disabled)
1372 return;
1373 for (i = 0; i < PCI_NUM_PINS; ++i) {
1374 int state = pci_irq_state(d, i);
1375 pci_change_irq_level(d, i, disabled ? -state : state);
1376 }
1377}
1378
5fafdf24 1379uint32_t pci_default_read_config(PCIDevice *d,
0ac32c83 1380 uint32_t address, int len)
69b91039 1381{
5029fe12 1382 uint32_t val = 0;
42e4126b 1383
f7d6a635
PP		 1384 assert(address + len <= pci_config_size(d));
1385
727b4866
AW		 1386 if (pci_is_express_downstream_port(d) &&
1387 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) {
1388 pcie_sync_bridge_lnk(d);
1389 }
5029fe12
IY		 1390 memcpy(&val, d->config + address, len);
1391 return le32_to_cpu(val);
0ac32c83
FB		 1392}
1393
d7efb7e0 1394void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
0ac32c83 1395{
a7b15a5c 1396 int i, was_irq_disabled = pci_irq_disabled(d);
d7efb7e0 1397 uint32_t val = val_in;
0ac32c83 1398
f7d6a635
PP		 1399 assert(addr + l <= pci_config_size(d));
1400
42e4126b 1401 for (i = 0; i < l; val >>= 8, ++i) {
91011d4f 1402 uint8_t wmask = d->wmask[addr + i];
92ba5f51
IY		 1403 uint8_t w1cmask = d->w1cmask[addr + i];
1404 assert(!(wmask & w1cmask));
91011d4f 1405 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
92ba5f51 1406 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
0ac32c83 1407 }
260c0cd3 1408 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
edb00035
IY		 1409 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1410 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
260c0cd3 1411 range_covers_byte(addr, l, PCI_COMMAND))
0ac32c83 1412 pci_update_mappings(d);
a7b15a5c 1413
1c380f94 1414 if (range_covers_byte(addr, l, PCI_COMMAND)) {
a7b15a5c 1415 pci_update_irq_disabled(d, was_irq_disabled);
1c380f94
AK		 1416 memory_region_set_enabled(&d->bus_master_enable_region,
1417 pci_get_word(d->config + PCI_COMMAND)
1418 & PCI_COMMAND_MASTER);
1419 }
95d65800 1420
d7efb7e0
KO		 1421 msi_write_config(d, addr, val_in, l);
1422 msix_write_config(d, addr, val_in, l);
69b91039
FB		 1423}
1424
502a5395
PB		 1425/***********************************************************/
1426/* generic PCI irq support */
30468f78 1427
502a5395 1428/* 0 <= irq_num <= 3. level must be 0 or 1 */
d98f08f5 1429static void pci_irq_handler(void *opaque, int irq_num, int level)
69b91039 1430{
a60380a5 1431 PCIDevice *pci_dev = opaque;
80b3ada7 1432 int change;
3b46e624 1433
d036bb21 1434 change = level - pci_irq_state(pci_dev, irq_num);
80b3ada7
PB		 1435 if (!change)
1436 return;
d2b59317 1437
d036bb21 1438 pci_set_irq_state(pci_dev, irq_num, level);
f9bf77dd 1439 pci_update_irq_status(pci_dev);
a7b15a5c
MT		 1440 if (pci_irq_disabled(pci_dev))
1441 return;
d036bb21 1442 pci_change_irq_level(pci_dev, irq_num, change);
69b91039
FB		 1443}
1444
d98f08f5
MA		 1445static inline int pci_intx(PCIDevice *pci_dev)
1446{
1447 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1448}
1449
1450qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1451{
1452 int intx = pci_intx(pci_dev);
1453
1454 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1455}
1456
1457void pci_set_irq(PCIDevice *pci_dev, int level)
1458{
1459 int intx = pci_intx(pci_dev);
1460 pci_irq_handler(pci_dev, intx, level);
1461}
1462
3afa9bb4
MT		 1463/* Special hooks used by device assignment */
1464void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1465{
0889464a 1466 assert(pci_bus_is_root(bus));
3afa9bb4
MT		 1467 bus->route_intx_to_irq = route_intx_to_irq;
1468}
1469
1470PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1471{
1472 PCIBus *bus;
1473
1474 do {
fd56e061
DG		 1475 bus = pci_get_bus(dev);
1476 pin = bus->map_irq(dev, pin);
1477 dev = bus->parent_dev;
3afa9bb4 1478 } while (dev);
05c0621e
AW		 1479
1480 if (!bus->route_intx_to_irq) {
312fd5f2 1481 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
05c0621e
AW		 1482 object_get_typename(OBJECT(bus->qbus.parent)));
1483 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1484 }
1485
3afa9bb4 1486 return bus->route_intx_to_irq(bus->irq_opaque, pin);
0ae16251
JK		 1487}
1488
d6e65d54
AW		 1489bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1490{
1491 return old->mode != new->mode || old->irq != new->irq;
1492}
1493
0ae16251
JK		 1494void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1495{
1496 PCIDevice *dev;
1497 PCIBus *sec;
1498 int i;
1499
1500 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1501 dev = bus->devices[i];
1502 if (dev && dev->intx_routing_notifier) {
1503 dev->intx_routing_notifier(dev);
1504 }
e5368f0d
AW		 1505 }
1506
1507 QLIST_FOREACH(sec, &bus->child, sibling) {
1508 pci_bus_fire_intx_routing_notifier(sec);
0ae16251
JK		 1509 }
1510}
1511
1512void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1513 PCIINTxRoutingNotifier notifier)
1514{
1515 dev->intx_routing_notifier = notifier;
69b91039
FB		 1516}
1517
91e56159
IY		 1518/*
1519 * PCI-to-PCI bridge specification
1520 * 9.1: Interrupt routing. Table 9-1
1521 *
1522 * the PCI Express Base Specification, Revision 2.1
1523 * 2.2.8.1: INTx interrutp signaling - Rules
1524 * the Implementation Note
1525 * Table 2-20
1526 */
1527/*
1528 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1529 * 0-origin unlike PCI interrupt pin register.
1530 */
1531int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1532{
e8ec4adf 1533 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);
91e56159
IY		 1534}
1535
502a5395
PB		 1536/***********************************************************/
1537/* monitor info on PCI */
0ac32c83 1538
6650ee6d
PB		 1539typedef struct {
1540 uint16_t class;
1541 const char *desc;
5e0259e7
GN		 1542 const char *fw_name;
1543 uint16_t fw_ign_bits;
6650ee6d
PB		 1544} pci_class_desc;
1545
09bc878a 1546static const pci_class_desc pci_class_descriptions[] =
6650ee6d 1547{
5e0259e7
GN		 1548 { 0x0001, "VGA controller", "display"},
1549 { 0x0100, "SCSI controller", "scsi"},
1550 { 0x0101, "IDE controller", "ide"},
1551 { 0x0102, "Floppy controller", "fdc"},
1552 { 0x0103, "IPI controller", "ipi"},
1553 { 0x0104, "RAID controller", "raid"},
dcb5b19a
TS		 1554 { 0x0106, "SATA controller"},
1555 { 0x0107, "SAS controller"},
1556 { 0x0180, "Storage controller"},
5e0259e7
GN		 1557 { 0x0200, "Ethernet controller", "ethernet"},
1558 { 0x0201, "Token Ring controller", "token-ring"},
1559 { 0x0202, "FDDI controller", "fddi"},
1560 { 0x0203, "ATM controller", "atm"},
dcb5b19a 1561 { 0x0280, "Network controller"},
5e0259e7 1562 { 0x0300, "VGA controller", "display", 0x00ff},
dcb5b19a
TS		 1563 { 0x0301, "XGA controller"},
1564 { 0x0302, "3D controller"},
1565 { 0x0380, "Display controller"},
5e0259e7
GN		 1566 { 0x0400, "Video controller", "video"},
1567 { 0x0401, "Audio controller", "sound"},
dcb5b19a 1568 { 0x0402, "Phone"},
602ef4d9 1569 { 0x0403, "Audio controller", "sound"},
dcb5b19a 1570 { 0x0480, "Multimedia controller"},
5e0259e7
GN		 1571 { 0x0500, "RAM controller", "memory"},
1572 { 0x0501, "Flash controller", "flash"},
dcb5b19a 1573 { 0x0580, "Memory controller"},
5e0259e7
GN		 1574 { 0x0600, "Host bridge", "host"},
1575 { 0x0601, "ISA bridge", "isa"},
1576 { 0x0602, "EISA bridge", "eisa"},
1577 { 0x0603, "MC bridge", "mca"},
4c41425d 1578 { 0x0604, "PCI bridge", "pci-bridge"},
5e0259e7
GN		 1579 { 0x0605, "PCMCIA bridge", "pcmcia"},
1580 { 0x0606, "NUBUS bridge", "nubus"},
1581 { 0x0607, "CARDBUS bridge", "cardbus"},
dcb5b19a
TS		 1582 { 0x0608, "RACEWAY bridge"},
1583 { 0x0680, "Bridge"},
5e0259e7
GN		 1584 { 0x0700, "Serial port", "serial"},
1585 { 0x0701, "Parallel port", "parallel"},
1586 { 0x0800, "Interrupt controller", "interrupt-controller"},
1587 { 0x0801, "DMA controller", "dma-controller"},
1588 { 0x0802, "Timer", "timer"},
1589 { 0x0803, "RTC", "rtc"},
1590 { 0x0900, "Keyboard", "keyboard"},
1591 { 0x0901, "Pen", "pen"},
1592 { 0x0902, "Mouse", "mouse"},
1593 { 0x0A00, "Dock station", "dock", 0x00ff},
1594 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1595 { 0x0c00, "Fireware contorller", "fireware"},
1596 { 0x0c01, "Access bus controller", "access-bus"},
1597 { 0x0c02, "SSA controller", "ssa"},
1598 { 0x0c03, "USB controller", "usb"},
1599 { 0x0c04, "Fibre channel controller", "fibre-channel"},
f7748569 1600 { 0x0c05, "SMBus"},
6650ee6d
PB		 1601 { 0, NULL}
1602};
1603
a8eeafda
GK		 1604static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1605 void (*fn)(PCIBus *b,
1606 PCIDevice *d,
1607 void *opaque),
1608 void *opaque)
1609{
1610 PCIDevice *d;
1611 int devfn;
1612
1613 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1614 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1615 if (d) {
1616 fn(bus, d, opaque);
1617 }
1618 }
1619}
1620
1621void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1622 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1623 void *opaque)
1624{
1625 bus = pci_find_bus_nr(bus, bus_num);
1626
1627 if (bus) {
1628 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1629 }
1630}
1631
163c8a59 1632static void pci_for_each_device_under_bus(PCIBus *bus,
7aa8cbb9
AP		 1633 void (*fn)(PCIBus *b, PCIDevice *d,
1634 void *opaque),
1635 void *opaque)
30468f78 1636{
163c8a59
LC		 1637 PCIDevice *d;
1638 int devfn;
30468f78 1639
163c8a59
LC		 1640 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1641 d = bus->devices[devfn];
1642 if (d) {
7aa8cbb9 1643 fn(bus, d, opaque);
163c8a59
LC		 1644 }
1645 }
1646}
1647
1648void pci_for_each_device(PCIBus *bus, int bus_num,
7aa8cbb9
AP		 1649 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1650 void *opaque)
163c8a59 1651{
d662210a 1652 bus = pci_find_bus_nr(bus, bus_num);
163c8a59
LC		 1653
1654 if (bus) {
7aa8cbb9 1655 pci_for_each_device_under_bus(bus, fn, opaque);
163c8a59
LC		 1656 }
1657}
1658
79627472 1659static const pci_class_desc *get_class_desc(int class)
163c8a59 1660{
79627472 1661 const pci_class_desc *desc;
163c8a59 1662
79627472
LC		 1663 desc = pci_class_descriptions;
1664 while (desc->desc && class != desc->class) {
1665 desc++;
30468f78 1666 }
b4dccd8d 1667
79627472
LC		 1668 return desc;
1669}
14421258 1670
79627472 1671static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
163c8a59 1672
79627472
LC		 1673static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1674{
1675 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1676 int i;
163c8a59 1677
79627472
LC		 1678 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1679 const PCIIORegion *r = &dev->io_regions[i];
1680 PciMemoryRegionList *region;
1681
1682 if (!r->size) {
1683 continue;
502a5395 1684 }
163c8a59 1685
79627472
LC		 1686 region = g_malloc0(sizeof(*region));
1687 region->value = g_malloc0(sizeof(*region->value));
163c8a59 1688
79627472
LC		 1689 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1690 region->value->type = g_strdup("io");
1691 } else {
1692 region->value->type = g_strdup("memory");
1693 region->value->has_prefetch = true;
1694 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1695 region->value->has_mem_type_64 = true;
1696 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
d5e4acf7 1697 }
163c8a59 1698
79627472
LC		 1699 region->value->bar = i;
1700 region->value->address = r->addr;
1701 region->value->size = r->size;
163c8a59 1702
79627472
LC		 1703 /* XXX: waiting for the qapi to support GSList */
1704 if (!cur_item) {
1705 head = cur_item = region;
1706 } else {
1707 cur_item->next = region;
1708 cur_item = region;
163c8a59 1709 }
80b3ada7 1710 }
384d8876 1711
79627472 1712 return head;
163c8a59
LC		 1713}
1714
79627472
LC		 1715static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1716 int bus_num)
163c8a59 1717{
79627472 1718 PciBridgeInfo *info;
9fa02cd1 1719 PciMemoryRange *range;
163c8a59 1720
9fa02cd1 1721 info = g_new0(PciBridgeInfo, 1);
163c8a59 1722
9fa02cd1
EB		 1723 info->bus = g_new0(PciBusInfo, 1);
1724 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1725 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1726 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
163c8a59 1727
9fa02cd1
EB		 1728 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1729 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1730 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
163c8a59 1731
9fa02cd1
EB		 1732 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1733 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1734 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
163c8a59 1735
9fa02cd1
EB		 1736 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1737 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1738 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
163c8a59 1739
79627472 1740 if (dev->config[PCI_SECONDARY_BUS] != 0) {
d662210a 1741 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
79627472
LC		 1742 if (child_bus) {
1743 info->has_devices = true;
1744 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1745 }
163c8a59
LC		 1746 }
1747
79627472 1748 return info;
163c8a59
LC		 1749}
1750
79627472
LC		 1751static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1752 int bus_num)
163c8a59 1753{
79627472
LC		 1754 const pci_class_desc *desc;
1755 PciDeviceInfo *info;
b5937f29 1756 uint8_t type;
79627472 1757 int class;
163c8a59 1758
9fa02cd1 1759 info = g_new0(PciDeviceInfo, 1);
79627472
LC		 1760 info->bus = bus_num;
1761 info->slot = PCI_SLOT(dev->devfn);
1762 info->function = PCI_FUNC(dev->devfn);
1763
9fa02cd1 1764 info->class_info = g_new0(PciDeviceClass, 1);
79627472 1765 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
9fa02cd1 1766 info->class_info->q_class = class;
79627472
LC		 1767 desc = get_class_desc(class);
1768 if (desc->desc) {
9fa02cd1
EB		 1769 info->class_info->has_desc = true;
1770 info->class_info->desc = g_strdup(desc->desc);
79627472
LC		 1771 }
1772
9fa02cd1
EB		 1773 info->id = g_new0(PciDeviceId, 1);
1774 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1775 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
79627472
LC		 1776 info->regions = qmp_query_pci_regions(dev);
1777 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
163c8a59
LC		 1778
1779 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
79627472
LC		 1780 info->has_irq = true;
1781 info->irq = dev->config[PCI_INTERRUPT_LINE];
163c8a59
LC		 1782 }
1783
b5937f29
IY		 1784 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1785 if (type == PCI_HEADER_TYPE_BRIDGE) {
79627472
LC		 1786 info->has_pci_bridge = true;
1787 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
18613dc6
DL		 1788 } else if (type == PCI_HEADER_TYPE_NORMAL) {
1789 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1790 info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
1791 info->id->subsystem_vendor =
1792 pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
1793 } else if (type == PCI_HEADER_TYPE_CARDBUS) {
1794 info->id->has_subsystem = info->id->has_subsystem_vendor = true;
1795 info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
1796 info->id->subsystem_vendor =
1797 pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
163c8a59
LC		 1798 }
1799
79627472 1800 return info;
163c8a59
LC		 1801}
1802
79627472 1803static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
384d8876 1804{
79627472 1805 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
163c8a59 1806 PCIDevice *dev;
79627472 1807 int devfn;
163c8a59
LC		 1808
1809 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1810 dev = bus->devices[devfn];
1811 if (dev) {
79627472
LC		 1812 info = g_malloc0(sizeof(*info));
1813 info->value = qmp_query_pci_device(dev, bus, bus_num);
1814
1815 /* XXX: waiting for the qapi to support GSList */
1816 if (!cur_item) {
1817 head = cur_item = info;
1818 } else {
1819 cur_item->next = info;
1820 cur_item = info;
1821 }
163c8a59 1822 }
1074df4f 1823 }
163c8a59 1824
79627472 1825 return head;
1074df4f
IY		 1826}
1827
79627472 1828static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1074df4f 1829{
79627472
LC		 1830 PciInfo *info = NULL;
1831
d662210a 1832 bus = pci_find_bus_nr(bus, bus_num);
502a5395 1833 if (bus) {
79627472
LC		 1834 info = g_malloc0(sizeof(*info));
1835 info->bus = bus_num;
1836 info->devices = qmp_query_pci_devices(bus, bus_num);
f2aa58c6 1837 }
163c8a59 1838
79627472 1839 return info;
f2aa58c6
FB		 1840}
1841
79627472 1842PciInfoList *qmp_query_pci(Error **errp)
f2aa58c6 1843{
79627472 1844 PciInfoList *info, *head = NULL, *cur_item = NULL;
7588e2b0 1845 PCIHostState *host_bridge;
163c8a59 1846
7588e2b0 1847 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
79627472 1848 info = g_malloc0(sizeof(*info));
cb2ed8b3
MA		 1849 info->value = qmp_query_pci_bus(host_bridge->bus,
1850 pci_bus_num(host_bridge->bus));
79627472
LC		 1851
1852 /* XXX: waiting for the qapi to support GSList */
1853 if (!cur_item) {
1854 head = cur_item = info;
1855 } else {
1856 cur_item->next = info;
1857 cur_item = info;
163c8a59 1858 }
e822a52a 1859 }
163c8a59 1860
79627472 1861 return head;
77d4bc34 1862}
a41b2ff2
PB		 1863
1864/* Initialize a PCI NIC. */
51f7cb97 1865PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
6dbcb819 1866 const char *default_model,
51f7cb97 1867 const char *default_devaddr)
a41b2ff2 1868{
5607c388 1869 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
52310c3f
PB		 1870 GSList *list;
1871 GPtrArray *pci_nic_models;
07caea31 1872 PCIBus *bus;
5607c388 1873 PCIDevice *pci_dev;
9d07d757 1874 DeviceState *dev;
51f7cb97 1875 int devfn;
cb457d76 1876 int i;
2ad778b8
DG		 1877 int dom, busnr;
1878 unsigned slot;
cb457d76 1879
52310c3f
PB		 1880 if (nd->model && !strcmp(nd->model, "virtio")) {
1881 g_free(nd->model);
1882 nd->model = g_strdup("virtio-net-pci");
1883 }
1884
1885 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1886 pci_nic_models = g_ptr_array_new();
1887 while (list) {
1888 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1889 TYPE_DEVICE);
1890 GSList *next;
1891 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1892 dc->user_creatable) {
1893 const char *name = object_class_get_name(list->data);
1894 g_ptr_array_add(pci_nic_models, (gpointer)name);
1895 }
1896 next = list->next;
1897 g_slist_free_1(list);
1898 list = next;
1899 }
1900 g_ptr_array_add(pci_nic_models, NULL);
1901
1902 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
51f7cb97
TH		 1903 exit(0);
1904 }
1905
52310c3f
PB		 1906 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1907 default_model);
51f7cb97
TH		 1908 if (i < 0) {
1909 exit(1);
1910 }
07caea31 1911
2ad778b8
DG		 1912 if (!rootbus) {
1913 error_report("No primary PCI bus");
1914 exit(1);
1915 }
1916
1917 assert(!rootbus->parent_dev);
1918
1919 if (!devaddr) {
1920 devfn = -1;
1921 busnr = 0;
1922 } else {
1923 if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
1924 error_report("Invalid PCI device address %s for device %s",
1925 devaddr, nd->model);
1926 exit(1);
1927 }
1928
1929 if (dom != 0) {
1930 error_report("No support for non-zero PCI domains");
1931 exit(1);
1932 }
1933
1934 devfn = PCI_DEVFN(slot, 0);
1935 }
1936
1937 bus = pci_find_bus_nr(rootbus, busnr);
07caea31 1938 if (!bus) {
1ecda02b 1939 error_report("Invalid PCI device address %s for device %s",
52310c3f 1940 devaddr, nd->model);
51f7cb97 1941 exit(1);
07caea31
MA		 1942 }
1943
52310c3f 1944 pci_dev = pci_create(bus, devfn, nd->model);
9ee05825 1945 dev = &pci_dev->qdev;
1cc33683 1946 qdev_set_nic_properties(dev, nd);
a023b7ac 1947 qdev_init_nofail(dev);
52310c3f 1948 g_ptr_array_free(pci_nic_models, true);
51f7cb97 1949 return pci_dev;
07caea31
MA		 1950}
1951
129d42fb
AJ		 1952PCIDevice *pci_vga_init(PCIBus *bus)
1953{
1954 switch (vga_interface_type) {
1955 case VGA_CIRRUS:
1956 return pci_create_simple(bus, -1, "cirrus-vga");
1957 case VGA_QXL:
1958 return pci_create_simple(bus, -1, "qxl-vga");
1959 case VGA_STD:
1960 return pci_create_simple(bus, -1, "VGA");
1961 case VGA_VMWARE:
1962 return pci_create_simple(bus, -1, "vmware-svga");
a94f0c5c
GH		 1963 case VGA_VIRTIO:
1964 return pci_create_simple(bus, -1, "virtio-vga");
129d42fb
AJ		 1965 case VGA_NONE:
1966 default: /* Other non-PCI types. Checking for unsupported types is already
1967 done in vl.c. */
1968 return NULL;
1969 }
1970}
1971
929176c3
MT		 1972/* Whether a given bus number is in range of the secondary
1973 * bus of the given bridge device. */
1974static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1975{
1976 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1977 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
09e5b819 1978 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
929176c3
MT		 1979 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1980}
1981
09e5b819
MA		 1982/* Whether a given bus number is in a range of a root bus */
1983static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1984{
1985 int i;
1986
1987 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1988 PCIDevice *dev = bus->devices[i];
1989
1990 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1991 if (pci_secondary_bus_in_range(dev, bus_num)) {
1992 return true;
1993 }
1994 }
1995 }
1996
1997 return false;
1998}
1999
d662210a 2000static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
3ae80618 2001{
470e6363 2002 PCIBus *sec;
3ae80618 2003
470e6363 2004 if (!bus) {
e822a52a 2005 return NULL;
470e6363 2006 }
3ae80618 2007
e822a52a
IY		 2008 if (pci_bus_num(bus) == bus_num) {
2009 return bus;
2010 }
2011
929176c3 2012 /* Consider all bus numbers in range for the host pci bridge. */
0889464a 2013 if (!pci_bus_is_root(bus) &&
929176c3
MT		 2014 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
2015 return NULL;
2016 }
2017
e822a52a 2018 /* try child bus */
929176c3
MT		 2019 for (; bus; bus = sec) {
2020 QLIST_FOREACH(sec, &bus->child, sibling) {
09e5b819 2021 if (pci_bus_num(sec) == bus_num) {
929176c3
MT		 2022 return sec;
2023 }
09e5b819
MA		 2024 /* PXB buses assumed to be children of bus 0 */
2025 if (pci_bus_is_root(sec)) {
2026 if (pci_root_bus_in_range(sec, bus_num)) {
2027 break;
2028 }
2029 } else {
2030 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
2031 break;
2032 }
c021f8e6 2033 }
e822a52a
IY		 2034 }
2035 }
2036
2037 return NULL;
3ae80618
AL		 2038}
2039
eb0acfdd
MT		 2040void pci_for_each_bus_depth_first(PCIBus *bus,
2041 void *(*begin)(PCIBus *bus, void *parent_state),
2042 void (*end)(PCIBus *bus, void *state),
2043 void *parent_state)
2044{
2045 PCIBus *sec;
2046 void *state;
2047
2048 if (!bus) {
2049 return;
2050 }
2051
2052 if (begin) {
2053 state = begin(bus, parent_state);
2054 } else {
2055 state = parent_state;
2056 }
2057
2058 QLIST_FOREACH(sec, &bus->child, sibling) {
2059 pci_for_each_bus_depth_first(sec, begin, end, state);
2060 }
2061
2062 if (end) {
2063 end(bus, state);
2064 }
2065}
2066
2067
5256d8bf 2068PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
3ae80618 2069{
d662210a 2070 bus = pci_find_bus_nr(bus, bus_num);
3ae80618
AL		 2071
2072 if (!bus)
2073 return NULL;
2074
5256d8bf 2075 return bus->devices[devfn];
3ae80618
AL		 2076}
2077
133e9b22 2078static void pci_qdev_realize(DeviceState *qdev, Error **errp)
6b1b92d3
PB		 2079{
2080 PCIDevice *pci_dev = (PCIDevice *)qdev;
40021f08 2081 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
d61a363d 2082 ObjectClass *klass = OBJECT_CLASS(pc);
133e9b22 2083 Error *local_err = NULL;
ab85ceb1 2084 bool is_default_rom;
4f5b6a05 2085 uint16_t class_id;
6b1b92d3 2086
d61a363d
YB		 2087 /* initialize cap_present for pci_is_express() and pci_config_size(),
2088 * Note that hybrid PCIs are not set automatically and need to manage
2089 * QEMU_PCI_CAP_EXPRESS manually */
2090 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2091 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
a9f49946
IY		 2092 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2093 }
2094
fd56e061 2095 pci_dev = do_pci_register_device(pci_dev,
6e008585 2096 object_get_typename(OBJECT(qdev)),
133e9b22 2097 pci_dev->devfn, errp);
09e3acc6 2098 if (pci_dev == NULL)
133e9b22 2099 return;
2897ae02 2100
7ee6c1e1
MA		 2101 if (pc->realize) {
2102 pc->realize(pci_dev, &local_err);
2103 if (local_err) {
2104 error_propagate(errp, local_err);
c2afc922 2105 do_pci_unregister_device(pci_dev);
133e9b22 2106 return;
c2afc922 2107 }
925fe64a 2108 }
8c52c8f3 2109
4f5b6a05
JF		 2110 if (pci_dev->failover_pair_id) {
2111 if (!pci_bus_is_express(pci_get_bus(pci_dev))) {
2112 error_setg(errp, "failover primary device must be on "
2113 "PCIExpress bus");
2114 error_propagate(errp, local_err);
b69c3c21 2115 pci_qdev_unrealize(DEVICE(pci_dev));
4f5b6a05
JF		 2116 return;
2117 }
2118 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);
2119 if (class_id != PCI_CLASS_NETWORK_ETHERNET) {
2120 error_setg(errp, "failover primary device is not an "
2121 "Ethernet device");
2122 error_propagate(errp, local_err);
b69c3c21 2123 pci_qdev_unrealize(DEVICE(pci_dev));
4f5b6a05
JF		 2124 return;
2125 }
2126 if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)
2127 && (PCI_FUNC(pci_dev->devfn) == 0)) {
2128 qdev->allow_unplug_during_migration = true;
2129 } else {
2130 error_setg(errp, "failover: primary device must be in its own "
2131 "PCI slot");
2132 error_propagate(errp, local_err);
b69c3c21 2133 pci_qdev_unrealize(DEVICE(pci_dev));
4f5b6a05
JF		 2134 return;
2135 }
a1190ab6 2136 qdev->allow_unplug_during_migration = true;
4f5b6a05
JF		 2137 }
2138
8c52c8f3 2139 /* rom loading */
ab85ceb1 2140 is_default_rom = false;
40021f08
AL		 2141 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2142 pci_dev->romfile = g_strdup(pc->romfile);
ab85ceb1
SW		 2143 is_default_rom = true;
2144 }
178e785f 2145
133e9b22
MA		 2146 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2147 if (local_err) {
2148 error_propagate(errp, local_err);
b69c3c21 2149 pci_qdev_unrealize(DEVICE(pci_dev));
133e9b22 2150 return;
178e785f 2151 }
ee995ffb
GH		 2152}
2153
49823868
IY		 2154PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2155 const char *name)
6b1b92d3
PB		 2156{
2157 DeviceState *dev;
2158
02e2da45 2159 dev = qdev_create(&bus->qbus, name);
09f1bbcd 2160 qdev_prop_set_int32(dev, "addr", devfn);
49823868 2161 qdev_prop_set_bit(dev, "multifunction", multifunction);
40021f08 2162 return PCI_DEVICE(dev);
71077c1c 2163}
6b1b92d3 2164
49823868
IY		 2165PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2166 bool multifunction,
2167 const char *name)
71077c1c 2168{
49823868 2169 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
e23a1b33 2170 qdev_init_nofail(&dev->qdev);
71077c1c 2171 return dev;
6b1b92d3 2172}
6f4cbd39 2173
49823868
IY		 2174PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2175{
2176 return pci_create_multifunction(bus, devfn, false, name);
2177}
2178
2179PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2180{
2181 return pci_create_simple_multifunction(bus, devfn, false, name);
2182}
2183
b56d701f 2184static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
6f4cbd39
MT		 2185{
2186 int offset = PCI_CONFIG_HEADER_SIZE;
2187 int i;
b56d701f 2188 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
6f4cbd39
MT		 2189 if (pdev->used[i])
2190 offset = i + 1;
2191 else if (i - offset + 1 == size)
2192 return offset;
b56d701f 2193 }
6f4cbd39
MT		 2194 return 0;
2195}
2196
2197static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2198 uint8_t *prev_p)
2199{
2200 uint8_t next, prev;
2201
2202 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2203 return 0;
2204
2205 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2206 prev = next + PCI_CAP_LIST_NEXT)
2207 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2208 break;
2209
2210 if (prev_p)
2211 *prev_p = prev;
2212 return next;
2213}
2214
c9abe111
JK		 2215static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2216{
2217 uint8_t next, prev, found = 0;
2218
2219 if (!(pdev->used[offset])) {
2220 return 0;
2221 }
2222
2223 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2224
2225 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2226 prev = next + PCI_CAP_LIST_NEXT) {
2227 if (next <= offset && next > found) {
2228 found = next;
2229 }
2230 }
2231 return found;
2232}
2233
ab85ceb1
SW		 2234/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2235 This is needed for an option rom which is used for more than one device. */
2236static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2237{
2238 uint16_t vendor_id;
2239 uint16_t device_id;
2240 uint16_t rom_vendor_id;
2241 uint16_t rom_device_id;
2242 uint16_t rom_magic;
2243 uint16_t pcir_offset;
2244 uint8_t checksum;
2245
2246 /* Words in rom data are little endian (like in PCI configuration),
2247 so they can be read / written with pci_get_word / pci_set_word. */
2248
2249 /* Only a valid rom will be patched. */
2250 rom_magic = pci_get_word(ptr);
2251 if (rom_magic != 0xaa55) {
2252 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2253 return;
2254 }
2255 pcir_offset = pci_get_word(ptr + 0x18);
2256 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2257 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2258 return;
2259 }
2260
2261 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2262 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2263 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2264 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2265
2266 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2267 vendor_id, device_id, rom_vendor_id, rom_device_id);
2268
2269 checksum = ptr[6];
2270
2271 if (vendor_id != rom_vendor_id) {
2272 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2273 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2274 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2275 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2276 ptr[6] = checksum;
2277 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2278 }
2279
2280 if (device_id != rom_device_id) {
2281 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2282 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2283 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2284 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2285 ptr[6] = checksum;
2286 pci_set_word(ptr + pcir_offset + 6, device_id);
2287 }
2288}
2289
c2039bd0 2290/* Add an option rom for the device */
133e9b22
MA		 2291static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2292 Error **errp)
c2039bd0
AL		 2293{
2294 int size;
2295 char *path;
2296 void *ptr;
1724f049 2297 char name[32];
4be9f0d1 2298 const VMStateDescription *vmsd;
c2039bd0 2299
8c52c8f3 2300 if (!pdev->romfile)
133e9b22 2301 return;
8c52c8f3 2302 if (strlen(pdev->romfile) == 0)
133e9b22 2303 return;
8c52c8f3 2304
88169ddf
GH		 2305 if (!pdev->rom_bar) {
2306 /*
2307 * Load rom via fw_cfg instead of creating a rom bar,
2308 * for 0.11 compatibility.
2309 */
2310 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
db80c7b9
MA		 2311
2312 /*
2313 * Hot-plugged devices can't use the option ROM
2314 * if the rom bar is disabled.
2315 */
2316 if (DEVICE(pdev)->hotplugged) {
133e9b22
MA		 2317 error_setg(errp, "Hot-plugged device without ROM bar"
2318 " can't have an option ROM");
2319 return;
db80c7b9
MA		 2320 }
2321
88169ddf
GH		 2322 if (class == 0x0300) {
2323 rom_add_vga(pdev->romfile);
2324 } else {
2e55e842 2325 rom_add_option(pdev->romfile, -1);
88169ddf 2326 }
133e9b22 2327 return;
88169ddf
GH		 2328 }
2329
8c52c8f3 2330 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
c2039bd0 2331 if (path == NULL) {
7267c094 2332 path = g_strdup(pdev->romfile);
c2039bd0
AL		 2333 }
2334
2335 size = get_image_size(path);
8c52c8f3 2336 if (size < 0) {
133e9b22 2337 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
8c7f3dd0 2338 g_free(path);
133e9b22 2339 return;
8c7f3dd0 2340 } else if (size == 0) {
133e9b22 2341 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
7267c094 2342 g_free(path);
133e9b22 2343 return;
8c52c8f3 2344 }
9bff5d81 2345 size = pow2ceil(size);
c2039bd0 2346
4be9f0d1
AL		 2347 vmsd = qdev_get_vmsd(DEVICE(pdev));
2348
2349 if (vmsd) {
2350 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2351 } else {
f79f2bfc 2352 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
4be9f0d1 2353 }
14caaf7f 2354 pdev->has_rom = true;
fefa9256 2355 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
14caaf7f 2356 ptr = memory_region_get_ram_ptr(&pdev->rom);
36bde091
PM		 2357 if (load_image_size(path, ptr, size) < 0) {
2358 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
2359 g_free(path);
2360 return;
2361 }
7267c094 2362 g_free(path);
c2039bd0 2363
ab85ceb1
SW		 2364 if (is_default_rom) {
2365 /* Only the default rom images will be patched (if needed). */
2366 pci_patch_ids(pdev, ptr, size);
2367 }
2368
e824b2cc 2369 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
c2039bd0
AL		 2370}
2371
230741dc
AW		 2372static void pci_del_option_rom(PCIDevice *pdev)
2373{
14caaf7f 2374 if (!pdev->has_rom)
230741dc
AW		 2375 return;
2376
c5705a77 2377 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
14caaf7f 2378 pdev->has_rom = false;
230741dc
AW		 2379}
2380
ca77089d 2381/*
27841278 2382 * On success, pci_add_capability() returns a positive value
eacbc632
MZ		 2383 * that the offset of the pci capability.
2384 * On failure, it sets an error and returns a negative error
2385 * code.
2386 */
27841278 2387int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
cd9aa33e
LE		 2388 uint8_t offset, uint8_t size,
2389 Error **errp)
6f4cbd39 2390{
ca77089d 2391 uint8_t *config;
c9abe111
JK		 2392 int i, overlapping_cap;
2393
ca77089d
IY		 2394 if (!offset) {
2395 offset = pci_find_space(pdev, size);
97fe42f1
C		 2396 /* out of PCI config space is programming error */
2397 assert(offset);
c9abe111
JK		 2398 } else {
2399 /* Verify that capabilities don't overlap. Note: device assignment
2400 * depends on this check to verify that the device is not broken.
2401 * Should never trigger for emulated devices, but it's helpful
2402 * for debugging these. */
2403 for (i = offset; i < offset + size; i++) {
2404 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2405 if (overlapping_cap) {
cd9aa33e
LE		 2406 error_setg(errp, "%s:%02x:%02x.%x "
2407 "Attempt to add PCI capability %x at offset "
2408 "%x overlaps existing capability %x at offset %x",
fd56e061 2409 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
cd9aa33e
LE		 2410 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2411 cap_id, offset, overlapping_cap, i);
c9abe111
JK		 2412 return -EINVAL;
2413 }
2414 }
ca77089d
IY		 2415 }
2416
2417 config = pdev->config + offset;
6f4cbd39
MT		 2418 config[PCI_CAP_LIST_ID] = cap_id;
2419 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2420 pdev->config[PCI_CAPABILITY_LIST] = offset;
2421 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
e26631b7 2422 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2423 /* Make capability read-only by default */
2424 memset(pdev->wmask + offset, 0, size);
bd4b65ee
MT		 2425 /* Check capability by default */
2426 memset(pdev->cmask + offset, 0xFF, size);
6f4cbd39
MT		 2427 return offset;
2428}
2429
2430/* Unlink capability from the pci config space. */
2431void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2432{
2433 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2434 if (!offset)
2435 return;
2436 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
ebabb67a 2437 /* Make capability writable again */
6f4cbd39 2438 memset(pdev->wmask + offset, 0xff, size);
1a4f5971 2439 memset(pdev->w1cmask + offset, 0, size);
bd4b65ee
MT		 2440 /* Clear cmask as device-specific registers can't be checked */
2441 memset(pdev->cmask + offset, 0, size);
e26631b7 2442 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
6f4cbd39
MT		 2443
2444 if (!pdev->config[PCI_CAPABILITY_LIST])
2445 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2446}
2447
6f4cbd39
MT		 2448uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2449{
2450 return pci_find_capability_list(pdev, cap_id, NULL);
2451}
10c4c98a
GH		 2452
2453static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2454{
2455 PCIDevice *d = (PCIDevice *)dev;
2456 const pci_class_desc *desc;
2457 char ctxt[64];
2458 PCIIORegion *r;
2459 int i, class;
2460
b0ff8eb2 2461 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
10c4c98a
GH		 2462 desc = pci_class_descriptions;
2463 while (desc->desc && class != desc->class)
2464 desc++;
2465 if (desc->desc) {
2466 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2467 } else {
2468 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2469 }
2470
2471 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2472 "pci id %04x:%04x (sub %04x:%04x)\n",
fd56e061 2473 indent, "", ctxt, pci_dev_bus_num(d),
e822a52a 2474 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
b0ff8eb2
IY		 2475 pci_get_word(d->config + PCI_VENDOR_ID),
2476 pci_get_word(d->config + PCI_DEVICE_ID),
2477 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2478 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
10c4c98a
GH		 2479 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2480 r = &d->io_regions[i];
2481 if (!r->size)
2482 continue;
89e8b13c
IY		 2483 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2484 " [0x%"FMT_PCIBUS"]\n",
2485 indent, "",
0392a017 2486 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
10c4c98a
GH		 2487 r->addr, r->addr + r->size - 1);
2488 }
2489}
03587182 2490
5e0259e7
GN		 2491static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2492{
2493 PCIDevice *d = (PCIDevice *)dev;
2494 const char *name = NULL;
2495 const pci_class_desc *desc = pci_class_descriptions;
2496 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2497
2498 while (desc->desc &&
2499 (class & ~desc->fw_ign_bits) !=
2500 (desc->class & ~desc->fw_ign_bits)) {
2501 desc++;
2502 }
2503
2504 if (desc->desc) {
2505 name = desc->fw_name;
2506 }
2507
2508 if (name) {
2509 pstrcpy(buf, len, name);
2510 } else {
2511 snprintf(buf, len, "pci%04x,%04x",
2512 pci_get_word(d->config + PCI_VENDOR_ID),
2513 pci_get_word(d->config + PCI_DEVICE_ID));
2514 }
2515
2516 return buf;
2517}
2518
2519static char *pcibus_get_fw_dev_path(DeviceState *dev)
2520{
2521 PCIDevice *d = (PCIDevice *)dev;
2522 char path[50], name[33];
2523 int off;
2524
2525 off = snprintf(path, sizeof(path), "%s@%x",
2526 pci_dev_fw_name(dev, name, sizeof name),
2527 PCI_SLOT(d->devfn));
2528 if (PCI_FUNC(d->devfn))
2529 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
a5cf8262 2530 return g_strdup(path);
5e0259e7
GN		 2531}
2532
4f43c1ff
AW		 2533static char *pcibus_get_dev_path(DeviceState *dev)
2534{
a6a7005d
MT		 2535 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2536 PCIDevice *t;
2537 int slot_depth;
2538 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2539 * 00 is added here to make this format compatible with
2540 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2541 * Slot.Function list specifies the slot and function numbers for all
2542 * devices on the path from root to the specific device. */
568f0690
DG		 2543 const char *root_bus_path;
2544 int root_bus_len;
2991181a 2545 char slot[] = ":SS.F";
2991181a 2546 int slot_len = sizeof slot - 1 /* For '\0' */;
a6a7005d
MT		 2547 int path_len;
2548 char *path, *p;
2991181a 2549 int s;
a6a7005d 2550
568f0690
DG		 2551 root_bus_path = pci_root_bus_path(d);
2552 root_bus_len = strlen(root_bus_path);
2553
a6a7005d
MT		 2554 /* Calculate # of slots on path between device and root. */;
2555 slot_depth = 0;
fd56e061 2556 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d
MT		 2557 ++slot_depth;
2558 }
2559
568f0690 2560 path_len = root_bus_len + slot_len * slot_depth;
a6a7005d
MT		 2561
2562 /* Allocate memory, fill in the terminating null byte. */
7267c094 2563 path = g_malloc(path_len + 1 /* For '\0' */);
a6a7005d
MT		 2564 path[path_len] = '\0';
2565
568f0690 2566 memcpy(path, root_bus_path, root_bus_len);
a6a7005d
MT		 2567
2568 /* Fill in slot numbers. We walk up from device to root, so need to print
2569 * them in the reverse order, last to first. */
2570 p = path + path_len;
fd56e061 2571 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
a6a7005d 2572 p -= slot_len;
2991181a 2573 s = snprintf(slot, sizeof slot, ":%02x.%x",
4c900518 2574 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2991181a
MT		 2575 assert(s == slot_len);
2576 memcpy(p, slot, slot_len);
a6a7005d
MT		 2577 }
2578
2579 return path;
4f43c1ff
AW		 2580}
2581
f3006dd1
IY		 2582static int pci_qdev_find_recursive(PCIBus *bus,
2583 const char *id, PCIDevice **pdev)
2584{
2585 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2586 if (!qdev) {
2587 return -ENODEV;
2588 }
2589
2590 /* roughly check if given qdev is pci device */
4be9f0d1 2591 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
40021f08 2592 *pdev = PCI_DEVICE(qdev);
f3006dd1
IY		 2593 return 0;
2594 }
2595 return -EINVAL;
2596}
2597
2598int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2599{
7588e2b0 2600 PCIHostState *host_bridge;
f3006dd1
IY		 2601 int rc = -ENODEV;
2602
7588e2b0
DG		 2603 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2604 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
f3006dd1
IY		 2605 if (!tmp) {
2606 rc = 0;
2607 break;
2608 }
2609 if (tmp != -ENODEV) {
2610 rc = tmp;
2611 }
2612 }
2613
2614 return rc;
2615}
f5e6fed8
AK		 2616
2617MemoryRegion *pci_address_space(PCIDevice *dev)
2618{
fd56e061 2619 return pci_get_bus(dev)->address_space_mem;
f5e6fed8 2620}
e11d6439
RH		 2621
2622MemoryRegion *pci_address_space_io(PCIDevice *dev)
2623{
fd56e061 2624 return pci_get_bus(dev)->address_space_io;
e11d6439 2625}
40021f08 2626
39bffca2
AL		 2627static void pci_device_class_init(ObjectClass *klass, void *data)
2628{
2629 DeviceClass *k = DEVICE_CLASS(klass);
7ee6c1e1 2630
133e9b22
MA		 2631 k->realize = pci_qdev_realize;
2632 k->unrealize = pci_qdev_unrealize;
0d936928 2633 k->bus_type = TYPE_PCI_BUS;
4f67d30b 2634 device_class_set_props(k, pci_props);
39bffca2
AL		 2635}
2636
2fefa16c
EH		 2637static void pci_device_class_base_init(ObjectClass *klass, void *data)
2638{
2639 if (!object_class_is_abstract(klass)) {
2640 ObjectClass *conventional =
2641 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2642 ObjectClass *pcie =
2643 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2644 assert(conventional || pcie);
2645 }
2646}
2647
9eda7d37
AK		 2648AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2649{
fd56e061 2650 PCIBus *bus = pci_get_bus(dev);
5af2ae23 2651 PCIBus *iommu_bus = bus;
77ef8f8d 2652 uint8_t devfn = dev->devfn;
9eda7d37 2653
77ef8f8d
AW		 2654 while (iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2655 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev);
2656
2657 /*
2658 * The requester ID of the provided device may be aliased, as seen from
2659 * the IOMMU, due to topology limitations. The IOMMU relies on a
2660 * requester ID to provide a unique AddressSpace for devices, but
2661 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2662 * to-PCI bridge creates and accepts transactions on behalf of down-
2663 * stream devices. When doing so, all downstream devices are masked
2664 * (aliased) behind a single requester ID. The requester ID used
2665 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2666 * bridges, with a PCIe capability indicating such, follow the
2667 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2668 * where the bridge uses the seconary bus as the bridge portion of the
2669 * requester ID and devfn of 00.0. For other bridges, typically those
2670 * found on the root complex such as the dmi-to-pci-bridge, we follow
2671 * the convention of typical bare-metal hardware, which uses the
2672 * requester ID of the bridge itself. There are device specific
2673 * exceptions to these rules, but these are the defaults that the
2674 * Linux kernel uses when determining DMA aliases itself and believed
2675 * to be true for the bare metal equivalents of the devices emulated
2676 * in QEMU.
2677 */
2678 if (!pci_bus_is_express(iommu_bus)) {
2679 PCIDevice *parent = iommu_bus->parent_dev;
2680
2681 if (pci_is_express(parent) &&
2682 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
2683 devfn = PCI_DEVFN(0, 0);
2684 bus = iommu_bus;
2685 } else {
2686 devfn = parent->devfn;
2687 bus = parent_bus;
2688 }
2689 }
2690
2691 iommu_bus = parent_bus;
9eda7d37 2692 }
5af2ae23 2693 if (iommu_bus && iommu_bus->iommu_fn) {
77ef8f8d 2694 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn);
9eda7d37 2695 }
9eda7d37
AK		 2696 return &address_space_memory;
2697}
2698
e00387d5 2699void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
5fa45de5 2700{
e00387d5
AK		 2701 bus->iommu_fn = fn;
2702 bus->iommu_opaque = opaque;
5fa45de5
DG		 2703}
2704
43864069
MT		 2705static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2706{
2707 Range *range = opaque;
2708 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2709 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
77d6f4ea 2710 int i;
43864069
MT		 2711
2712 if (!(cmd & PCI_COMMAND_MEMORY)) {
2713 return;
2714 }
2715
2716 if (pc->is_bridge) {
2717 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2718 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2719
2720 base = MAX(base, 0x1ULL << 32);
2721
2722 if (limit >= base) {
2723 Range pref_range;
a0efbf16 2724 range_set_bounds(&pref_range, base, limit);
43864069
MT		 2725 range_extend(range, &pref_range);
2726 }
2727 }
77d6f4ea
MT		 2728 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2729 PCIIORegion *r = &dev->io_regions[i];
a0efbf16 2730 pcibus_t lob, upb;
43864069
MT		 2731 Range region_range;
2732
77d6f4ea
MT		 2733 if (!r->size ||
2734 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2735 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2736 continue;
2737 }
77d6f4ea 2738
a0efbf16
MA		 2739 lob = pci_bar_address(dev, i, r->type, r->size);
2740 upb = lob + r->size - 1;
2741 if (lob == PCI_BAR_UNMAPPED) {
43864069
MT		 2742 continue;
2743 }
43864069 2744
a0efbf16 2745 lob = MAX(lob, 0x1ULL << 32);
43864069 2746
a0efbf16
MA		 2747 if (upb >= lob) {
2748 range_set_bounds(&region_range, lob, upb);
43864069
MT		 2749 range_extend(range, &region_range);
2750 }
2751 }
2752}
2753
2754void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2755{
a0efbf16 2756 range_make_empty(range);
43864069
MT		 2757 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2758}
2759
3f1e1478
C		 2760static bool pcie_has_upstream_port(PCIDevice *dev)
2761{
fd56e061 2762 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
3f1e1478
C		 2763
2764 /* Device associated with an upstream port.
2765 * As there are several types of these, it's easier to check the
2766 * parent device: upstream ports are always connected to
2767 * root or downstream ports.
2768 */
2769 return parent_dev &&
2770 pci_is_express(parent_dev) &&
2771 parent_dev->exp.exp_cap &&
2772 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2773 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2774}
2775
2776PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2777{
fd56e061
DG		 2778 PCIBus *bus = pci_get_bus(pci_dev);
2779
3f1e1478
C		 2780 if(pcie_has_upstream_port(pci_dev)) {
2781 /* With an upstream PCIe port, we only support 1 device at slot 0 */
fd56e061 2782 return bus->devices[0];
3f1e1478
C		 2783 } else {
2784 /* Other bus types might support multiple devices at slots 0-31 */
fd56e061 2785 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
3f1e1478
C		 2786 }
2787}
2788
e1d4fb2d
PX		 2789MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2790{
2791 MSIMessage msg;
2792 if (msix_enabled(dev)) {
2793 msg = msix_get_message(dev, vector);
2794 } else if (msi_enabled(dev)) {
2795 msg = msi_get_message(dev, vector);
2796 } else {
2797 /* Should never happen */
2798 error_report("%s: unknown interrupt type", __func__);
2799 abort();
2800 }
2801 return msg;
2802}
2803
8c43a6f0 2804static const TypeInfo pci_device_type_info = {
40021f08
AL		 2805 .name = TYPE_PCI_DEVICE,
2806 .parent = TYPE_DEVICE,
2807 .instance_size = sizeof(PCIDevice),
2808 .abstract = true,
2809 .class_size = sizeof(PCIDeviceClass),
39bffca2 2810 .class_init = pci_device_class_init,
2fefa16c 2811 .class_base_init = pci_device_class_base_init,
40021f08
AL		 2812};
2813
83f7d43a 2814static void pci_register_types(void)
40021f08 2815{
0d936928 2816 type_register_static(&pci_bus_info);
3a861c46 2817 type_register_static(&pcie_bus_info);
619f02ae
EH		 2818 type_register_static(&conventional_pci_interface_info);
2819 type_register_static(&pcie_interface_info);
40021f08
AL		 2820 type_register_static(&pci_device_type_info);
2821}
2822
83f7d43a 2823type_init(pci_register_types)
QEMU mirror