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hw/pci/pci_host: Let pci_data_[read/write] use unsigned 'size' argument
[mirror_qemu.git] / hw / pci / pci_host.c
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1/*
2 * pci_host.c
3 *
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
70539e18 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 */
20
97d5408f 21#include "qemu/osdep.h"
c759b24f 22#include "hw/pci/pci.h"
c2077e2c 23#include "hw/pci/pci_bridge.h"
c759b24f 24#include "hw/pci/pci_host.h"
0b8fa32f 25#include "qemu/module.h"
3f1e1478 26#include "hw/pci/pci_bus.h"
3bf4dfdd 27#include "trace.h"
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28
29/* debug PCI */
30//#define DEBUG_PCI
31
32#ifdef DEBUG_PCI
33#define PCI_DPRINTF(fmt, ...) \
34do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
35#else
36#define PCI_DPRINTF(fmt, ...)
37#endif
38
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39/*
40 * PCI address
41 * bit 16 - 24: bus number
42 * bit 8 - 15: devfun number
43 * bit 0 - 7: offset in configuration space of a given pci device
44 */
45
085d8134 46/* the helper function to get a PCIDevice* for a given pci address */
8d6514f8 47static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
766347cc 48{
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49 uint8_t bus_num = addr >> 16;
50 uint8_t devfn = addr >> 8;
51
5256d8bf 52 return pci_find_device(bus, bus_num, devfn);
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53}
54
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55static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
56{
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57 if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
58 !pci_bus_allows_extended_config_space(bus)) {
59 *limit = PCI_CONFIG_SPACE_SIZE;
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60 }
61}
62
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63void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
64 uint32_t limit, uint32_t val, uint32_t len)
65{
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66 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
67 if (limit <= addr) {
68 return;
69 }
70
42e4126b 71 assert(len <= 4);
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72 /* non-zero functions are only exposed when function 0 is present,
73 * allowing direct removal of unexposed functions.
74 */
75 if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
76 return;
77 }
78
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79 trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn),
80 PCI_FUNC(pci_dev->devfn), addr, val);
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81 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
82}
83
84uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
85 uint32_t limit, uint32_t len)
86{
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87 uint32_t ret;
88
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89 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
90 if (limit <= addr) {
91 return ~0x0;
92 }
93
42e4126b 94 assert(len <= 4);
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95 /* non-zero functions are only exposed when function 0 is present,
96 * allowing direct removal of unexposed functions.
97 */
98 if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
99 return ~0x0;
100 }
101
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102 ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
103 trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn),
104 PCI_FUNC(pci_dev->devfn), addr, ret);
105
106 return ret;
42e4126b
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107}
108
f2a7e8f1 109void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len)
766347cc 110{
8d6514f8 111 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
7ac901cd 112 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
766347cc 113
42e4126b 114 if (!pci_dev) {
766347cc 115 return;
42e4126b 116 }
766347cc 117
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118 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
119 val, len);
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120}
121
f2a7e8f1 122uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len)
766347cc 123{
8d6514f8 124 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
7ac901cd 125 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
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126
127 if (!pci_dev) {
4677d8ed 128 return ~0x0;
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129 }
130
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131 return pci_host_config_read_common(pci_dev, config_addr,
132 PCI_CONFIG_SPACE_SIZE, len);
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133}
134
a8170e5e 135static void pci_host_config_write(void *opaque, hwaddr addr,
d0ed8076 136 uint64_t val, unsigned len)
a455783b 137{
d0ed8076 138 PCIHostState *s = opaque;
a455783b 139
d0ed8076 140 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
9f6f0423 141 __func__, addr, len, val);
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142 if (addr != 0 || len != 4) {
143 return;
144 }
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145 s->config_reg = val;
146}
147
a8170e5e 148static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
d0ed8076 149 unsigned len)
a455783b 150{
d0ed8076 151 PCIHostState *s = opaque;
a455783b 152 uint32_t val = s->config_reg;
952760bb 153
d0ed8076 154 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
9f6f0423 155 __func__, addr, len, val);
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156 return val;
157}
158
a8170e5e 159static void pci_host_data_write(void *opaque, hwaddr addr,
d0ed8076 160 uint64_t val, unsigned len)
a455783b 161{
d0ed8076 162 PCIHostState *s = opaque;
4ce537a7 163
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164 if (s->config_reg & (1u << 31))
165 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
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166}
167
d0ed8076 168static uint64_t pci_host_data_read(void *opaque,
a8170e5e 169 hwaddr addr, unsigned len)
a455783b 170{
d0ed8076 171 PCIHostState *s = opaque;
4ce537a7 172
ac43fa50 173 if (!(s->config_reg & (1U << 31))) {
9f6f0423 174 return 0xffffffff;
ac43fa50 175 }
4ce537a7 176 return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
9f6f0423 177}
a455783b 178
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179const MemoryRegionOps pci_host_conf_le_ops = {
180 .read = pci_host_config_read,
181 .write = pci_host_config_write,
182 .endianness = DEVICE_LITTLE_ENDIAN,
183};
a455783b 184
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185const MemoryRegionOps pci_host_conf_be_ops = {
186 .read = pci_host_config_read,
187 .write = pci_host_config_write,
188 .endianness = DEVICE_BIG_ENDIAN,
189};
d2c33733 190
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191const MemoryRegionOps pci_host_data_le_ops = {
192 .read = pci_host_data_read,
193 .write = pci_host_data_write,
194 .endianness = DEVICE_LITTLE_ENDIAN,
195};
196
197const MemoryRegionOps pci_host_data_be_ops = {
198 .read = pci_host_data_read,
199 .write = pci_host_data_write,
200 .endianness = DEVICE_BIG_ENDIAN,
201};
a455783b 202
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203static const TypeInfo pci_host_type_info = {
204 .name = TYPE_PCI_HOST_BRIDGE,
205 .parent = TYPE_SYS_BUS_DEVICE,
206 .abstract = true,
568f0690 207 .class_size = sizeof(PCIHostBridgeClass),
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AF
208 .instance_size = sizeof(PCIHostState),
209};
210
211static void pci_host_register_types(void)
212{
213 type_register_static(&pci_host_type_info);
214}
4f5e19e6 215
b44ff9d4 216type_init(pci_host_register_types)