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4f5e19e6 IY |
1 | /* |
2 | * pci_host.c | |
3 | * | |
4 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> | |
5 | * VA Linux Systems Japan K.K. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | ||
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | ||
17 | * You should have received a copy of the GNU General Public License along | |
70539e18 | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
4f5e19e6 IY |
19 | */ |
20 | ||
97d5408f | 21 | #include "qemu/osdep.h" |
c759b24f | 22 | #include "hw/pci/pci.h" |
c2077e2c | 23 | #include "hw/pci/pci_bridge.h" |
c759b24f | 24 | #include "hw/pci/pci_host.h" |
2ebc2121 | 25 | #include "hw/qdev-properties.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
3f1e1478 | 27 | #include "hw/pci/pci_bus.h" |
2ebc2121 | 28 | #include "migration/vmstate.h" |
3bf4dfdd | 29 | #include "trace.h" |
4f5e19e6 IY |
30 | |
31 | /* debug PCI */ | |
32 | //#define DEBUG_PCI | |
33 | ||
34 | #ifdef DEBUG_PCI | |
35 | #define PCI_DPRINTF(fmt, ...) \ | |
36 | do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) | |
37 | #else | |
38 | #define PCI_DPRINTF(fmt, ...) | |
39 | #endif | |
40 | ||
766347cc IY |
41 | /* |
42 | * PCI address | |
43 | * bit 16 - 24: bus number | |
44 | * bit 8 - 15: devfun number | |
45 | * bit 0 - 7: offset in configuration space of a given pci device | |
46 | */ | |
47 | ||
085d8134 | 48 | /* the helper function to get a PCIDevice* for a given pci address */ |
8d6514f8 | 49 | static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) |
766347cc | 50 | { |
42331e9f IY |
51 | uint8_t bus_num = addr >> 16; |
52 | uint8_t devfn = addr >> 8; | |
53 | ||
5256d8bf | 54 | return pci_find_device(bus, bus_num, devfn); |
766347cc IY |
55 | } |
56 | ||
c2077e2c AW |
57 | static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) |
58 | { | |
2f57db8a DG |
59 | if ((*limit > PCI_CONFIG_SPACE_SIZE) && |
60 | !pci_bus_allows_extended_config_space(bus)) { | |
61 | *limit = PCI_CONFIG_SPACE_SIZE; | |
c2077e2c AW |
62 | } |
63 | } | |
64 | ||
348e3544 YB |
65 | static bool is_pci_dev_ejected(PCIDevice *pci_dev) |
66 | { | |
67 | /* | |
68 | * device unplug was requested and the guest acked it, | |
69 | * so we stop responding config accesses even if the | |
70 | * device is not deleted (failover flow) | |
71 | */ | |
72 | return pci_dev && pci_dev->partially_hotplugged && | |
73 | !pci_dev->qdev.pending_deleted_event; | |
74 | } | |
75 | ||
42e4126b JK |
76 | void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, |
77 | uint32_t limit, uint32_t val, uint32_t len) | |
78 | { | |
c2077e2c AW |
79 | pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); |
80 | if (limit <= addr) { | |
81 | return; | |
82 | } | |
83 | ||
42e4126b | 84 | assert(len <= 4); |
3f1e1478 C |
85 | /* non-zero functions are only exposed when function 0 is present, |
86 | * allowing direct removal of unexposed functions. | |
87 | */ | |
23786d13 | 88 | if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || |
348e3544 | 89 | !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) { |
3f1e1478 C |
90 | return; |
91 | } | |
92 | ||
deeb956c LV |
93 | trace_pci_cfg_write(pci_dev->name, pci_dev_bus_num(pci_dev), |
94 | PCI_SLOT(pci_dev->devfn), | |
3bf4dfdd | 95 | PCI_FUNC(pci_dev->devfn), addr, val); |
42e4126b JK |
96 | pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); |
97 | } | |
98 | ||
99 | uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, | |
100 | uint32_t limit, uint32_t len) | |
101 | { | |
3bf4dfdd AK |
102 | uint32_t ret; |
103 | ||
c2077e2c AW |
104 | pci_adjust_config_limit(pci_get_bus(pci_dev), &limit); |
105 | if (limit <= addr) { | |
106 | return ~0x0; | |
107 | } | |
108 | ||
42e4126b | 109 | assert(len <= 4); |
3f1e1478 C |
110 | /* non-zero functions are only exposed when function 0 is present, |
111 | * allowing direct removal of unexposed functions. | |
112 | */ | |
23786d13 | 113 | if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) || |
348e3544 | 114 | !pci_dev->has_power || is_pci_dev_ejected(pci_dev)) { |
3f1e1478 C |
115 | return ~0x0; |
116 | } | |
117 | ||
3bf4dfdd | 118 | ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr)); |
deeb956c LV |
119 | trace_pci_cfg_read(pci_dev->name, pci_dev_bus_num(pci_dev), |
120 | PCI_SLOT(pci_dev->devfn), | |
3bf4dfdd AK |
121 | PCI_FUNC(pci_dev->devfn), addr, ret); |
122 | ||
123 | return ret; | |
42e4126b JK |
124 | } |
125 | ||
f2a7e8f1 | 126 | void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len) |
766347cc | 127 | { |
8d6514f8 | 128 | PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
7ac901cd | 129 | uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); |
766347cc | 130 | |
42e4126b | 131 | if (!pci_dev) { |
1bdad09b PMD |
132 | trace_pci_cfg_write("empty", extract32(addr, 16, 8), |
133 | extract32(addr, 11, 5), extract32(addr, 8, 3), | |
134 | config_addr, val); | |
766347cc | 135 | return; |
42e4126b | 136 | } |
766347cc | 137 | |
42e4126b JK |
138 | pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, |
139 | val, len); | |
766347cc IY |
140 | } |
141 | ||
f2a7e8f1 | 142 | uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len) |
766347cc | 143 | { |
8d6514f8 | 144 | PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
7ac901cd | 145 | uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); |
766347cc IY |
146 | |
147 | if (!pci_dev) { | |
1bdad09b PMD |
148 | trace_pci_cfg_read("empty", extract32(addr, 16, 8), |
149 | extract32(addr, 11, 5), extract32(addr, 8, 3), | |
150 | config_addr, ~0x0); | |
4677d8ed | 151 | return ~0x0; |
766347cc IY |
152 | } |
153 | ||
4ce537a7 PMD |
154 | return pci_host_config_read_common(pci_dev, config_addr, |
155 | PCI_CONFIG_SPACE_SIZE, len); | |
766347cc IY |
156 | } |
157 | ||
a8170e5e | 158 | static void pci_host_config_write(void *opaque, hwaddr addr, |
d0ed8076 | 159 | uint64_t val, unsigned len) |
a455783b | 160 | { |
d0ed8076 | 161 | PCIHostState *s = opaque; |
a455783b | 162 | |
883f2c59 | 163 | PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n", |
9f6f0423 | 164 | __func__, addr, len, val); |
cdde6ffc AK |
165 | if (addr != 0 || len != 4) { |
166 | return; | |
167 | } | |
a455783b IY |
168 | s->config_reg = val; |
169 | } | |
170 | ||
a8170e5e | 171 | static uint64_t pci_host_config_read(void *opaque, hwaddr addr, |
d0ed8076 | 172 | unsigned len) |
a455783b | 173 | { |
d0ed8076 | 174 | PCIHostState *s = opaque; |
a455783b | 175 | uint32_t val = s->config_reg; |
952760bb | 176 | |
883f2c59 | 177 | PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n", |
9f6f0423 | 178 | __func__, addr, len, val); |
a455783b IY |
179 | return val; |
180 | } | |
181 | ||
a8170e5e | 182 | static void pci_host_data_write(void *opaque, hwaddr addr, |
d0ed8076 | 183 | uint64_t val, unsigned len) |
a455783b | 184 | { |
d0ed8076 | 185 | PCIHostState *s = opaque; |
4ce537a7 | 186 | |
9f6f0423 MT |
187 | if (s->config_reg & (1u << 31)) |
188 | pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); | |
a455783b IY |
189 | } |
190 | ||
d0ed8076 | 191 | static uint64_t pci_host_data_read(void *opaque, |
a8170e5e | 192 | hwaddr addr, unsigned len) |
a455783b | 193 | { |
d0ed8076 | 194 | PCIHostState *s = opaque; |
4ce537a7 | 195 | |
ac43fa50 | 196 | if (!(s->config_reg & (1U << 31))) { |
9f6f0423 | 197 | return 0xffffffff; |
ac43fa50 | 198 | } |
4ce537a7 | 199 | return pci_data_read(s->bus, s->config_reg | (addr & 3), len); |
9f6f0423 | 200 | } |
a455783b | 201 | |
d0ed8076 AK |
202 | const MemoryRegionOps pci_host_conf_le_ops = { |
203 | .read = pci_host_config_read, | |
204 | .write = pci_host_config_write, | |
205 | .endianness = DEVICE_LITTLE_ENDIAN, | |
206 | }; | |
a455783b | 207 | |
d0ed8076 AK |
208 | const MemoryRegionOps pci_host_conf_be_ops = { |
209 | .read = pci_host_config_read, | |
210 | .write = pci_host_config_write, | |
211 | .endianness = DEVICE_BIG_ENDIAN, | |
212 | }; | |
d2c33733 | 213 | |
d0ed8076 AK |
214 | const MemoryRegionOps pci_host_data_le_ops = { |
215 | .read = pci_host_data_read, | |
216 | .write = pci_host_data_write, | |
217 | .endianness = DEVICE_LITTLE_ENDIAN, | |
218 | }; | |
219 | ||
220 | const MemoryRegionOps pci_host_data_be_ops = { | |
221 | .read = pci_host_data_read, | |
222 | .write = pci_host_data_write, | |
223 | .endianness = DEVICE_BIG_ENDIAN, | |
224 | }; | |
a455783b | 225 | |
2ebc2121 HW |
226 | static bool pci_host_needed(void *opaque) |
227 | { | |
228 | PCIHostState *s = opaque; | |
229 | return s->mig_enabled; | |
230 | } | |
231 | ||
232 | const VMStateDescription vmstate_pcihost = { | |
233 | .name = "PCIHost", | |
234 | .needed = pci_host_needed, | |
235 | .version_id = 1, | |
236 | .minimum_version_id = 1, | |
8e5e0890 | 237 | .fields = (const VMStateField[]) { |
2ebc2121 HW |
238 | VMSTATE_UINT32(config_reg, PCIHostState), |
239 | VMSTATE_END_OF_LIST() | |
240 | } | |
241 | }; | |
242 | ||
243 | static Property pci_host_properties_common[] = { | |
244 | DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, | |
245 | mig_enabled, true), | |
3b20f4ca | 246 | DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false), |
2ebc2121 HW |
247 | DEFINE_PROP_END_OF_LIST(), |
248 | }; | |
249 | ||
250 | static void pci_host_class_init(ObjectClass *klass, void *data) | |
251 | { | |
252 | DeviceClass *dc = DEVICE_CLASS(klass); | |
253 | device_class_set_props(dc, pci_host_properties_common); | |
254 | dc->vmsd = &vmstate_pcihost; | |
255 | } | |
256 | ||
b44ff9d4 AF |
257 | static const TypeInfo pci_host_type_info = { |
258 | .name = TYPE_PCI_HOST_BRIDGE, | |
259 | .parent = TYPE_SYS_BUS_DEVICE, | |
260 | .abstract = true, | |
568f0690 | 261 | .class_size = sizeof(PCIHostBridgeClass), |
b44ff9d4 | 262 | .instance_size = sizeof(PCIHostState), |
2ebc2121 | 263 | .class_init = pci_host_class_init, |
b44ff9d4 AF |
264 | }; |
265 | ||
266 | static void pci_host_register_types(void) | |
267 | { | |
268 | type_register_static(&pci_host_type_info); | |
269 | } | |
4f5e19e6 | 270 | |
b44ff9d4 | 271 | type_init(pci_host_register_types) |