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0428527c IY |
1 | /* |
2 | * pcie.c | |
3 | * | |
4 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
5 | * VA Linux Systems Japan K.K. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
97d5408f | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
c759b24f MT |
23 | #include "hw/pci/pci_bridge.h" |
24 | #include "hw/pci/pcie.h" | |
25 | #include "hw/pci/msix.h" | |
26 | #include "hw/pci/msi.h" | |
06aac7bd | 27 | #include "hw/pci/pci_bus.h" |
c759b24f | 28 | #include "hw/pci/pcie_regs.h" |
3d67447f | 29 | #include "hw/pci/pcie_port.h" |
1de7afc9 | 30 | #include "qemu/range.h" |
0428527c IY |
31 | |
32 | //#define DEBUG_PCIE | |
33 | #ifdef DEBUG_PCIE | |
34 | # define PCIE_DPRINTF(fmt, ...) \ | |
35 | fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) | |
36 | #else | |
37 | # define PCIE_DPRINTF(fmt, ...) do {} while (0) | |
38 | #endif | |
39 | #define PCIE_DEV_PRINTF(dev, fmt, ...) \ | |
40 | PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) | |
41 | ||
42 | ||
43 | /*************************************************************************** | |
44 | * pci express capability helper functions | |
45 | */ | |
0428527c | 46 | |
6383292a | 47 | static void |
6b449540 | 48 | pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) |
6383292a | 49 | { |
6b449540 MT |
50 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
51 | uint8_t *cmask = dev->cmask + dev->exp.exp_cap; | |
52 | ||
0428527c | 53 | /* capability register |
6383292a | 54 | interrupt message number defaults to 0 */ |
0428527c IY |
55 | pci_set_word(exp_cap + PCI_EXP_FLAGS, |
56 | ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | | |
6383292a | 57 | version); |
0428527c IY |
58 | |
59 | /* device capability register | |
60 | * table 7-12: | |
61 | * roll based error reporting bit must be set by all | |
62 | * Functions conforming to the ECN, PCI Express Base | |
63 | * Specification, Revision 1.1., or subsequent PCI Express Base | |
64 | * Specification revisions. | |
65 | */ | |
66 | pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); | |
67 | ||
68 | pci_set_long(exp_cap + PCI_EXP_LNKCAP, | |
69 | (port << PCI_EXP_LNKCAP_PN_SHIFT) | | |
70 | PCI_EXP_LNKCAP_ASPMS_0S | | |
d96a0ac7 AW |
71 | QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | |
72 | QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT)); | |
0428527c IY |
73 | |
74 | pci_set_word(exp_cap + PCI_EXP_LNKSTA, | |
d96a0ac7 AW |
75 | QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | |
76 | QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); | |
6b449540 MT |
77 | |
78 | if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { | |
79 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, | |
80 | PCI_EXP_LNKSTA_DLLLA); | |
81 | } | |
82 | ||
83 | /* We changed link status bits over time, and changing them across | |
84 | * migrations is generally fine as hardware changes them too. | |
85 | * Let's not bother checking. | |
86 | */ | |
87 | pci_set_word(cmask + PCI_EXP_LNKSTA, 0); | |
6383292a DF |
88 | } |
89 | ||
3d67447f AW |
90 | static void pcie_cap_fill_slot_lnk(PCIDevice *dev) |
91 | { | |
92 | PCIESlot *s = (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT); | |
93 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; | |
94 | ||
95 | /* Skip anything that isn't a PCIESlot */ | |
96 | if (!s) { | |
97 | return; | |
98 | } | |
99 | ||
100 | /* Clear and fill LNKCAP from what was configured above */ | |
101 | pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, | |
102 | PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); | |
103 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, | |
104 | QEMU_PCI_EXP_LNKCAP_MLW(s->width) | | |
105 | QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); | |
106 | ||
107 | /* | |
108 | * Link bandwidth notification is required for all root ports and | |
109 | * downstream ports supporting links wider than x1 or multiple link | |
110 | * speeds. | |
111 | */ | |
112 | if (s->width > QEMU_PCI_EXP_LNK_X1 || | |
113 | s->speed > QEMU_PCI_EXP_LNK_2_5GT) { | |
114 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, | |
115 | PCI_EXP_LNKCAP_LBNC); | |
116 | } | |
117 | ||
118 | if (s->speed > QEMU_PCI_EXP_LNK_2_5GT) { | |
119 | /* | |
120 | * Hot-plug capable downstream ports and downstream ports supporting | |
121 | * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC | |
122 | * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which | |
123 | * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also | |
124 | * technically implement this, but it's not done here for compatibility. | |
125 | */ | |
126 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, | |
127 | PCI_EXP_LNKCAP_DLLLARC); | |
128 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, | |
129 | PCI_EXP_LNKSTA_DLLLA); | |
130 | ||
131 | /* | |
132 | * Target Link Speed defaults to the highest link speed supported by | |
133 | * the component. 2.5GT/s devices are permitted to hardwire to zero. | |
134 | */ | |
135 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKCTL2, | |
136 | PCI_EXP_LNKCTL2_TLS); | |
137 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKCTL2, | |
138 | QEMU_PCI_EXP_LNKCAP_MLS(s->speed) & | |
139 | PCI_EXP_LNKCTL2_TLS); | |
140 | } | |
141 | ||
142 | /* | |
143 | * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is | |
144 | * actually a reference to the highest bit supported in this register. | |
145 | * We assume the device supports all link speeds. | |
146 | */ | |
147 | if (s->speed > QEMU_PCI_EXP_LNK_5GT) { | |
148 | pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP2, ~0U); | |
149 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, | |
150 | PCI_EXP_LNKCAP2_SLS_2_5GB | | |
151 | PCI_EXP_LNKCAP2_SLS_5_0GB | | |
152 | PCI_EXP_LNKCAP2_SLS_8_0GB); | |
153 | if (s->speed > QEMU_PCI_EXP_LNK_8GT) { | |
154 | pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2, | |
155 | PCI_EXP_LNKCAP2_SLS_16_0GB); | |
156 | } | |
157 | } | |
158 | } | |
159 | ||
f8cd1b02 MZ |
160 | int pcie_cap_init(PCIDevice *dev, uint8_t offset, |
161 | uint8_t type, uint8_t port, | |
162 | Error **errp) | |
6383292a DF |
163 | { |
164 | /* PCIe cap v2 init */ | |
165 | int pos; | |
166 | uint8_t *exp_cap; | |
167 | ||
168 | assert(pci_is_express(dev)); | |
169 | ||
9a7c2a59 | 170 | pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, |
f8cd1b02 | 171 | PCI_EXP_VER2_SIZEOF, errp); |
6383292a DF |
172 | if (pos < 0) { |
173 | return pos; | |
174 | } | |
175 | dev->exp.exp_cap = pos; | |
176 | exp_cap = dev->config + pos; | |
177 | ||
178 | /* Filling values common with v1 */ | |
6b449540 | 179 | pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2); |
0428527c | 180 | |
3d67447f AW |
181 | /* Fill link speed and width options */ |
182 | pcie_cap_fill_slot_lnk(dev); | |
183 | ||
6383292a | 184 | /* Filling v2 specific values */ |
0428527c IY |
185 | pci_set_long(exp_cap + PCI_EXP_DEVCAP2, |
186 | PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); | |
187 | ||
30b04f87 | 188 | pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); |
f03d8ea3 MA |
189 | |
190 | if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { | |
191 | /* read-only to behave like a 'NULL' Extended Capability Header */ | |
192 | pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); | |
193 | } | |
194 | ||
0428527c IY |
195 | return pos; |
196 | } | |
197 | ||
6383292a DF |
198 | int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, |
199 | uint8_t port) | |
200 | { | |
201 | /* PCIe cap v1 init */ | |
202 | int pos; | |
9a7c2a59 | 203 | Error *local_err = NULL; |
6383292a DF |
204 | |
205 | assert(pci_is_express(dev)); | |
206 | ||
9a7c2a59 MZ |
207 | pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, |
208 | PCI_EXP_VER1_SIZEOF, &local_err); | |
6383292a | 209 | if (pos < 0) { |
9a7c2a59 | 210 | error_report_err(local_err); |
6383292a DF |
211 | return pos; |
212 | } | |
213 | dev->exp.exp_cap = pos; | |
6383292a | 214 | |
6b449540 | 215 | pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); |
6383292a DF |
216 | |
217 | return pos; | |
218 | } | |
219 | ||
220 | static int | |
221 | pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) | |
6214e73c AW |
222 | { |
223 | uint8_t type = PCI_EXP_TYPE_ENDPOINT; | |
f8cd1b02 MZ |
224 | Error *local_err = NULL; |
225 | int ret; | |
6214e73c AW |
226 | |
227 | /* | |
228 | * Windows guests will report Code 10, device cannot start, if | |
229 | * a regular Endpoint type is exposed on a root complex. These | |
230 | * should instead be Root Complex Integrated Endpoints. | |
231 | */ | |
fd56e061 DG |
232 | if (pci_bus_is_express(pci_get_bus(dev)) |
233 | && pci_bus_is_root(pci_get_bus(dev))) { | |
6214e73c AW |
234 | type = PCI_EXP_TYPE_RC_END; |
235 | } | |
236 | ||
f8cd1b02 MZ |
237 | if (cap_size == PCI_EXP_VER1_SIZEOF) { |
238 | return pcie_cap_v1_init(dev, offset, type, 0); | |
239 | } else { | |
240 | ret = pcie_cap_init(dev, offset, type, 0, &local_err); | |
241 | ||
242 | if (ret < 0) { | |
243 | error_report_err(local_err); | |
244 | } | |
245 | ||
246 | return ret; | |
247 | } | |
6383292a DF |
248 | } |
249 | ||
250 | int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) | |
251 | { | |
252 | return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); | |
253 | } | |
254 | ||
255 | int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) | |
256 | { | |
257 | return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); | |
6214e73c AW |
258 | } |
259 | ||
0428527c IY |
260 | void pcie_cap_exit(PCIDevice *dev) |
261 | { | |
262 | pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); | |
263 | } | |
264 | ||
6383292a DF |
265 | void pcie_cap_v1_exit(PCIDevice *dev) |
266 | { | |
267 | pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF); | |
268 | } | |
269 | ||
0428527c IY |
270 | uint8_t pcie_cap_get_type(const PCIDevice *dev) |
271 | { | |
272 | uint32_t pos = dev->exp.exp_cap; | |
273 | assert(pos > 0); | |
274 | return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & | |
275 | PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; | |
276 | } | |
277 | ||
278 | /* MSI/MSI-X */ | |
279 | /* pci express interrupt message number */ | |
280 | /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ | |
281 | void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) | |
282 | { | |
283 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; | |
284 | assert(vector < 32); | |
285 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); | |
286 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, | |
287 | vector << PCI_EXP_FLAGS_IRQ_SHIFT); | |
288 | } | |
289 | ||
290 | uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) | |
291 | { | |
292 | return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & | |
293 | PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; | |
294 | } | |
295 | ||
296 | void pcie_cap_deverr_init(PCIDevice *dev) | |
297 | { | |
298 | uint32_t pos = dev->exp.exp_cap; | |
299 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, | |
300 | PCI_EXP_DEVCAP_RBER); | |
301 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, | |
302 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | | |
303 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); | |
304 | pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, | |
305 | PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | | |
8e815eee | 306 | PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); |
0428527c IY |
307 | } |
308 | ||
309 | void pcie_cap_deverr_reset(PCIDevice *dev) | |
310 | { | |
311 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; | |
312 | pci_long_test_and_clear_mask(devctl, | |
313 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | | |
314 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); | |
315 | } | |
316 | ||
d584f1b9 MA |
317 | void pcie_cap_lnkctl_init(PCIDevice *dev) |
318 | { | |
319 | uint32_t pos = dev->exp.exp_cap; | |
320 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, | |
321 | PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); | |
322 | } | |
323 | ||
324 | void pcie_cap_lnkctl_reset(PCIDevice *dev) | |
325 | { | |
326 | uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; | |
327 | pci_long_test_and_clear_mask(lnkctl, | |
328 | PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); | |
329 | } | |
330 | ||
6bde6aaa MT |
331 | static void hotplug_event_update_event_status(PCIDevice *dev) |
332 | { | |
333 | uint32_t pos = dev->exp.exp_cap; | |
334 | uint8_t *exp_cap = dev->config + pos; | |
335 | uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); | |
336 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); | |
337 | ||
338 | dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && | |
339 | (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); | |
340 | } | |
341 | ||
342 | static void hotplug_event_notify(PCIDevice *dev) | |
343 | { | |
344 | bool prev = dev->exp.hpev_notified; | |
345 | ||
346 | hotplug_event_update_event_status(dev); | |
347 | ||
348 | if (prev == dev->exp.hpev_notified) { | |
349 | return; | |
350 | } | |
351 | ||
352 | /* Note: the logic above does not take into account whether interrupts | |
353 | * are masked. The result is that interrupt will be sent when it is | |
354 | * subsequently unmasked. This appears to be legal: Section 6.7.3.4: | |
355 | * The Port may optionally send an MSI when there are hot-plug events that | |
356 | * occur while interrupt generation is disabled, and interrupt generation is | |
357 | * subsequently enabled. */ | |
4a9dd665 MT |
358 | if (msix_enabled(dev)) { |
359 | msix_notify(dev, pcie_cap_flags_get_vector(dev)); | |
360 | } else if (msi_enabled(dev)) { | |
361 | msi_notify(dev, pcie_cap_flags_get_vector(dev)); | |
362 | } else { | |
5a03e708 | 363 | pci_set_irq(dev, dev->exp.hpev_notified); |
6bde6aaa MT |
364 | } |
365 | } | |
366 | ||
1553d4f1 IY |
367 | static void hotplug_event_clear(PCIDevice *dev) |
368 | { | |
369 | hotplug_event_update_event_status(dev); | |
370 | if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { | |
5a03e708 | 371 | pci_irq_deassert(dev); |
1553d4f1 IY |
372 | } |
373 | } | |
374 | ||
0428527c | 375 | /* |
a1c7273b | 376 | * A PCI Express Hot-Plug Event has occurred, so update slot status register |
0428527c IY |
377 | * and notify OS of the event if necessary. |
378 | * | |
379 | * 6.7.3 PCI Express Hot-Plug Events | |
380 | * 6.7.3.4 Software Notification of Hot-Plug Events | |
381 | */ | |
382 | static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) | |
383 | { | |
6bde6aaa MT |
384 | /* Minor optimization: if nothing changed - no event is needed. */ |
385 | if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + | |
386 | PCI_EXP_SLTSTA, event)) { | |
0428527c IY |
387 | return; |
388 | } | |
6bde6aaa | 389 | hotplug_event_notify(dev); |
0428527c IY |
390 | } |
391 | ||
5571727a | 392 | static void pcie_cap_slot_plug_common(PCIDevice *hotplug_dev, DeviceState *dev, |
b9731850 | 393 | Error **errp) |
0428527c | 394 | { |
b9731850 DH |
395 | uint8_t *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; |
396 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); | |
0428527c | 397 | |
e4bcd27c | 398 | PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); |
0428527c IY |
399 | if (sltsta & PCI_EXP_SLTSTA_EIS) { |
400 | /* the slot is electromechanically locked. | |
401 | * This error is propagated up to qdev and then to HMP/QMP. | |
402 | */ | |
6c150fbd | 403 | error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); |
0428527c | 404 | } |
a66e657e IM |
405 | } |
406 | ||
b9731850 DH |
407 | void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
408 | Error **errp) | |
409 | { | |
410 | pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, errp); | |
411 | } | |
412 | ||
5571727a DH |
413 | void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
414 | Error **errp) | |
a66e657e | 415 | { |
b9731850 DH |
416 | PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); |
417 | uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; | |
6e1f0a55 | 418 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
a66e657e | 419 | |
a66e657e IM |
420 | /* Don't send event when device is enabled during qemu machine creation: |
421 | * it is present on boot, no hotplug event is necessary. We do send an | |
422 | * event when the device is disabled later. */ | |
423 | if (!dev->hotplugged) { | |
0428527c IY |
424 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
425 | PCI_EXP_SLTSTA_PDS); | |
2f2b18f6 ZX |
426 | if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { |
427 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, | |
428 | PCI_EXP_LNKSTA_DLLLA); | |
429 | } | |
a66e657e | 430 | return; |
0428527c | 431 | } |
a66e657e | 432 | |
3f1e1478 C |
433 | /* To enable multifunction hot-plug, we just ensure the function |
434 | * 0 added last. When function 0 is added, we set the sltsta and | |
435 | * inform OS via event notification. | |
6e1f0a55 | 436 | */ |
3f1e1478 C |
437 | if (pci_get_function_0(pci_dev)) { |
438 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, | |
439 | PCI_EXP_SLTSTA_PDS); | |
2f2b18f6 ZX |
440 | if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { |
441 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, | |
442 | PCI_EXP_LNKSTA_DLLLA); | |
443 | } | |
3f1e1478 C |
444 | pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), |
445 | PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); | |
446 | } | |
a66e657e IM |
447 | } |
448 | ||
a1952d01 DH |
449 | void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, |
450 | Error **errp) | |
0d1c7d88 | 451 | { |
07578b0a | 452 | object_property_set_bool(OBJECT(dev), false, "realized", NULL); |
0d1c7d88 C |
453 | } |
454 | ||
a1952d01 DH |
455 | static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) |
456 | { | |
457 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(dev)); | |
458 | ||
459 | hotplug_handler_unplug(hotplug_ctrl, DEVICE(dev), &error_abort); | |
07578b0a | 460 | object_unparent(OBJECT(dev)); |
a1952d01 DH |
461 | } |
462 | ||
5571727a DH |
463 | void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, |
464 | DeviceState *dev, Error **errp) | |
a66e657e | 465 | { |
b9731850 | 466 | Error *local_err = NULL; |
0d1c7d88 | 467 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
fd56e061 | 468 | PCIBus *bus = pci_get_bus(pci_dev); |
a66e657e | 469 | |
b9731850 DH |
470 | pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, &local_err); |
471 | if (local_err) { | |
472 | error_propagate(errp, local_err); | |
473 | return; | |
474 | } | |
a66e657e | 475 | |
0d1c7d88 C |
476 | /* In case user cancel the operation of multi-function hot-add, |
477 | * remove the function that is unexposed to guest individually, | |
478 | * without interaction with guest. | |
479 | */ | |
480 | if (pci_dev->devfn && | |
481 | !bus->devices[0]) { | |
482 | pcie_unplug_device(bus, pci_dev, NULL); | |
483 | ||
484 | return; | |
485 | } | |
486 | ||
554f802d | 487 | pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); |
0428527c IY |
488 | } |
489 | ||
490 | /* pci express slot for pci express root/downstream port | |
491 | PCI express capability slot registers */ | |
492 | void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) | |
493 | { | |
494 | uint32_t pos = dev->exp.exp_cap; | |
495 | ||
496 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, | |
497 | PCI_EXP_FLAGS_SLOT); | |
498 | ||
499 | pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
500 | ~PCI_EXP_SLTCAP_PSN); | |
501 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
502 | (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | | |
503 | PCI_EXP_SLTCAP_EIP | | |
504 | PCI_EXP_SLTCAP_HPS | | |
505 | PCI_EXP_SLTCAP_HPC | | |
506 | PCI_EXP_SLTCAP_PIP | | |
507 | PCI_EXP_SLTCAP_AIP | | |
508 | PCI_EXP_SLTCAP_ABP); | |
509 | ||
f23b6bdc MA |
510 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
511 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
512 | PCI_EXP_SLTCAP_PCP); | |
513 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, | |
514 | PCI_EXP_SLTCTL_PCC); | |
515 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
516 | PCI_EXP_SLTCTL_PCC); | |
517 | } | |
518 | ||
0428527c IY |
519 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, |
520 | PCI_EXP_SLTCTL_PIC | | |
521 | PCI_EXP_SLTCTL_AIC); | |
522 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, | |
523 | PCI_EXP_SLTCTL_PIC_OFF | | |
524 | PCI_EXP_SLTCTL_AIC_OFF); | |
525 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
526 | PCI_EXP_SLTCTL_PIC | | |
527 | PCI_EXP_SLTCTL_AIC | | |
528 | PCI_EXP_SLTCTL_HPIE | | |
529 | PCI_EXP_SLTCTL_CCIE | | |
530 | PCI_EXP_SLTCTL_PDCE | | |
531 | PCI_EXP_SLTCTL_ABPE); | |
532 | /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, | |
533 | * make the bit writable here in order to detect 1b is written. | |
534 | * pcie_cap_slot_write_config() test-and-clear the bit, so | |
535 | * this bit always returns 0 to the guest. | |
536 | */ | |
537 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
538 | PCI_EXP_SLTCTL_EIC); | |
539 | ||
540 | pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, | |
541 | PCI_EXP_HP_EV_SUPPORTED); | |
542 | ||
6bde6aaa MT |
543 | dev->exp.hpev_notified = false; |
544 | ||
a66e657e | 545 | qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), |
94d1cc5f | 546 | OBJECT(dev), NULL); |
0428527c IY |
547 | } |
548 | ||
549 | void pcie_cap_slot_reset(PCIDevice *dev) | |
550 | { | |
551 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; | |
f23b6bdc MA |
552 | uint8_t port_type = pcie_cap_get_type(dev); |
553 | ||
554 | assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || | |
555 | port_type == PCI_EXP_TYPE_ROOT_PORT); | |
0428527c IY |
556 | |
557 | PCIE_DEV_PRINTF(dev, "reset\n"); | |
558 | ||
559 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, | |
560 | PCI_EXP_SLTCTL_EIC | | |
561 | PCI_EXP_SLTCTL_PIC | | |
562 | PCI_EXP_SLTCTL_AIC | | |
563 | PCI_EXP_SLTCTL_HPIE | | |
564 | PCI_EXP_SLTCTL_CCIE | | |
565 | PCI_EXP_SLTCTL_PDCE | | |
566 | PCI_EXP_SLTCTL_ABPE); | |
567 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, | |
0428527c IY |
568 | PCI_EXP_SLTCTL_AIC_OFF); |
569 | ||
f23b6bdc | 570 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
f23b6bdc | 571 | /* Downstream ports enforce device number 0. */ |
20de98af MT |
572 | bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; |
573 | uint16_t pic; | |
f23b6bdc MA |
574 | |
575 | if (populated) { | |
576 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, | |
577 | PCI_EXP_SLTCTL_PCC); | |
578 | } else { | |
579 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, | |
580 | PCI_EXP_SLTCTL_PCC); | |
581 | } | |
582 | ||
583 | pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; | |
584 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); | |
20de98af | 585 | } |
f23b6bdc | 586 | |
0428527c IY |
587 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
588 | PCI_EXP_SLTSTA_EIS |/* on reset, | |
589 | the lock is released */ | |
590 | PCI_EXP_SLTSTA_CC | | |
591 | PCI_EXP_SLTSTA_PDC | | |
592 | PCI_EXP_SLTSTA_ABP); | |
6bde6aaa | 593 | |
804b2071 | 594 | hotplug_event_update_event_status(dev); |
0428527c IY |
595 | } |
596 | ||
597 | void pcie_cap_slot_write_config(PCIDevice *dev, | |
6bde6aaa | 598 | uint32_t addr, uint32_t val, int len) |
0428527c IY |
599 | { |
600 | uint32_t pos = dev->exp.exp_cap; | |
601 | uint8_t *exp_cap = dev->config + pos; | |
0428527c IY |
602 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
603 | ||
1553d4f1 IY |
604 | if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { |
605 | hotplug_event_clear(dev); | |
606 | } | |
607 | ||
ac0cdda3 MT |
608 | if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { |
609 | return; | |
610 | } | |
611 | ||
ac0cdda3 MT |
612 | if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
613 | PCI_EXP_SLTCTL_EIC)) { | |
614 | sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ | |
615 | pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); | |
616 | PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " | |
617 | "sltsta -> 0x%02"PRIx16"\n", | |
618 | sltsta); | |
619 | } | |
0428527c | 620 | |
554f802d MA |
621 | /* |
622 | * If the slot is polulated, power indicator is off and power | |
623 | * controller is off, it is safe to detach the devices. | |
624 | */ | |
625 | if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && | |
626 | ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { | |
6ba9fe86 C |
627 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); |
628 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
629 | pcie_unplug_device, NULL); | |
554f802d | 630 | |
6ba9fe86 C |
631 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
632 | PCI_EXP_SLTSTA_PDS); | |
2f2b18f6 ZX |
633 | if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { |
634 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, | |
635 | PCI_EXP_LNKSTA_DLLLA); | |
636 | } | |
6ba9fe86 | 637 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
554f802d MA |
638 | PCI_EXP_SLTSTA_PDC); |
639 | } | |
640 | ||
6bde6aaa | 641 | hotplug_event_notify(dev); |
ac0cdda3 MT |
642 | |
643 | /* | |
644 | * 6.7.3.2 Command Completed Events | |
645 | * | |
646 | * Software issues a command to a hot-plug capable Downstream Port by | |
647 | * issuing a write transaction that targets any portion of the Port’s Slot | |
648 | * Control register. A single write to the Slot Control register is | |
649 | * considered to be a single command, even if the write affects more than | |
650 | * one field in the Slot Control register. In response to this transaction, | |
651 | * the Port must carry out the requested actions and then set the | |
652 | * associated status field for the command completed event. */ | |
653 | ||
654 | /* Real hardware might take a while to complete requested command because | |
655 | * physical movement would be involved like locking the electromechanical | |
656 | * lock. However in our case, command is completed instantaneously above, | |
657 | * so send a command completion event right now. | |
658 | */ | |
659 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); | |
0428527c IY |
660 | } |
661 | ||
6bde6aaa MT |
662 | int pcie_cap_slot_post_load(void *opaque, int version_id) |
663 | { | |
664 | PCIDevice *dev = opaque; | |
665 | hotplug_event_update_event_status(dev); | |
666 | return 0; | |
667 | } | |
668 | ||
0428527c IY |
669 | void pcie_cap_slot_push_attention_button(PCIDevice *dev) |
670 | { | |
671 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); | |
672 | } | |
673 | ||
674 | /* root control/capabilities/status. PME isn't emulated for now */ | |
675 | void pcie_cap_root_init(PCIDevice *dev) | |
676 | { | |
677 | pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, | |
678 | PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | | |
679 | PCI_EXP_RTCTL_SEFEE); | |
680 | } | |
681 | ||
682 | void pcie_cap_root_reset(PCIDevice *dev) | |
683 | { | |
684 | pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); | |
685 | } | |
686 | ||
0428527c IY |
687 | /* function level reset(FLR) */ |
688 | void pcie_cap_flr_init(PCIDevice *dev) | |
689 | { | |
690 | pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, | |
691 | PCI_EXP_DEVCAP_FLR); | |
692 | ||
693 | /* Although reading BCR_FLR returns always 0, | |
694 | * the bit is made writable here in order to detect the 1b is written | |
695 | * pcie_cap_flr_write_config() test-and-clear the bit, so | |
696 | * this bit always returns 0 to the guest. | |
697 | */ | |
698 | pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, | |
699 | PCI_EXP_DEVCTL_BCR_FLR); | |
700 | } | |
701 | ||
702 | void pcie_cap_flr_write_config(PCIDevice *dev, | |
703 | uint32_t addr, uint32_t val, int len) | |
704 | { | |
705 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; | |
0ead87c8 IY |
706 | if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { |
707 | /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler | |
708 | so the handler can detect FLR by looking at this bit. */ | |
709 | pci_device_reset(dev); | |
710 | pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); | |
0428527c IY |
711 | } |
712 | } | |
713 | ||
821be9db | 714 | /* Alternative Routing-ID Interpretation (ARI) |
187de915 | 715 | * forwarding support for root and downstream ports |
821be9db KO |
716 | */ |
717 | void pcie_cap_arifwd_init(PCIDevice *dev) | |
0428527c IY |
718 | { |
719 | uint32_t pos = dev->exp.exp_cap; | |
720 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, | |
721 | PCI_EXP_DEVCAP2_ARI); | |
722 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, | |
723 | PCI_EXP_DEVCTL2_ARI); | |
724 | } | |
725 | ||
821be9db | 726 | void pcie_cap_arifwd_reset(PCIDevice *dev) |
0428527c IY |
727 | { |
728 | uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; | |
729 | pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); | |
730 | } | |
731 | ||
821be9db | 732 | bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) |
0428527c IY |
733 | { |
734 | if (!pci_is_express(dev)) { | |
735 | return false; | |
736 | } | |
737 | if (!dev->exp.exp_cap) { | |
738 | return false; | |
739 | } | |
740 | ||
741 | return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & | |
742 | PCI_EXP_DEVCTL2_ARI; | |
743 | } | |
744 | ||
745 | /************************************************************************** | |
4d5e17a5 | 746 | * pci express extended capability list management functions |
0428527c IY |
747 | * uint16_t ext_cap_id (16 bit) |
748 | * uint8_t cap_ver (4 bit) | |
749 | * uint16_t cap_offset (12 bit) | |
750 | * uint16_t ext_cap_size | |
751 | */ | |
752 | ||
4bb571d8 MT |
753 | /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */ |
754 | static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id, | |
0428527c IY |
755 | uint16_t *prev_p) |
756 | { | |
757 | uint16_t prev = 0; | |
758 | uint16_t next; | |
759 | uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); | |
760 | ||
761 | if (!header) { | |
762 | /* no extended capability */ | |
763 | next = 0; | |
764 | goto out; | |
765 | } | |
766 | for (next = PCI_CONFIG_SPACE_SIZE; next; | |
767 | prev = next, next = PCI_EXT_CAP_NEXT(header)) { | |
768 | ||
769 | assert(next >= PCI_CONFIG_SPACE_SIZE); | |
770 | assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); | |
771 | ||
772 | header = pci_get_long(dev->config + next); | |
773 | if (PCI_EXT_CAP_ID(header) == cap_id) { | |
774 | break; | |
775 | } | |
776 | } | |
777 | ||
778 | out: | |
779 | if (prev_p) { | |
780 | *prev_p = prev; | |
781 | } | |
782 | return next; | |
783 | } | |
784 | ||
785 | uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) | |
786 | { | |
787 | return pcie_find_capability_list(dev, cap_id, NULL); | |
788 | } | |
789 | ||
790 | static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) | |
791 | { | |
812d2594 | 792 | uint32_t header = pci_get_long(dev->config + pos); |
0428527c IY |
793 | assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); |
794 | header = (header & ~PCI_EXT_CAP_NEXT_MASK) | | |
795 | ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); | |
796 | pci_set_long(dev->config + pos, header); | |
797 | } | |
798 | ||
799 | /* | |
d62d1eb6 | 800 | * Caller must supply valid (offset, size) such that the range wouldn't |
0428527c IY |
801 | * overlap with other capability or other registers. |
802 | * This function doesn't check it. | |
803 | */ | |
804 | void pcie_add_capability(PCIDevice *dev, | |
805 | uint16_t cap_id, uint8_t cap_ver, | |
806 | uint16_t offset, uint16_t size) | |
807 | { | |
0428527c IY |
808 | assert(offset >= PCI_CONFIG_SPACE_SIZE); |
809 | assert(offset < offset + size); | |
79095ef7 | 810 | assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); |
0428527c IY |
811 | assert(size >= 8); |
812 | assert(pci_is_express(dev)); | |
813 | ||
d4e9b75a | 814 | if (offset != PCI_CONFIG_SPACE_SIZE) { |
0428527c IY |
815 | uint16_t prev; |
816 | ||
4bb571d8 MT |
817 | /* |
818 | * 0xffffffff is not a valid cap id (it's a 16 bit field). use | |
819 | * internally to find the last capability in the linked list. | |
820 | */ | |
d4e9b75a | 821 | pcie_find_capability_list(dev, 0xffffffff, &prev); |
0428527c | 822 | assert(prev >= PCI_CONFIG_SPACE_SIZE); |
0428527c IY |
823 | pcie_ext_cap_set_next(dev, prev, offset); |
824 | } | |
d4e9b75a | 825 | pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); |
0428527c IY |
826 | |
827 | /* Make capability read-only by default */ | |
828 | memset(dev->wmask + offset, 0, size); | |
829 | memset(dev->w1cmask + offset, 0, size); | |
830 | /* Check capability by default */ | |
831 | memset(dev->cmask + offset, 0xFF, size); | |
832 | } | |
833 | ||
727b4866 AW |
834 | /* |
835 | * Sync the PCIe Link Status negotiated speed and width of a bridge with the | |
836 | * downstream device. If downstream device is not present, re-write with the | |
88c86919 AW |
837 | * Link Capability fields. If downstream device reports invalid width or |
838 | * speed, replace with minimum values (LnkSta fields are RsvdZ on VFs but such | |
839 | * values interfere with PCIe native hotplug detecting new devices). Limit | |
840 | * width and speed to bridge capabilities for compatibility. Use config_read | |
841 | * to access the downstream device since it could be an assigned device with | |
842 | * volatile link information. | |
727b4866 AW |
843 | */ |
844 | void pcie_sync_bridge_lnk(PCIDevice *bridge_dev) | |
845 | { | |
846 | PCIBridge *br = PCI_BRIDGE(bridge_dev); | |
847 | PCIBus *bus = pci_bridge_get_sec_bus(br); | |
848 | PCIDevice *target = bus->devices[0]; | |
849 | uint8_t *exp_cap = bridge_dev->config + bridge_dev->exp.exp_cap; | |
850 | uint16_t lnksta, lnkcap = pci_get_word(exp_cap + PCI_EXP_LNKCAP); | |
851 | ||
852 | if (!target || !target->exp.exp_cap) { | |
853 | lnksta = lnkcap; | |
854 | } else { | |
855 | lnksta = target->config_read(target, | |
856 | target->exp.exp_cap + PCI_EXP_LNKSTA, | |
857 | sizeof(lnksta)); | |
858 | ||
859 | if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) { | |
860 | lnksta &= ~PCI_EXP_LNKSTA_NLW; | |
861 | lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW; | |
88c86919 AW |
862 | } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) { |
863 | lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1); | |
727b4866 AW |
864 | } |
865 | ||
866 | if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) { | |
867 | lnksta &= ~PCI_EXP_LNKSTA_CLS; | |
868 | lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS; | |
88c86919 AW |
869 | } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) { |
870 | lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT); | |
727b4866 AW |
871 | } |
872 | } | |
873 | ||
874 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, | |
875 | PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW); | |
876 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta & | |
877 | (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW)); | |
878 | } | |
879 | ||
0428527c IY |
880 | /************************************************************************** |
881 | * pci express extended capability helper functions | |
882 | */ | |
883 | ||
884 | /* ARI */ | |
885 | void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) | |
886 | { | |
887 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, | |
888 | offset, PCI_ARI_SIZEOF); | |
ec70b46b | 889 | pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); |
0428527c | 890 | } |
b56b9285 DF |
891 | |
892 | void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num) | |
893 | { | |
894 | static const int pci_dsn_ver = 1; | |
895 | static const int pci_dsn_cap = 4; | |
896 | ||
897 | pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset, | |
898 | PCI_EXT_CAP_DSN_SIZEOF); | |
899 | pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); | |
900 | } | |
615c4ed2 JW |
901 | |
902 | void pcie_ats_init(PCIDevice *dev, uint16_t offset) | |
903 | { | |
904 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, | |
905 | offset, PCI_EXT_CAP_ATS_SIZEOF); | |
906 | ||
907 | dev->exp.ats_cap = offset; | |
908 | ||
909 | /* Invalidate Queue Depth 0, Page Aligned Request 0 */ | |
910 | pci_set_word(dev->config + offset + PCI_ATS_CAP, 0); | |
911 | /* STU 0, Disabled by default */ | |
912 | pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); | |
913 | ||
914 | pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); | |
915 | } | |
db891a9b KO |
916 | |
917 | /* ACS (Access Control Services) */ | |
918 | void pcie_acs_init(PCIDevice *dev, uint16_t offset) | |
919 | { | |
920 | bool is_downstream = pci_is_express_downstream_port(dev); | |
921 | uint16_t cap_bits = 0; | |
922 | ||
923 | /* For endpoints, only multifunction devs may have an ACS capability: */ | |
924 | assert(is_downstream || | |
925 | (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || | |
926 | PCI_FUNC(dev->devfn)); | |
927 | ||
928 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, | |
929 | PCI_ACS_SIZEOF); | |
930 | dev->exp.acs_cap = offset; | |
931 | ||
932 | if (is_downstream) { | |
933 | /* | |
934 | * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with | |
935 | * caveats on the latter four that we ignore for simplicity). | |
936 | * Endpoints may also implement a subset of ACS capabilities, | |
937 | * but these are optional if the endpoint does not support | |
938 | * peer-to-peer between functions and thus omitted here. | |
939 | */ | |
940 | cap_bits = PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | | |
941 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; | |
942 | } | |
943 | ||
944 | pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); | |
945 | pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); | |
946 | } | |
947 | ||
948 | void pcie_acs_reset(PCIDevice *dev) | |
949 | { | |
950 | if (dev->exp.acs_cap) { | |
951 | pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); | |
952 | } | |
953 | } |