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0428527c IY |
1 | /* |
2 | * pcie.c | |
3 | * | |
4 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
5 | * VA Linux Systems Japan K.K. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
97d5408f | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
d8dfad9c | 23 | #include "qemu-common.h" |
c759b24f MT |
24 | #include "hw/pci/pci_bridge.h" |
25 | #include "hw/pci/pcie.h" | |
26 | #include "hw/pci/msix.h" | |
27 | #include "hw/pci/msi.h" | |
06aac7bd | 28 | #include "hw/pci/pci_bus.h" |
c759b24f | 29 | #include "hw/pci/pcie_regs.h" |
1de7afc9 | 30 | #include "qemu/range.h" |
0428527c IY |
31 | |
32 | //#define DEBUG_PCIE | |
33 | #ifdef DEBUG_PCIE | |
34 | # define PCIE_DPRINTF(fmt, ...) \ | |
35 | fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) | |
36 | #else | |
37 | # define PCIE_DPRINTF(fmt, ...) do {} while (0) | |
38 | #endif | |
39 | #define PCIE_DEV_PRINTF(dev, fmt, ...) \ | |
40 | PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) | |
41 | ||
42 | ||
43 | /*************************************************************************** | |
44 | * pci express capability helper functions | |
45 | */ | |
46 | int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) | |
47 | { | |
48 | int pos; | |
49 | uint8_t *exp_cap; | |
50 | ||
51 | assert(pci_is_express(dev)); | |
52 | ||
53 | pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, | |
54 | PCI_EXP_VER2_SIZEOF); | |
55 | if (pos < 0) { | |
56 | return pos; | |
57 | } | |
58 | dev->exp.exp_cap = pos; | |
59 | exp_cap = dev->config + pos; | |
60 | ||
61 | /* capability register | |
62 | interrupt message number defaults to 0 */ | |
63 | pci_set_word(exp_cap + PCI_EXP_FLAGS, | |
64 | ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) | | |
65 | PCI_EXP_FLAGS_VER2); | |
66 | ||
67 | /* device capability register | |
68 | * table 7-12: | |
69 | * roll based error reporting bit must be set by all | |
70 | * Functions conforming to the ECN, PCI Express Base | |
71 | * Specification, Revision 1.1., or subsequent PCI Express Base | |
72 | * Specification revisions. | |
73 | */ | |
74 | pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); | |
75 | ||
76 | pci_set_long(exp_cap + PCI_EXP_LNKCAP, | |
77 | (port << PCI_EXP_LNKCAP_PN_SHIFT) | | |
78 | PCI_EXP_LNKCAP_ASPMS_0S | | |
79 | PCI_EXP_LNK_MLW_1 | | |
80 | PCI_EXP_LNK_LS_25); | |
81 | ||
82 | pci_set_word(exp_cap + PCI_EXP_LNKSTA, | |
b2101eae | 83 | PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25 |PCI_EXP_LNKSTA_DLLLA); |
0428527c IY |
84 | |
85 | pci_set_long(exp_cap + PCI_EXP_DEVCAP2, | |
86 | PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); | |
87 | ||
30b04f87 | 88 | pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); |
0428527c IY |
89 | return pos; |
90 | } | |
91 | ||
6214e73c AW |
92 | int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) |
93 | { | |
94 | uint8_t type = PCI_EXP_TYPE_ENDPOINT; | |
95 | ||
96 | /* | |
97 | * Windows guests will report Code 10, device cannot start, if | |
98 | * a regular Endpoint type is exposed on a root complex. These | |
99 | * should instead be Root Complex Integrated Endpoints. | |
100 | */ | |
101 | if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) { | |
102 | type = PCI_EXP_TYPE_RC_END; | |
103 | } | |
104 | ||
105 | return pcie_cap_init(dev, offset, type, 0); | |
106 | } | |
107 | ||
0428527c IY |
108 | void pcie_cap_exit(PCIDevice *dev) |
109 | { | |
110 | pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF); | |
111 | } | |
112 | ||
113 | uint8_t pcie_cap_get_type(const PCIDevice *dev) | |
114 | { | |
115 | uint32_t pos = dev->exp.exp_cap; | |
116 | assert(pos > 0); | |
117 | return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) & | |
118 | PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT; | |
119 | } | |
120 | ||
121 | /* MSI/MSI-X */ | |
122 | /* pci express interrupt message number */ | |
123 | /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */ | |
124 | void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector) | |
125 | { | |
126 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; | |
127 | assert(vector < 32); | |
128 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ); | |
129 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, | |
130 | vector << PCI_EXP_FLAGS_IRQ_SHIFT); | |
131 | } | |
132 | ||
133 | uint8_t pcie_cap_flags_get_vector(PCIDevice *dev) | |
134 | { | |
135 | return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) & | |
136 | PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT; | |
137 | } | |
138 | ||
139 | void pcie_cap_deverr_init(PCIDevice *dev) | |
140 | { | |
141 | uint32_t pos = dev->exp.exp_cap; | |
142 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP, | |
143 | PCI_EXP_DEVCAP_RBER); | |
144 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, | |
145 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | | |
146 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); | |
147 | pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA, | |
148 | PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED | | |
8e815eee | 149 | PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD); |
0428527c IY |
150 | } |
151 | ||
152 | void pcie_cap_deverr_reset(PCIDevice *dev) | |
153 | { | |
154 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; | |
155 | pci_long_test_and_clear_mask(devctl, | |
156 | PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | | |
157 | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); | |
158 | } | |
159 | ||
6bde6aaa MT |
160 | static void hotplug_event_update_event_status(PCIDevice *dev) |
161 | { | |
162 | uint32_t pos = dev->exp.exp_cap; | |
163 | uint8_t *exp_cap = dev->config + pos; | |
164 | uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); | |
165 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); | |
166 | ||
167 | dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && | |
168 | (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); | |
169 | } | |
170 | ||
171 | static void hotplug_event_notify(PCIDevice *dev) | |
172 | { | |
173 | bool prev = dev->exp.hpev_notified; | |
174 | ||
175 | hotplug_event_update_event_status(dev); | |
176 | ||
177 | if (prev == dev->exp.hpev_notified) { | |
178 | return; | |
179 | } | |
180 | ||
181 | /* Note: the logic above does not take into account whether interrupts | |
182 | * are masked. The result is that interrupt will be sent when it is | |
183 | * subsequently unmasked. This appears to be legal: Section 6.7.3.4: | |
184 | * The Port may optionally send an MSI when there are hot-plug events that | |
185 | * occur while interrupt generation is disabled, and interrupt generation is | |
186 | * subsequently enabled. */ | |
4a9dd665 MT |
187 | if (msix_enabled(dev)) { |
188 | msix_notify(dev, pcie_cap_flags_get_vector(dev)); | |
189 | } else if (msi_enabled(dev)) { | |
190 | msi_notify(dev, pcie_cap_flags_get_vector(dev)); | |
191 | } else { | |
5a03e708 | 192 | pci_set_irq(dev, dev->exp.hpev_notified); |
6bde6aaa MT |
193 | } |
194 | } | |
195 | ||
1553d4f1 IY |
196 | static void hotplug_event_clear(PCIDevice *dev) |
197 | { | |
198 | hotplug_event_update_event_status(dev); | |
199 | if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) { | |
5a03e708 | 200 | pci_irq_deassert(dev); |
1553d4f1 IY |
201 | } |
202 | } | |
203 | ||
0428527c | 204 | /* |
a1c7273b | 205 | * A PCI Express Hot-Plug Event has occurred, so update slot status register |
0428527c IY |
206 | * and notify OS of the event if necessary. |
207 | * | |
208 | * 6.7.3 PCI Express Hot-Plug Events | |
209 | * 6.7.3.4 Software Notification of Hot-Plug Events | |
210 | */ | |
211 | static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) | |
212 | { | |
6bde6aaa MT |
213 | /* Minor optimization: if nothing changed - no event is needed. */ |
214 | if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + | |
215 | PCI_EXP_SLTSTA, event)) { | |
0428527c IY |
216 | return; |
217 | } | |
6bde6aaa | 218 | hotplug_event_notify(dev); |
0428527c IY |
219 | } |
220 | ||
a66e657e IM |
221 | static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev, |
222 | DeviceState *dev, | |
223 | uint8_t **exp_cap, Error **errp) | |
0428527c | 224 | { |
a66e657e IM |
225 | *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap; |
226 | uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA); | |
0428527c | 227 | |
e4bcd27c | 228 | PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta); |
0428527c IY |
229 | if (sltsta & PCI_EXP_SLTSTA_EIS) { |
230 | /* the slot is electromechanically locked. | |
231 | * This error is propagated up to qdev and then to HMP/QMP. | |
232 | */ | |
6c150fbd | 233 | error_setg_errno(errp, EBUSY, "slot is electromechanically locked"); |
0428527c | 234 | } |
a66e657e IM |
235 | } |
236 | ||
237 | void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, | |
238 | Error **errp) | |
239 | { | |
240 | uint8_t *exp_cap; | |
6e1f0a55 | 241 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
a66e657e IM |
242 | |
243 | pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); | |
0428527c | 244 | |
a66e657e IM |
245 | /* Don't send event when device is enabled during qemu machine creation: |
246 | * it is present on boot, no hotplug event is necessary. We do send an | |
247 | * event when the device is disabled later. */ | |
248 | if (!dev->hotplugged) { | |
0428527c IY |
249 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, |
250 | PCI_EXP_SLTSTA_PDS); | |
a66e657e | 251 | return; |
0428527c | 252 | } |
a66e657e | 253 | |
3f1e1478 C |
254 | /* To enable multifunction hot-plug, we just ensure the function |
255 | * 0 added last. When function 0 is added, we set the sltsta and | |
256 | * inform OS via event notification. | |
6e1f0a55 | 257 | */ |
3f1e1478 C |
258 | if (pci_get_function_0(pci_dev)) { |
259 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, | |
260 | PCI_EXP_SLTSTA_PDS); | |
261 | pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), | |
262 | PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); | |
263 | } | |
a66e657e IM |
264 | } |
265 | ||
0d1c7d88 C |
266 | static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque) |
267 | { | |
268 | object_unparent(OBJECT(dev)); | |
269 | } | |
270 | ||
14d5a28f IM |
271 | void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev, |
272 | DeviceState *dev, Error **errp) | |
a66e657e IM |
273 | { |
274 | uint8_t *exp_cap; | |
0d1c7d88 C |
275 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
276 | PCIBus *bus = pci_dev->bus; | |
a66e657e IM |
277 | |
278 | pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp); | |
279 | ||
0d1c7d88 C |
280 | /* In case user cancel the operation of multi-function hot-add, |
281 | * remove the function that is unexposed to guest individually, | |
282 | * without interaction with guest. | |
283 | */ | |
284 | if (pci_dev->devfn && | |
285 | !bus->devices[0]) { | |
286 | pcie_unplug_device(bus, pci_dev, NULL); | |
287 | ||
288 | return; | |
289 | } | |
290 | ||
554f802d | 291 | pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); |
0428527c IY |
292 | } |
293 | ||
294 | /* pci express slot for pci express root/downstream port | |
295 | PCI express capability slot registers */ | |
296 | void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) | |
297 | { | |
298 | uint32_t pos = dev->exp.exp_cap; | |
299 | ||
300 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, | |
301 | PCI_EXP_FLAGS_SLOT); | |
302 | ||
303 | pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
304 | ~PCI_EXP_SLTCAP_PSN); | |
305 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
306 | (slot << PCI_EXP_SLTCAP_PSN_SHIFT) | | |
307 | PCI_EXP_SLTCAP_EIP | | |
308 | PCI_EXP_SLTCAP_HPS | | |
309 | PCI_EXP_SLTCAP_HPC | | |
310 | PCI_EXP_SLTCAP_PIP | | |
311 | PCI_EXP_SLTCAP_AIP | | |
312 | PCI_EXP_SLTCAP_ABP); | |
313 | ||
f23b6bdc MA |
314 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
315 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, | |
316 | PCI_EXP_SLTCAP_PCP); | |
317 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, | |
318 | PCI_EXP_SLTCTL_PCC); | |
319 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
320 | PCI_EXP_SLTCTL_PCC); | |
321 | } | |
322 | ||
0428527c IY |
323 | pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, |
324 | PCI_EXP_SLTCTL_PIC | | |
325 | PCI_EXP_SLTCTL_AIC); | |
326 | pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL, | |
327 | PCI_EXP_SLTCTL_PIC_OFF | | |
328 | PCI_EXP_SLTCTL_AIC_OFF); | |
329 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
330 | PCI_EXP_SLTCTL_PIC | | |
331 | PCI_EXP_SLTCTL_AIC | | |
332 | PCI_EXP_SLTCTL_HPIE | | |
333 | PCI_EXP_SLTCTL_CCIE | | |
334 | PCI_EXP_SLTCTL_PDCE | | |
335 | PCI_EXP_SLTCTL_ABPE); | |
336 | /* Although reading PCI_EXP_SLTCTL_EIC returns always 0, | |
337 | * make the bit writable here in order to detect 1b is written. | |
338 | * pcie_cap_slot_write_config() test-and-clear the bit, so | |
339 | * this bit always returns 0 to the guest. | |
340 | */ | |
341 | pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, | |
342 | PCI_EXP_SLTCTL_EIC); | |
343 | ||
344 | pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, | |
345 | PCI_EXP_HP_EV_SUPPORTED); | |
346 | ||
6bde6aaa MT |
347 | dev->exp.hpev_notified = false; |
348 | ||
a66e657e IM |
349 | qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), |
350 | DEVICE(dev), NULL); | |
0428527c IY |
351 | } |
352 | ||
353 | void pcie_cap_slot_reset(PCIDevice *dev) | |
354 | { | |
355 | uint8_t *exp_cap = dev->config + dev->exp.exp_cap; | |
f23b6bdc MA |
356 | uint8_t port_type = pcie_cap_get_type(dev); |
357 | ||
358 | assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || | |
359 | port_type == PCI_EXP_TYPE_ROOT_PORT); | |
0428527c IY |
360 | |
361 | PCIE_DEV_PRINTF(dev, "reset\n"); | |
362 | ||
363 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, | |
364 | PCI_EXP_SLTCTL_EIC | | |
365 | PCI_EXP_SLTCTL_PIC | | |
366 | PCI_EXP_SLTCTL_AIC | | |
367 | PCI_EXP_SLTCTL_HPIE | | |
368 | PCI_EXP_SLTCTL_CCIE | | |
369 | PCI_EXP_SLTCTL_PDCE | | |
370 | PCI_EXP_SLTCTL_ABPE); | |
371 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, | |
0428527c IY |
372 | PCI_EXP_SLTCTL_AIC_OFF); |
373 | ||
f23b6bdc | 374 | if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { |
f23b6bdc | 375 | /* Downstream ports enforce device number 0. */ |
20de98af MT |
376 | bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0]; |
377 | uint16_t pic; | |
f23b6bdc MA |
378 | |
379 | if (populated) { | |
380 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, | |
381 | PCI_EXP_SLTCTL_PCC); | |
382 | } else { | |
383 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, | |
384 | PCI_EXP_SLTCTL_PCC); | |
385 | } | |
386 | ||
387 | pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; | |
388 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); | |
20de98af | 389 | } |
f23b6bdc | 390 | |
0428527c IY |
391 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
392 | PCI_EXP_SLTSTA_EIS |/* on reset, | |
393 | the lock is released */ | |
394 | PCI_EXP_SLTSTA_CC | | |
395 | PCI_EXP_SLTSTA_PDC | | |
396 | PCI_EXP_SLTSTA_ABP); | |
6bde6aaa | 397 | |
804b2071 | 398 | hotplug_event_update_event_status(dev); |
0428527c IY |
399 | } |
400 | ||
401 | void pcie_cap_slot_write_config(PCIDevice *dev, | |
6bde6aaa | 402 | uint32_t addr, uint32_t val, int len) |
0428527c IY |
403 | { |
404 | uint32_t pos = dev->exp.exp_cap; | |
405 | uint8_t *exp_cap = dev->config + pos; | |
0428527c IY |
406 | uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
407 | ||
1553d4f1 IY |
408 | if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { |
409 | hotplug_event_clear(dev); | |
410 | } | |
411 | ||
ac0cdda3 MT |
412 | if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) { |
413 | return; | |
414 | } | |
415 | ||
ac0cdda3 MT |
416 | if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
417 | PCI_EXP_SLTCTL_EIC)) { | |
418 | sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ | |
419 | pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta); | |
420 | PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: " | |
421 | "sltsta -> 0x%02"PRIx16"\n", | |
422 | sltsta); | |
423 | } | |
0428527c | 424 | |
554f802d MA |
425 | /* |
426 | * If the slot is polulated, power indicator is off and power | |
427 | * controller is off, it is safe to detach the devices. | |
428 | */ | |
429 | if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) && | |
430 | ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) { | |
6ba9fe86 C |
431 | PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); |
432 | pci_for_each_device(sec_bus, pci_bus_num(sec_bus), | |
433 | pcie_unplug_device, NULL); | |
554f802d | 434 | |
6ba9fe86 C |
435 | pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, |
436 | PCI_EXP_SLTSTA_PDS); | |
437 | pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, | |
554f802d MA |
438 | PCI_EXP_SLTSTA_PDC); |
439 | } | |
440 | ||
6bde6aaa | 441 | hotplug_event_notify(dev); |
ac0cdda3 MT |
442 | |
443 | /* | |
444 | * 6.7.3.2 Command Completed Events | |
445 | * | |
446 | * Software issues a command to a hot-plug capable Downstream Port by | |
447 | * issuing a write transaction that targets any portion of the Port’s Slot | |
448 | * Control register. A single write to the Slot Control register is | |
449 | * considered to be a single command, even if the write affects more than | |
450 | * one field in the Slot Control register. In response to this transaction, | |
451 | * the Port must carry out the requested actions and then set the | |
452 | * associated status field for the command completed event. */ | |
453 | ||
454 | /* Real hardware might take a while to complete requested command because | |
455 | * physical movement would be involved like locking the electromechanical | |
456 | * lock. However in our case, command is completed instantaneously above, | |
457 | * so send a command completion event right now. | |
458 | */ | |
459 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); | |
0428527c IY |
460 | } |
461 | ||
6bde6aaa MT |
462 | int pcie_cap_slot_post_load(void *opaque, int version_id) |
463 | { | |
464 | PCIDevice *dev = opaque; | |
465 | hotplug_event_update_event_status(dev); | |
466 | return 0; | |
467 | } | |
468 | ||
0428527c IY |
469 | void pcie_cap_slot_push_attention_button(PCIDevice *dev) |
470 | { | |
471 | pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); | |
472 | } | |
473 | ||
474 | /* root control/capabilities/status. PME isn't emulated for now */ | |
475 | void pcie_cap_root_init(PCIDevice *dev) | |
476 | { | |
477 | pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, | |
478 | PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | | |
479 | PCI_EXP_RTCTL_SEFEE); | |
480 | } | |
481 | ||
482 | void pcie_cap_root_reset(PCIDevice *dev) | |
483 | { | |
484 | pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); | |
485 | } | |
486 | ||
0428527c IY |
487 | /* function level reset(FLR) */ |
488 | void pcie_cap_flr_init(PCIDevice *dev) | |
489 | { | |
490 | pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP, | |
491 | PCI_EXP_DEVCAP_FLR); | |
492 | ||
493 | /* Although reading BCR_FLR returns always 0, | |
494 | * the bit is made writable here in order to detect the 1b is written | |
495 | * pcie_cap_flr_write_config() test-and-clear the bit, so | |
496 | * this bit always returns 0 to the guest. | |
497 | */ | |
498 | pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, | |
499 | PCI_EXP_DEVCTL_BCR_FLR); | |
500 | } | |
501 | ||
502 | void pcie_cap_flr_write_config(PCIDevice *dev, | |
503 | uint32_t addr, uint32_t val, int len) | |
504 | { | |
505 | uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; | |
0ead87c8 IY |
506 | if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { |
507 | /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler | |
508 | so the handler can detect FLR by looking at this bit. */ | |
509 | pci_device_reset(dev); | |
510 | pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); | |
0428527c IY |
511 | } |
512 | } | |
513 | ||
821be9db | 514 | /* Alternative Routing-ID Interpretation (ARI) |
187de915 | 515 | * forwarding support for root and downstream ports |
821be9db KO |
516 | */ |
517 | void pcie_cap_arifwd_init(PCIDevice *dev) | |
0428527c IY |
518 | { |
519 | uint32_t pos = dev->exp.exp_cap; | |
520 | pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, | |
521 | PCI_EXP_DEVCAP2_ARI); | |
522 | pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, | |
523 | PCI_EXP_DEVCTL2_ARI); | |
524 | } | |
525 | ||
821be9db | 526 | void pcie_cap_arifwd_reset(PCIDevice *dev) |
0428527c IY |
527 | { |
528 | uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2; | |
529 | pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI); | |
530 | } | |
531 | ||
821be9db | 532 | bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev) |
0428527c IY |
533 | { |
534 | if (!pci_is_express(dev)) { | |
535 | return false; | |
536 | } | |
537 | if (!dev->exp.exp_cap) { | |
538 | return false; | |
539 | } | |
540 | ||
541 | return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & | |
542 | PCI_EXP_DEVCTL2_ARI; | |
543 | } | |
544 | ||
545 | /************************************************************************** | |
4d5e17a5 | 546 | * pci express extended capability list management functions |
0428527c IY |
547 | * uint16_t ext_cap_id (16 bit) |
548 | * uint8_t cap_ver (4 bit) | |
549 | * uint16_t cap_offset (12 bit) | |
550 | * uint16_t ext_cap_size | |
551 | */ | |
552 | ||
553 | static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id, | |
554 | uint16_t *prev_p) | |
555 | { | |
556 | uint16_t prev = 0; | |
557 | uint16_t next; | |
558 | uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); | |
559 | ||
560 | if (!header) { | |
561 | /* no extended capability */ | |
562 | next = 0; | |
563 | goto out; | |
564 | } | |
565 | for (next = PCI_CONFIG_SPACE_SIZE; next; | |
566 | prev = next, next = PCI_EXT_CAP_NEXT(header)) { | |
567 | ||
568 | assert(next >= PCI_CONFIG_SPACE_SIZE); | |
569 | assert(next <= PCIE_CONFIG_SPACE_SIZE - 8); | |
570 | ||
571 | header = pci_get_long(dev->config + next); | |
572 | if (PCI_EXT_CAP_ID(header) == cap_id) { | |
573 | break; | |
574 | } | |
575 | } | |
576 | ||
577 | out: | |
578 | if (prev_p) { | |
579 | *prev_p = prev; | |
580 | } | |
581 | return next; | |
582 | } | |
583 | ||
584 | uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id) | |
585 | { | |
586 | return pcie_find_capability_list(dev, cap_id, NULL); | |
587 | } | |
588 | ||
589 | static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next) | |
590 | { | |
812d2594 | 591 | uint32_t header = pci_get_long(dev->config + pos); |
0428527c IY |
592 | assert(!(next & (PCI_EXT_CAP_ALIGN - 1))); |
593 | header = (header & ~PCI_EXT_CAP_NEXT_MASK) | | |
594 | ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK); | |
595 | pci_set_long(dev->config + pos, header); | |
596 | } | |
597 | ||
598 | /* | |
599 | * caller must supply valid (offset, size) * such that the range shouldn't | |
600 | * overlap with other capability or other registers. | |
601 | * This function doesn't check it. | |
602 | */ | |
603 | void pcie_add_capability(PCIDevice *dev, | |
604 | uint16_t cap_id, uint8_t cap_ver, | |
605 | uint16_t offset, uint16_t size) | |
606 | { | |
607 | uint32_t header; | |
608 | uint16_t next; | |
609 | ||
610 | assert(offset >= PCI_CONFIG_SPACE_SIZE); | |
611 | assert(offset < offset + size); | |
79095ef7 | 612 | assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); |
0428527c IY |
613 | assert(size >= 8); |
614 | assert(pci_is_express(dev)); | |
615 | ||
616 | if (offset == PCI_CONFIG_SPACE_SIZE) { | |
617 | header = pci_get_long(dev->config + offset); | |
618 | next = PCI_EXT_CAP_NEXT(header); | |
619 | } else { | |
620 | uint16_t prev; | |
621 | ||
622 | /* 0 is reserved cap id. use internally to find the last capability | |
623 | in the linked list */ | |
624 | next = pcie_find_capability_list(dev, 0, &prev); | |
625 | ||
626 | assert(prev >= PCI_CONFIG_SPACE_SIZE); | |
627 | assert(next == 0); | |
628 | pcie_ext_cap_set_next(dev, prev, offset); | |
629 | } | |
630 | pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); | |
631 | ||
632 | /* Make capability read-only by default */ | |
633 | memset(dev->wmask + offset, 0, size); | |
634 | memset(dev->w1cmask + offset, 0, size); | |
635 | /* Check capability by default */ | |
636 | memset(dev->cmask + offset, 0xFF, size); | |
637 | } | |
638 | ||
639 | /************************************************************************** | |
640 | * pci express extended capability helper functions | |
641 | */ | |
642 | ||
643 | /* ARI */ | |
644 | void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) | |
645 | { | |
646 | pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, | |
647 | offset, PCI_ARI_SIZEOF); | |
ec70b46b | 648 | pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); |
0428527c | 649 | } |