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Commit | Line | Data |
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8135aeed IY |
1 | /* |
2 | * ioh3420.c | |
3 | * Intel X58 north bridge IOH | |
4 | * PCI Express root port device id 3420 | |
5 | * | |
6 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
97d5408f | 23 | #include "qemu/osdep.h" |
83c9f4ca PB |
24 | #include "hw/pci/pci_ids.h" |
25 | #include "hw/pci/msi.h" | |
26 | #include "hw/pci/pcie.h" | |
47b43a1f | 27 | #include "ioh3420.h" |
1108b2f8 | 28 | #include "qapi/error.h" |
8135aeed IY |
29 | |
30 | #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ | |
31 | #define PCI_DEVICE_ID_IOH_REV 0x2 | |
32 | #define IOH_EP_SSVID_OFFSET 0x40 | |
33 | #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL | |
34 | #define IOH_EP_SSVID_SSID 0 | |
35 | #define IOH_EP_MSI_OFFSET 0x60 | |
36 | #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT | |
37 | #define IOH_EP_MSI_NR_VECTOR 2 | |
38 | #define IOH_EP_EXP_OFFSET 0x90 | |
39 | #define IOH_EP_AER_OFFSET 0x100 | |
40 | ||
61620c2f IY |
41 | /* |
42 | * If two MSI vector are allocated, Advanced Error Interrupt Message Number | |
43 | * is 1. otherwise 0. | |
44 | * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. | |
45 | */ | |
46 | static uint8_t ioh3420_aer_vector(const PCIDevice *d) | |
47 | { | |
48 | switch (msi_nr_vectors_allocated(d)) { | |
49 | case 1: | |
50 | return 0; | |
51 | case 2: | |
52 | return 1; | |
53 | case 4: | |
54 | case 8: | |
55 | case 16: | |
56 | case 32: | |
57 | default: | |
58 | break; | |
59 | } | |
60 | abort(); | |
61 | return 0; | |
62 | } | |
63 | ||
64 | static void ioh3420_aer_vector_update(PCIDevice *d) | |
65 | { | |
66 | pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); | |
67 | } | |
68 | ||
8135aeed IY |
69 | static void ioh3420_write_config(PCIDevice *d, |
70 | uint32_t address, uint32_t val, int len) | |
71 | { | |
61620c2f IY |
72 | uint32_t root_cmd = |
73 | pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); | |
74 | ||
8135aeed | 75 | pci_bridge_write_config(d, address, val, len); |
61620c2f | 76 | ioh3420_aer_vector_update(d); |
6bde6aaa | 77 | pcie_cap_slot_write_config(d, address, val, len); |
61620c2f IY |
78 | pcie_aer_write_config(d, address, val, len); |
79 | pcie_aer_root_write_config(d, address, val, len, root_cmd); | |
8135aeed IY |
80 | } |
81 | ||
82 | static void ioh3420_reset(DeviceState *qdev) | |
83 | { | |
40021f08 | 84 | PCIDevice *d = PCI_DEVICE(qdev); |
cbd2d434 | 85 | |
61620c2f | 86 | ioh3420_aer_vector_update(d); |
8135aeed IY |
87 | pcie_cap_root_reset(d); |
88 | pcie_cap_deverr_reset(d); | |
89 | pcie_cap_slot_reset(d); | |
a74b8702 | 90 | pcie_cap_arifwd_reset(d); |
61620c2f | 91 | pcie_aer_root_reset(d); |
8135aeed IY |
92 | pci_bridge_reset(qdev); |
93 | pci_bridge_disable_base_limit(d); | |
8135aeed IY |
94 | } |
95 | ||
96 | static int ioh3420_initfn(PCIDevice *d) | |
97 | { | |
bcb75750 AF |
98 | PCIEPort *p = PCIE_PORT(d); |
99 | PCIESlot *s = PCIE_SLOT(d); | |
8135aeed | 100 | int rc; |
1108b2f8 | 101 | Error *err = NULL; |
8135aeed | 102 | |
2c533c54 | 103 | pci_config_set_interrupt_pin(d->config, 1); |
9cfaa007 | 104 | pci_bridge_initfn(d, TYPE_PCIE_BUS); |
8135aeed IY |
105 | pcie_port_init_reg(d); |
106 | ||
8135aeed IY |
107 | rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, |
108 | IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); | |
109 | if (rc < 0) { | |
61620c2f | 110 | goto err_bridge; |
8135aeed | 111 | } |
52ea63de | 112 | |
8135aeed IY |
113 | rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, |
114 | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, | |
1108b2f8 | 115 | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err); |
8135aeed | 116 | if (rc < 0) { |
1108b2f8 C |
117 | assert(rc == -ENOTSUP); |
118 | error_report_err(err); | |
61620c2f | 119 | goto err_bridge; |
8135aeed | 120 | } |
52ea63de | 121 | |
8135aeed IY |
122 | rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); |
123 | if (rc < 0) { | |
61620c2f | 124 | goto err_msi; |
8135aeed | 125 | } |
821be9db | 126 | |
a74b8702 | 127 | pcie_cap_arifwd_init(d); |
8135aeed IY |
128 | pcie_cap_deverr_init(d); |
129 | pcie_cap_slot_init(d, s->slot); | |
52ea63de C |
130 | pcie_cap_root_init(d); |
131 | ||
8135aeed IY |
132 | pcie_chassis_create(s->chassis); |
133 | rc = pcie_chassis_add_slot(s); | |
134 | if (rc < 0) { | |
61620c2f | 135 | goto err_pcie_cap; |
8135aeed | 136 | } |
52ea63de | 137 | |
8d86ada2 | 138 | rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); |
61620c2f IY |
139 | if (rc < 0) { |
140 | goto err; | |
141 | } | |
142 | pcie_aer_root_init(d); | |
143 | ioh3420_aer_vector_update(d); | |
52ea63de | 144 | |
8135aeed | 145 | return 0; |
61620c2f IY |
146 | |
147 | err: | |
148 | pcie_chassis_del_slot(s); | |
149 | err_pcie_cap: | |
150 | pcie_cap_exit(d); | |
151 | err_msi: | |
152 | msi_uninit(d); | |
153 | err_bridge: | |
f90c2bcd | 154 | pci_bridge_exitfn(d); |
61620c2f | 155 | return rc; |
8135aeed IY |
156 | } |
157 | ||
f90c2bcd | 158 | static void ioh3420_exitfn(PCIDevice *d) |
8135aeed | 159 | { |
bcb75750 | 160 | PCIESlot *s = PCIE_SLOT(d); |
61620c2f IY |
161 | |
162 | pcie_aer_exit(d); | |
163 | pcie_chassis_del_slot(s); | |
8135aeed | 164 | pcie_cap_exit(d); |
61620c2f | 165 | msi_uninit(d); |
f90c2bcd | 166 | pci_bridge_exitfn(d); |
8135aeed IY |
167 | } |
168 | ||
f23b6bdc MA |
169 | static Property ioh3420_props[] = { |
170 | DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, | |
171 | QEMU_PCIE_SLTCAP_PCP_BITNR, true), | |
172 | DEFINE_PROP_END_OF_LIST() | |
173 | }; | |
174 | ||
8135aeed IY |
175 | static const VMStateDescription vmstate_ioh3420 = { |
176 | .name = "ioh-3240-express-root-port", | |
177 | .version_id = 1, | |
178 | .minimum_version_id = 1, | |
6bde6aaa | 179 | .post_load = pcie_cap_slot_post_load, |
8135aeed | 180 | .fields = (VMStateField[]) { |
bcb75750 AF |
181 | VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), |
182 | VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, | |
183 | PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), | |
8135aeed IY |
184 | VMSTATE_END_OF_LIST() |
185 | } | |
186 | }; | |
187 | ||
40021f08 AL |
188 | static void ioh3420_class_init(ObjectClass *klass, void *data) |
189 | { | |
39bffca2 | 190 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
191 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
192 | ||
193 | k->is_express = 1; | |
194 | k->is_bridge = 1; | |
195 | k->config_write = ioh3420_write_config; | |
196 | k->init = ioh3420_initfn; | |
197 | k->exit = ioh3420_exitfn; | |
198 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
199 | k->device_id = PCI_DEVICE_ID_IOH_EPORT; | |
200 | k->revision = PCI_DEVICE_ID_IOH_REV; | |
125ee0ed | 201 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 AL |
202 | dc->desc = "Intel IOH device id 3420 PCIE Root Port"; |
203 | dc->reset = ioh3420_reset; | |
204 | dc->vmsd = &vmstate_ioh3420; | |
f23b6bdc | 205 | dc->props = ioh3420_props; |
40021f08 AL |
206 | } |
207 | ||
8c43a6f0 | 208 | static const TypeInfo ioh3420_info = { |
39bffca2 | 209 | .name = "ioh3420", |
bcb75750 | 210 | .parent = TYPE_PCIE_SLOT, |
39bffca2 | 211 | .class_init = ioh3420_class_init, |
8135aeed IY |
212 | }; |
213 | ||
83f7d43a | 214 | static void ioh3420_register_types(void) |
8135aeed | 215 | { |
39bffca2 | 216 | type_register_static(&ioh3420_info); |
8135aeed IY |
217 | } |
218 | ||
83f7d43a | 219 | type_init(ioh3420_register_types) |