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Commit | Line | Data |
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48ebf2f9 IY |
1 | /* |
2 | * x3130_downstream.c | |
3 | * TI X3130 pci express downstream port switch | |
4 | * | |
5 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
6 | * VA Linux Systems Japan K.K. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
97d5408f | 22 | #include "qemu/osdep.h" |
83c9f4ca PB |
23 | #include "hw/pci/pci_ids.h" |
24 | #include "hw/pci/msi.h" | |
25 | #include "hw/pci/pcie.h" | |
c6329a2d | 26 | #include "hw/pci/pcie_port.h" |
a27bd6c7 | 27 | #include "hw/qdev-properties.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
1108b2f8 | 29 | #include "qapi/error.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
c41481af | 31 | #include "hw/pci-bridge/xio3130_downstream.h" |
48ebf2f9 IY |
32 | |
33 | #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ | |
34 | #define XIO3130_REVISION 0x1 | |
35 | #define XIO3130_MSI_OFFSET 0x70 | |
36 | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT | |
37 | #define XIO3130_MSI_NR_VECTOR 1 | |
38 | #define XIO3130_SSVID_OFFSET 0x80 | |
39 | #define XIO3130_SSVID_SVID 0 | |
40 | #define XIO3130_SSVID_SSID 0 | |
41 | #define XIO3130_EXP_OFFSET 0x90 | |
42 | #define XIO3130_AER_OFFSET 0x100 | |
43 | ||
44 | static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, | |
45 | uint32_t val, int len) | |
46 | { | |
2841ab43 MT |
47 | uint16_t slt_ctl, slt_sta; |
48 | ||
8e2e95ef | 49 | pcie_cap_slot_get(d, &slt_ctl, &slt_sta); |
48ebf2f9 IY |
50 | pci_bridge_write_config(d, address, val, len); |
51 | pcie_cap_flr_write_config(d, address, val, len); | |
2841ab43 | 52 | pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); |
09b926d4 | 53 | pcie_aer_write_config(d, address, val, len); |
48ebf2f9 IY |
54 | } |
55 | ||
56 | static void xio3130_downstream_reset(DeviceState *qdev) | |
57 | { | |
40021f08 | 58 | PCIDevice *d = PCI_DEVICE(qdev); |
cbd2d434 | 59 | |
48ebf2f9 IY |
60 | pcie_cap_deverr_reset(d); |
61 | pcie_cap_slot_reset(d); | |
821be9db | 62 | pcie_cap_arifwd_reset(d); |
48ebf2f9 IY |
63 | pci_bridge_reset(qdev); |
64 | } | |
65 | ||
f8cd1b02 | 66 | static void xio3130_downstream_realize(PCIDevice *d, Error **errp) |
48ebf2f9 | 67 | { |
bcb75750 AF |
68 | PCIEPort *p = PCIE_PORT(d); |
69 | PCIESlot *s = PCIE_SLOT(d); | |
48ebf2f9 IY |
70 | int rc; |
71 | ||
9cfaa007 | 72 | pci_bridge_initfn(d, TYPE_PCIE_BUS); |
48ebf2f9 | 73 | pcie_port_init_reg(d); |
48ebf2f9 IY |
74 | |
75 | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, | |
76 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, | |
f8cd1b02 MZ |
77 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, |
78 | errp); | |
48ebf2f9 | 79 | if (rc < 0) { |
1108b2f8 | 80 | assert(rc == -ENOTSUP); |
09b926d4 | 81 | goto err_bridge; |
48ebf2f9 | 82 | } |
52ea63de | 83 | |
48ebf2f9 | 84 | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
f8cd1b02 MZ |
85 | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, |
86 | errp); | |
48ebf2f9 | 87 | if (rc < 0) { |
a105813a | 88 | goto err_msi; |
48ebf2f9 | 89 | } |
52ea63de | 90 | |
48ebf2f9 | 91 | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, |
f8cd1b02 | 92 | p->port, errp); |
48ebf2f9 | 93 | if (rc < 0) { |
09b926d4 | 94 | goto err_msi; |
48ebf2f9 | 95 | } |
0ead87c8 | 96 | pcie_cap_flr_init(d); |
48ebf2f9 | 97 | pcie_cap_deverr_init(d); |
530a0963 | 98 | pcie_cap_slot_init(d, s); |
52ea63de C |
99 | pcie_cap_arifwd_init(d); |
100 | ||
48ebf2f9 IY |
101 | pcie_chassis_create(s->chassis); |
102 | rc = pcie_chassis_add_slot(s); | |
103 | if (rc < 0) { | |
8b3d2634 | 104 | error_setg(errp, "Can't add chassis slot, error %d", rc); |
09b926d4 | 105 | goto err_pcie_cap; |
48ebf2f9 | 106 | } |
52ea63de | 107 | |
f18c697b | 108 | rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, |
f8cd1b02 | 109 | PCI_ERR_SIZEOF, errp); |
09b926d4 IY |
110 | if (rc < 0) { |
111 | goto err; | |
112 | } | |
48ebf2f9 | 113 | |
f8cd1b02 | 114 | return; |
09b926d4 IY |
115 | |
116 | err: | |
117 | pcie_chassis_del_slot(s); | |
118 | err_pcie_cap: | |
119 | pcie_cap_exit(d); | |
120 | err_msi: | |
121 | msi_uninit(d); | |
122 | err_bridge: | |
f90c2bcd | 123 | pci_bridge_exitfn(d); |
48ebf2f9 IY |
124 | } |
125 | ||
f90c2bcd | 126 | static void xio3130_downstream_exitfn(PCIDevice *d) |
48ebf2f9 | 127 | { |
bcb75750 | 128 | PCIESlot *s = PCIE_SLOT(d); |
09b926d4 IY |
129 | |
130 | pcie_aer_exit(d); | |
131 | pcie_chassis_del_slot(s); | |
48ebf2f9 | 132 | pcie_cap_exit(d); |
09b926d4 | 133 | msi_uninit(d); |
f90c2bcd | 134 | pci_bridge_exitfn(d); |
48ebf2f9 IY |
135 | } |
136 | ||
f23b6bdc MA |
137 | static Property xio3130_downstream_props[] = { |
138 | DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, | |
139 | QEMU_PCIE_SLTCAP_PCP_BITNR, true), | |
140 | DEFINE_PROP_END_OF_LIST() | |
141 | }; | |
142 | ||
48ebf2f9 IY |
143 | static const VMStateDescription vmstate_xio3130_downstream = { |
144 | .name = "xio3130-express-downstream-port", | |
9d6b9db1 | 145 | .priority = MIG_PRI_PCI_BUS, |
48ebf2f9 IY |
146 | .version_id = 1, |
147 | .minimum_version_id = 1, | |
6bde6aaa | 148 | .post_load = pcie_cap_slot_post_load, |
f026c578 | 149 | .fields = (const VMStateField[]) { |
20daa90a | 150 | VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), |
bcb75750 AF |
151 | VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, |
152 | PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), | |
48ebf2f9 IY |
153 | VMSTATE_END_OF_LIST() |
154 | } | |
155 | }; | |
156 | ||
40021f08 AL |
157 | static void xio3130_downstream_class_init(ObjectClass *klass, void *data) |
158 | { | |
39bffca2 | 159 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
160 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
161 | ||
40021f08 | 162 | k->config_write = xio3130_downstream_write_config; |
f8cd1b02 | 163 | k->realize = xio3130_downstream_realize; |
40021f08 AL |
164 | k->exit = xio3130_downstream_exitfn; |
165 | k->vendor_id = PCI_VENDOR_ID_TI; | |
166 | k->device_id = PCI_DEVICE_ID_TI_XIO3130D; | |
167 | k->revision = XIO3130_REVISION; | |
125ee0ed | 168 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 AL |
169 | dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; |
170 | dc->reset = xio3130_downstream_reset; | |
171 | dc->vmsd = &vmstate_xio3130_downstream; | |
4f67d30b | 172 | device_class_set_props(dc, xio3130_downstream_props); |
40021f08 AL |
173 | } |
174 | ||
8c43a6f0 | 175 | static const TypeInfo xio3130_downstream_info = { |
c41481af | 176 | .name = TYPE_XIO3130_DOWNSTREAM, |
bcb75750 | 177 | .parent = TYPE_PCIE_SLOT, |
39bffca2 | 178 | .class_init = xio3130_downstream_class_init, |
71d78767 EH |
179 | .interfaces = (InterfaceInfo[]) { |
180 | { INTERFACE_PCIE_DEVICE }, | |
181 | { } | |
182 | }, | |
48ebf2f9 IY |
183 | }; |
184 | ||
83f7d43a | 185 | static void xio3130_downstream_register_types(void) |
48ebf2f9 | 186 | { |
39bffca2 | 187 | type_register_static(&xio3130_downstream_info); |
48ebf2f9 IY |
188 | } |
189 | ||
83f7d43a | 190 | type_init(xio3130_downstream_register_types) |