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Commit | Line | Data |
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faf1e708 IY |
1 | /* |
2 | * xio3130_upstream.c | |
3 | * TI X3130 pci express upstream port switch | |
4 | * | |
5 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> | |
6 | * VA Linux Systems Japan K.K. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
97d5408f | 22 | #include "qemu/osdep.h" |
83c9f4ca PB |
23 | #include "hw/pci/pci_ids.h" |
24 | #include "hw/pci/msi.h" | |
25 | #include "hw/pci/pcie.h" | |
c6329a2d | 26 | #include "hw/pci/pcie_port.h" |
d6454270 | 27 | #include "migration/vmstate.h" |
0b8fa32f | 28 | #include "qemu/module.h" |
faf1e708 IY |
29 | |
30 | #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ | |
31 | #define XIO3130_REVISION 0x2 | |
32 | #define XIO3130_MSI_OFFSET 0x70 | |
33 | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT | |
34 | #define XIO3130_MSI_NR_VECTOR 1 | |
35 | #define XIO3130_SSVID_OFFSET 0x80 | |
36 | #define XIO3130_SSVID_SVID 0 | |
37 | #define XIO3130_SSVID_SSID 0 | |
38 | #define XIO3130_EXP_OFFSET 0x90 | |
39 | #define XIO3130_AER_OFFSET 0x100 | |
40 | ||
41 | static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, | |
42 | uint32_t val, int len) | |
43 | { | |
44 | pci_bridge_write_config(d, address, val, len); | |
45 | pcie_cap_flr_write_config(d, address, val, len); | |
a158f92f | 46 | pcie_aer_write_config(d, address, val, len); |
faf1e708 IY |
47 | } |
48 | ||
49 | static void xio3130_upstream_reset(DeviceState *qdev) | |
50 | { | |
40021f08 | 51 | PCIDevice *d = PCI_DEVICE(qdev); |
cbd2d434 | 52 | |
faf1e708 IY |
53 | pci_bridge_reset(qdev); |
54 | pcie_cap_deverr_reset(d); | |
55 | } | |
56 | ||
f8cd1b02 | 57 | static void xio3130_upstream_realize(PCIDevice *d, Error **errp) |
faf1e708 | 58 | { |
bcb75750 | 59 | PCIEPort *p = PCIE_PORT(d); |
faf1e708 IY |
60 | int rc; |
61 | ||
9cfaa007 | 62 | pci_bridge_initfn(d, TYPE_PCIE_BUS); |
faf1e708 | 63 | pcie_port_init_reg(d); |
faf1e708 IY |
64 | |
65 | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, | |
66 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, | |
f8cd1b02 MZ |
67 | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, |
68 | errp); | |
faf1e708 | 69 | if (rc < 0) { |
1108b2f8 | 70 | assert(rc == -ENOTSUP); |
a158f92f | 71 | goto err_bridge; |
faf1e708 | 72 | } |
52ea63de | 73 | |
faf1e708 | 74 | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
f8cd1b02 MZ |
75 | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, |
76 | errp); | |
faf1e708 | 77 | if (rc < 0) { |
16ddcbd3 | 78 | goto err_msi; |
faf1e708 | 79 | } |
52ea63de | 80 | |
faf1e708 | 81 | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, |
f8cd1b02 | 82 | p->port, errp); |
faf1e708 | 83 | if (rc < 0) { |
a158f92f | 84 | goto err_msi; |
faf1e708 | 85 | } |
faf1e708 | 86 | pcie_cap_flr_init(d); |
faf1e708 | 87 | pcie_cap_deverr_init(d); |
52ea63de | 88 | |
f18c697b | 89 | rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, |
f8cd1b02 | 90 | PCI_ERR_SIZEOF, errp); |
a158f92f IY |
91 | if (rc < 0) { |
92 | goto err; | |
93 | } | |
faf1e708 | 94 | |
f8cd1b02 | 95 | return; |
a158f92f IY |
96 | |
97 | err: | |
98 | pcie_cap_exit(d); | |
99 | err_msi: | |
100 | msi_uninit(d); | |
101 | err_bridge: | |
f90c2bcd | 102 | pci_bridge_exitfn(d); |
faf1e708 IY |
103 | } |
104 | ||
f90c2bcd | 105 | static void xio3130_upstream_exitfn(PCIDevice *d) |
faf1e708 | 106 | { |
a158f92f | 107 | pcie_aer_exit(d); |
faf1e708 | 108 | pcie_cap_exit(d); |
a158f92f | 109 | msi_uninit(d); |
f90c2bcd | 110 | pci_bridge_exitfn(d); |
faf1e708 IY |
111 | } |
112 | ||
faf1e708 IY |
113 | static const VMStateDescription vmstate_xio3130_upstream = { |
114 | .name = "xio3130-express-upstream-port", | |
9d6b9db1 | 115 | .priority = MIG_PRI_PCI_BUS, |
faf1e708 IY |
116 | .version_id = 1, |
117 | .minimum_version_id = 1, | |
faf1e708 | 118 | .fields = (VMStateField[]) { |
20daa90a | 119 | VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort), |
bcb75750 | 120 | VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, |
f055e96b | 121 | vmstate_pcie_aer_log, PCIEAERLog), |
faf1e708 IY |
122 | VMSTATE_END_OF_LIST() |
123 | } | |
124 | }; | |
125 | ||
40021f08 AL |
126 | static void xio3130_upstream_class_init(ObjectClass *klass, void *data) |
127 | { | |
39bffca2 | 128 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
129 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
130 | ||
91f4c995 | 131 | k->is_bridge = true; |
40021f08 | 132 | k->config_write = xio3130_upstream_write_config; |
f8cd1b02 | 133 | k->realize = xio3130_upstream_realize; |
40021f08 AL |
134 | k->exit = xio3130_upstream_exitfn; |
135 | k->vendor_id = PCI_VENDOR_ID_TI; | |
136 | k->device_id = PCI_DEVICE_ID_TI_XIO3130U; | |
137 | k->revision = XIO3130_REVISION; | |
125ee0ed | 138 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 AL |
139 | dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; |
140 | dc->reset = xio3130_upstream_reset; | |
141 | dc->vmsd = &vmstate_xio3130_upstream; | |
40021f08 AL |
142 | } |
143 | ||
8c43a6f0 | 144 | static const TypeInfo xio3130_upstream_info = { |
39bffca2 | 145 | .name = "x3130-upstream", |
bcb75750 | 146 | .parent = TYPE_PCIE_PORT, |
39bffca2 | 147 | .class_init = xio3130_upstream_class_init, |
71d78767 EH |
148 | .interfaces = (InterfaceInfo[]) { |
149 | { INTERFACE_PCIE_DEVICE }, | |
150 | { } | |
151 | }, | |
faf1e708 IY |
152 | }; |
153 | ||
83f7d43a | 154 | static void xio3130_upstream_register_types(void) |
faf1e708 | 155 | { |
39bffca2 | 156 | type_register_static(&xio3130_upstream_info); |
faf1e708 IY |
157 | } |
158 | ||
83f7d43a | 159 | type_init(xio3130_upstream_register_types) |