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Commit | Line | Data |
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d0f7453d HC |
1 | /* |
2 | * bonito north bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
d0f7453d HC |
11 | */ |
12 | ||
13 | /* | |
c3a09ff6 | 14 | * fuloong 2e mini pc has a bonito north bridge. |
d0f7453d HC |
15 | */ |
16 | ||
f3db354c FB |
17 | /* |
18 | * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? | |
d0f7453d HC |
19 | * |
20 | * devfn pci_slot<<3 + funno | |
21 | * one pci bus can have 32 devices and each device can have 8 functions. | |
22 | * | |
23 | * In bonito north bridge, pci slot = IDSEL bit - 12. | |
24 | * For example, PCI_IDSEL_VIA686B = 17, | |
25 | * pci slot = 17-12=5 | |
26 | * | |
27 | * so | |
28 | * VT686B_FUN0's devfn = (5<<3)+0 | |
29 | * VT686B_FUN1's devfn = (5<<3)+1 | |
30 | * | |
31 | * qemu also uses pci address for north bridge to access pci config register. | |
32 | * bus_no [23:16] | |
33 | * dev_no [15:11] | |
34 | * fun_no [10:8] | |
35 | * reg_no [7:2] | |
36 | * | |
37 | * so function bonito_sbridge_pciaddr for the translation from | |
38 | * north bridge address to pci address. | |
39 | */ | |
40 | ||
97d5408f | 41 | #include "qemu/osdep.h" |
a0b544c1 | 42 | #include "qemu/units.h" |
3e80f690 | 43 | #include "qapi/error.h" |
0151abe4 | 44 | #include "qemu/error-report.h" |
83c9f4ca | 45 | #include "hw/pci/pci.h" |
64552b6b | 46 | #include "hw/irq.h" |
0d09e41a | 47 | #include "hw/mips/mips.h" |
83c9f4ca | 48 | #include "hw/pci/pci_host.h" |
d6454270 | 49 | #include "migration/vmstate.h" |
71e8a915 | 50 | #include "sysemu/reset.h" |
54d31236 | 51 | #include "sysemu/runstate.h" |
022c62cb | 52 | #include "exec/address-spaces.h" |
25cca0a9 | 53 | #include "hw/misc/unimp.h" |
1f8a6c8b | 54 | #include "hw/registerfields.h" |
db1015e9 | 55 | #include "qom/object.h" |
d0f7453d | 56 | |
f3db354c | 57 | /* #define DEBUG_BONITO */ |
d0f7453d HC |
58 | |
59 | #ifdef DEBUG_BONITO | |
a89f364a | 60 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
d0f7453d HC |
61 | #else |
62 | #define DPRINTF(fmt, ...) | |
63 | #endif | |
64 | ||
65 | /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ | |
66 | #define BONITO_BOOT_BASE 0x1fc00000 | |
67 | #define BONITO_BOOT_SIZE 0x00100000 | |
f3db354c | 68 | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) |
d0f7453d HC |
69 | #define BONITO_FLASH_BASE 0x1c000000 |
70 | #define BONITO_FLASH_SIZE 0x03000000 | |
f3db354c | 71 | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) |
d0f7453d HC |
72 | #define BONITO_SOCKET_BASE 0x1f800000 |
73 | #define BONITO_SOCKET_SIZE 0x00400000 | |
f3db354c | 74 | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) |
d0f7453d HC |
75 | #define BONITO_REG_BASE 0x1fe00000 |
76 | #define BONITO_REG_SIZE 0x00040000 | |
f3db354c | 77 | #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) |
d0f7453d HC |
78 | #define BONITO_DEV_BASE 0x1ff00000 |
79 | #define BONITO_DEV_SIZE 0x00100000 | |
f3db354c | 80 | #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) |
d0f7453d HC |
81 | #define BONITO_PCILO_BASE 0x10000000 |
82 | #define BONITO_PCILO_BASE_VA 0xb0000000 | |
83 | #define BONITO_PCILO_SIZE 0x0c000000 | |
f3db354c | 84 | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) |
d0f7453d HC |
85 | #define BONITO_PCILO0_BASE 0x10000000 |
86 | #define BONITO_PCILO1_BASE 0x14000000 | |
87 | #define BONITO_PCILO2_BASE 0x18000000 | |
88 | #define BONITO_PCIHI_BASE 0x20000000 | |
a0b544c1 | 89 | #define BONITO_PCIHI_SIZE 0x60000000 |
f3db354c | 90 | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) |
d0f7453d HC |
91 | #define BONITO_PCIIO_BASE 0x1fd00000 |
92 | #define BONITO_PCIIO_BASE_VA 0xbfd00000 | |
93 | #define BONITO_PCIIO_SIZE 0x00010000 | |
f3db354c | 94 | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) |
d0f7453d HC |
95 | #define BONITO_PCICFG_BASE 0x1fe80000 |
96 | #define BONITO_PCICFG_SIZE 0x00080000 | |
f3db354c | 97 | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) |
d0f7453d HC |
98 | |
99 | ||
100 | #define BONITO_PCICONFIGBASE 0x00 | |
101 | #define BONITO_REGBASE 0x100 | |
102 | ||
f3db354c | 103 | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) |
d0f7453d HC |
104 | #define BONITO_PCICONFIG_SIZE (0x100) |
105 | ||
f3db354c | 106 | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) |
d0f7453d HC |
107 | #define BONITO_INTERNAL_REG_SIZE (0x70) |
108 | ||
109 | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) | |
110 | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) | |
111 | ||
112 | ||
113 | ||
114 | /* 1. Bonito h/w Configuration */ | |
115 | /* Power on register */ | |
116 | ||
117 | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ | |
1f8a6c8b PMD |
118 | |
119 | /* PCI configuration register */ | |
d0f7453d | 120 | #define BONITO_BONGENCFG_OFFSET 0x4 |
f3db354c | 121 | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ |
1f8a6c8b PMD |
122 | REG32(BONGENCFG, 0x104) |
123 | FIELD(BONGENCFG, DEBUGMODE, 0, 1) | |
124 | FIELD(BONGENCFG, SNOOP, 1, 1) | |
125 | FIELD(BONGENCFG, CPUSELFRESET, 2, 1) | |
126 | FIELD(BONGENCFG, BYTESWAP, 6, 1) | |
127 | FIELD(BONGENCFG, UNCACHED, 7, 1) | |
128 | FIELD(BONGENCFG, PREFETCH, 8, 1) | |
129 | FIELD(BONGENCFG, WRITEBEHIND, 9, 1) | |
130 | FIELD(BONGENCFG, PCIQUEUE, 12, 1) | |
d0f7453d HC |
131 | |
132 | /* 2. IO & IDE configuration */ | |
133 | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ | |
134 | ||
135 | /* 3. IO & IDE configuration */ | |
136 | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ | |
137 | ||
138 | /* 4. PCI address map control */ | |
139 | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ | |
140 | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ | |
141 | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ | |
142 | ||
143 | /* 5. ICU & GPIO regs */ | |
144 | /* GPIO Regs - r/w */ | |
145 | #define BONITO_GPIODATA_OFFSET 0x1c | |
146 | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ | |
147 | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ | |
148 | ||
149 | /* ICU Configuration Regs - r/w */ | |
150 | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ | |
151 | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ | |
152 | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ | |
153 | ||
154 | /* ICU Enable Regs - IntEn & IntISR are r/o. */ | |
155 | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ | |
156 | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ | |
157 | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ | |
158 | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ | |
159 | ||
160 | /* PCI mail boxes */ | |
161 | #define BONITO_PCIMAIL0_OFFSET 0x40 | |
162 | #define BONITO_PCIMAIL1_OFFSET 0x44 | |
163 | #define BONITO_PCIMAIL2_OFFSET 0x48 | |
164 | #define BONITO_PCIMAIL3_OFFSET 0x4c | |
165 | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ | |
166 | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ | |
167 | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ | |
168 | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ | |
169 | ||
170 | /* 6. PCI cache */ | |
171 | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ | |
172 | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ | |
173 | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ | |
174 | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ | |
175 | ||
176 | /* 7. other*/ | |
177 | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ | |
178 | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ | |
179 | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ | |
180 | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ | |
181 | ||
182 | #define BONITO_REGS (0x70 >> 2) | |
183 | ||
184 | /* PCI config for south bridge. type 0 */ | |
185 | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ | |
186 | #define BONITO_PCICONF_IDSEL_OFFSET 11 | |
187 | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ | |
188 | #define BONITO_PCICONF_FUN_OFFSET 8 | |
189 | #define BONITO_PCICONF_REG_MASK 0xFC | |
190 | #define BONITO_PCICONF_REG_OFFSET 0 | |
191 | ||
192 | ||
193 | /* idsel BIT = pci slot number +12 */ | |
194 | #define PCI_SLOT_BASE 12 | |
195 | #define PCI_IDSEL_VIA686B_BIT (17) | |
f3db354c | 196 | #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) |
d0f7453d | 197 | |
f3db354c | 198 | #define PCI_ADDR(busno , devno , funno , regno) \ |
0374cbd2 | 199 | ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno)) |
d0f7453d | 200 | |
c5589ee9 | 201 | typedef struct BonitoState BonitoState; |
d0f7453d | 202 | |
db1015e9 | 203 | struct PCIBonitoState { |
d0f7453d | 204 | PCIDevice dev; |
c5589ee9 | 205 | |
d0f7453d HC |
206 | BonitoState *pcihost; |
207 | uint32_t regs[BONITO_REGS]; | |
208 | ||
209 | struct bonldma { | |
210 | uint32_t ldmactrl; | |
211 | uint32_t ldmastat; | |
212 | uint32_t ldmaaddr; | |
213 | uint32_t ldmago; | |
214 | } bonldma; | |
215 | ||
216 | /* Based at 1fe00300, bonito Copier */ | |
217 | struct boncop { | |
218 | uint32_t copctrl; | |
219 | uint32_t copstat; | |
220 | uint32_t coppaddr; | |
221 | uint32_t copgo; | |
222 | } boncop; | |
223 | ||
224 | /* Bonito registers */ | |
89200979 | 225 | MemoryRegion iomem; |
def344a6 | 226 | MemoryRegion iomem_ldma; |
9a542a48 | 227 | MemoryRegion iomem_cop; |
e37b80fa PB |
228 | MemoryRegion bonito_pciio; |
229 | MemoryRegion bonito_localio; | |
d0f7453d | 230 | |
db1015e9 EH |
231 | }; |
232 | typedef struct PCIBonitoState PCIBonitoState; | |
d0f7453d | 233 | |
c5589ee9 AF |
234 | struct BonitoState { |
235 | PCIHostState parent_obj; | |
c5589ee9 | 236 | qemu_irq *pic; |
c5589ee9 | 237 | PCIBonitoState *pci_dev; |
f7cf2219 | 238 | MemoryRegion pci_mem; |
c5589ee9 | 239 | }; |
d0f7453d | 240 | |
a2a645d9 | 241 | #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" |
8063396b | 242 | OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE) |
a2a645d9 C |
243 | |
244 | #define TYPE_PCI_BONITO "Bonito" | |
8063396b | 245 | OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO) |
a2a645d9 | 246 | |
a8170e5e | 247 | static void bonito_writel(void *opaque, hwaddr addr, |
89200979 | 248 | uint64_t val, unsigned size) |
d0f7453d HC |
249 | { |
250 | PCIBonitoState *s = opaque; | |
251 | uint32_t saddr; | |
252 | int reset = 0; | |
253 | ||
0ca4f941 | 254 | saddr = addr >> 2; |
d0f7453d | 255 | |
3d14264c | 256 | DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n", |
f3db354c | 257 | addr, val, saddr); |
d0f7453d HC |
258 | switch (saddr) { |
259 | case BONITO_BONPONCFG: | |
260 | case BONITO_IODEVCFG: | |
261 | case BONITO_SDCFG: | |
262 | case BONITO_PCIMAP: | |
263 | case BONITO_PCIMEMBASECFG: | |
264 | case BONITO_PCIMAP_CFG: | |
265 | case BONITO_GPIODATA: | |
266 | case BONITO_GPIOIE: | |
267 | case BONITO_INTEDGE: | |
268 | case BONITO_INTSTEER: | |
269 | case BONITO_INTPOL: | |
270 | case BONITO_PCIMAIL0: | |
271 | case BONITO_PCIMAIL1: | |
272 | case BONITO_PCIMAIL2: | |
273 | case BONITO_PCIMAIL3: | |
274 | case BONITO_PCICACHECTRL: | |
275 | case BONITO_PCICACHETAG: | |
276 | case BONITO_PCIBADADDR: | |
277 | case BONITO_PCIMSTAT: | |
278 | case BONITO_TIMECFG: | |
279 | case BONITO_CPUCFG: | |
280 | case BONITO_DQCFG: | |
281 | case BONITO_MEMSIZE: | |
282 | s->regs[saddr] = val; | |
283 | break; | |
284 | case BONITO_BONGENCFG: | |
285 | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { | |
286 | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ | |
287 | } | |
288 | s->regs[saddr] = val; | |
289 | if (reset) { | |
cf83f140 | 290 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
d0f7453d HC |
291 | } |
292 | break; | |
293 | case BONITO_INTENSET: | |
294 | s->regs[BONITO_INTENSET] = val; | |
295 | s->regs[BONITO_INTEN] |= val; | |
296 | break; | |
297 | case BONITO_INTENCLR: | |
298 | s->regs[BONITO_INTENCLR] = val; | |
299 | s->regs[BONITO_INTEN] &= ~val; | |
300 | break; | |
301 | case BONITO_INTEN: | |
302 | case BONITO_INTISR: | |
b2bedb21 | 303 | DPRINTF("write to readonly bonito register %x\n", saddr); |
d0f7453d HC |
304 | break; |
305 | default: | |
b2bedb21 | 306 | DPRINTF("write to unknown bonito register %x\n", saddr); |
d0f7453d HC |
307 | break; |
308 | } | |
309 | } | |
310 | ||
a8170e5e | 311 | static uint64_t bonito_readl(void *opaque, hwaddr addr, |
89200979 | 312 | unsigned size) |
d0f7453d HC |
313 | { |
314 | PCIBonitoState *s = opaque; | |
315 | uint32_t saddr; | |
316 | ||
0ca4f941 | 317 | saddr = addr >> 2; |
d0f7453d | 318 | |
b2bedb21 | 319 | DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); |
d0f7453d HC |
320 | switch (saddr) { |
321 | case BONITO_INTISR: | |
322 | return s->regs[saddr]; | |
323 | default: | |
324 | return s->regs[saddr]; | |
325 | } | |
326 | } | |
327 | ||
89200979 BC |
328 | static const MemoryRegionOps bonito_ops = { |
329 | .read = bonito_readl, | |
330 | .write = bonito_writel, | |
331 | .endianness = DEVICE_NATIVE_ENDIAN, | |
332 | .valid = { | |
333 | .min_access_size = 4, | |
334 | .max_access_size = 4, | |
335 | }, | |
d0f7453d HC |
336 | }; |
337 | ||
a8170e5e | 338 | static void bonito_pciconf_writel(void *opaque, hwaddr addr, |
183e1d40 | 339 | uint64_t val, unsigned size) |
d0f7453d HC |
340 | { |
341 | PCIBonitoState *s = opaque; | |
c5589ee9 | 342 | PCIDevice *d = PCI_DEVICE(s); |
d0f7453d | 343 | |
3d14264c | 344 | DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val); |
c5589ee9 | 345 | d->config_write(d, addr, val, 4); |
d0f7453d HC |
346 | } |
347 | ||
a8170e5e | 348 | static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, |
183e1d40 | 349 | unsigned size) |
d0f7453d HC |
350 | { |
351 | ||
352 | PCIBonitoState *s = opaque; | |
c5589ee9 | 353 | PCIDevice *d = PCI_DEVICE(s); |
d0f7453d HC |
354 | |
355 | DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); | |
c5589ee9 | 356 | return d->config_read(d, addr, 4); |
d0f7453d HC |
357 | } |
358 | ||
359 | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ | |
d0f7453d | 360 | |
183e1d40 BC |
361 | static const MemoryRegionOps bonito_pciconf_ops = { |
362 | .read = bonito_pciconf_readl, | |
363 | .write = bonito_pciconf_writel, | |
364 | .endianness = DEVICE_NATIVE_ENDIAN, | |
365 | .valid = { | |
366 | .min_access_size = 4, | |
367 | .max_access_size = 4, | |
368 | }, | |
d0f7453d HC |
369 | }; |
370 | ||
a8170e5e | 371 | static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, |
def344a6 | 372 | unsigned size) |
d0f7453d HC |
373 | { |
374 | uint32_t val; | |
375 | PCIBonitoState *s = opaque; | |
376 | ||
58d47978 PM |
377 | if (addr >= sizeof(s->bonldma)) { |
378 | return 0; | |
379 | } | |
380 | ||
f3db354c | 381 | val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; |
d0f7453d HC |
382 | |
383 | return val; | |
384 | } | |
385 | ||
a8170e5e | 386 | static void bonito_ldma_writel(void *opaque, hwaddr addr, |
def344a6 | 387 | uint64_t val, unsigned size) |
d0f7453d HC |
388 | { |
389 | PCIBonitoState *s = opaque; | |
390 | ||
58d47978 PM |
391 | if (addr >= sizeof(s->bonldma)) { |
392 | return; | |
393 | } | |
394 | ||
f3db354c | 395 | ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
d0f7453d HC |
396 | } |
397 | ||
def344a6 BC |
398 | static const MemoryRegionOps bonito_ldma_ops = { |
399 | .read = bonito_ldma_readl, | |
400 | .write = bonito_ldma_writel, | |
401 | .endianness = DEVICE_NATIVE_ENDIAN, | |
402 | .valid = { | |
403 | .min_access_size = 4, | |
404 | .max_access_size = 4, | |
405 | }, | |
d0f7453d HC |
406 | }; |
407 | ||
a8170e5e | 408 | static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, |
9a542a48 | 409 | unsigned size) |
d0f7453d HC |
410 | { |
411 | uint32_t val; | |
412 | PCIBonitoState *s = opaque; | |
413 | ||
58d47978 PM |
414 | if (addr >= sizeof(s->boncop)) { |
415 | return 0; | |
416 | } | |
417 | ||
f3db354c | 418 | val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; |
d0f7453d HC |
419 | |
420 | return val; | |
421 | } | |
422 | ||
a8170e5e | 423 | static void bonito_cop_writel(void *opaque, hwaddr addr, |
9a542a48 | 424 | uint64_t val, unsigned size) |
d0f7453d HC |
425 | { |
426 | PCIBonitoState *s = opaque; | |
427 | ||
58d47978 PM |
428 | if (addr >= sizeof(s->boncop)) { |
429 | return; | |
430 | } | |
431 | ||
f3db354c | 432 | ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; |
d0f7453d HC |
433 | } |
434 | ||
9a542a48 BC |
435 | static const MemoryRegionOps bonito_cop_ops = { |
436 | .read = bonito_cop_readl, | |
437 | .write = bonito_cop_writel, | |
438 | .endianness = DEVICE_NATIVE_ENDIAN, | |
439 | .valid = { | |
440 | .min_access_size = 4, | |
441 | .max_access_size = 4, | |
442 | }, | |
d0f7453d HC |
443 | }; |
444 | ||
a8170e5e | 445 | static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) |
d0f7453d HC |
446 | { |
447 | PCIBonitoState *s = opaque; | |
8558d942 | 448 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
449 | uint32_t cfgaddr; |
450 | uint32_t idsel; | |
451 | uint32_t devno; | |
452 | uint32_t funno; | |
453 | uint32_t regno; | |
454 | uint32_t pciaddr; | |
455 | ||
456 | /* support type0 pci config */ | |
457 | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { | |
458 | return 0xffffffff; | |
459 | } | |
460 | ||
461 | cfgaddr = addr & 0xffff; | |
462 | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; | |
463 | ||
f3db354c FB |
464 | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> |
465 | BONITO_PCICONF_IDSEL_OFFSET; | |
786a4ea8 | 466 | devno = ctz32(idsel); |
d0f7453d HC |
467 | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; |
468 | regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; | |
469 | ||
470 | if (idsel == 0) { | |
ce3f3d30 PMD |
471 | error_report("error in bonito pci config address 0x" TARGET_FMT_plx |
472 | ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]); | |
d0f7453d HC |
473 | exit(1); |
474 | } | |
c5589ee9 | 475 | pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); |
b2bedb21 | 476 | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", |
c5589ee9 | 477 | cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); |
d0f7453d HC |
478 | |
479 | return pciaddr; | |
480 | } | |
481 | ||
421ab725 PM |
482 | static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, |
483 | unsigned size) | |
d0f7453d HC |
484 | { |
485 | PCIBonitoState *s = opaque; | |
c5589ee9 | 486 | PCIDevice *d = PCI_DEVICE(s); |
8558d942 | 487 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
488 | uint32_t pciaddr; |
489 | uint16_t status; | |
490 | ||
3d14264c | 491 | DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n", |
421ab725 | 492 | addr, size, val); |
d0f7453d HC |
493 | |
494 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
495 | ||
496 | if (pciaddr == 0xffffffff) { | |
497 | return; | |
498 | } | |
499 | ||
500 | /* set the pci address in s->config_reg */ | |
c5589ee9 | 501 | phb->config_reg = (pciaddr) | (1u << 31); |
421ab725 | 502 | pci_data_write(phb->bus, phb->config_reg, val, size); |
d0f7453d HC |
503 | |
504 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
c5589ee9 | 505 | status = pci_get_word(d->config + PCI_STATUS); |
d0f7453d | 506 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
c5589ee9 | 507 | pci_set_word(d->config + PCI_STATUS, status); |
d0f7453d HC |
508 | } |
509 | ||
421ab725 | 510 | static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) |
d0f7453d HC |
511 | { |
512 | PCIBonitoState *s = opaque; | |
c5589ee9 | 513 | PCIDevice *d = PCI_DEVICE(s); |
8558d942 | 514 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
d0f7453d HC |
515 | uint32_t pciaddr; |
516 | uint16_t status; | |
517 | ||
421ab725 | 518 | DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); |
d0f7453d HC |
519 | |
520 | pciaddr = bonito_sbridge_pciaddr(s, addr); | |
521 | ||
522 | if (pciaddr == 0xffffffff) { | |
421ab725 | 523 | return MAKE_64BIT_MASK(0, size * 8); |
d0f7453d HC |
524 | } |
525 | ||
526 | /* set the pci address in s->config_reg */ | |
c5589ee9 | 527 | phb->config_reg = (pciaddr) | (1u << 31); |
d0f7453d HC |
528 | |
529 | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ | |
c5589ee9 | 530 | status = pci_get_word(d->config + PCI_STATUS); |
d0f7453d | 531 | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
c5589ee9 | 532 | pci_set_word(d->config + PCI_STATUS, status); |
d0f7453d | 533 | |
421ab725 | 534 | return pci_data_read(phb->bus, phb->config_reg, size); |
d0f7453d HC |
535 | } |
536 | ||
537 | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ | |
845cbeb8 | 538 | static const MemoryRegionOps bonito_spciconf_ops = { |
421ab725 PM |
539 | .read = bonito_spciconf_read, |
540 | .write = bonito_spciconf_write, | |
541 | .valid.min_access_size = 1, | |
542 | .valid.max_access_size = 4, | |
543 | .impl.min_access_size = 1, | |
544 | .impl.max_access_size = 4, | |
845cbeb8 | 545 | .endianness = DEVICE_NATIVE_ENDIAN, |
d0f7453d HC |
546 | }; |
547 | ||
548 | #define BONITO_IRQ_BASE 32 | |
549 | ||
550 | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) | |
551 | { | |
c5589ee9 AF |
552 | BonitoState *s = opaque; |
553 | qemu_irq *pic = s->pic; | |
554 | PCIBonitoState *bonito_state = s->pci_dev; | |
d0f7453d HC |
555 | int internal_irq = irq_num - BONITO_IRQ_BASE; |
556 | ||
c5589ee9 | 557 | if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { |
d0f7453d HC |
558 | qemu_irq_pulse(*pic); |
559 | } else { /* level triggered */ | |
c5589ee9 | 560 | if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { |
d0f7453d HC |
561 | qemu_irq_raise(*pic); |
562 | } else { | |
563 | qemu_irq_lower(*pic); | |
564 | } | |
565 | } | |
566 | } | |
567 | ||
568 | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ | |
f3db354c | 569 | static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) |
d0f7453d HC |
570 | { |
571 | int slot; | |
572 | ||
8d40def6 | 573 | slot = PCI_SLOT(pci_dev->devfn); |
d0f7453d HC |
574 | |
575 | switch (slot) { | |
c3a09ff6 | 576 | case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ |
d0f7453d | 577 | return irq_num % 4 + BONITO_IRQ_BASE; |
c3a09ff6 | 578 | case 6: /* FULOONG2E_ATI_SLOT, VGA */ |
d0f7453d | 579 | return 4 + BONITO_IRQ_BASE; |
c3a09ff6 | 580 | case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */ |
d0f7453d HC |
581 | return 5 + BONITO_IRQ_BASE; |
582 | case 8 ... 12: /* PCI slot 1 to 4 */ | |
583 | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; | |
584 | default: /* Unknown device, don't do any translation */ | |
585 | return irq_num; | |
586 | } | |
587 | } | |
588 | ||
589 | static void bonito_reset(void *opaque) | |
590 | { | |
591 | PCIBonitoState *s = opaque; | |
1f8a6c8b | 592 | uint32_t val = 0; |
d0f7453d HC |
593 | |
594 | /* set the default value of north bridge registers */ | |
595 | ||
596 | s->regs[BONITO_BONPONCFG] = 0xc40; | |
1f8a6c8b PMD |
597 | val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1); |
598 | val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1); | |
599 | val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1); | |
600 | val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1); | |
601 | val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1); | |
602 | s->regs[BONITO_BONGENCFG] = val; | |
603 | ||
d0f7453d HC |
604 | s->regs[BONITO_IODEVCFG] = 0x2bff8010; |
605 | s->regs[BONITO_SDCFG] = 0x255e0091; | |
606 | ||
607 | s->regs[BONITO_GPIODATA] = 0x1ff; | |
608 | s->regs[BONITO_GPIOIE] = 0x1ff; | |
609 | s->regs[BONITO_DQCFG] = 0x8; | |
610 | s->regs[BONITO_MEMSIZE] = 0x10000000; | |
611 | s->regs[BONITO_PCIMAP] = 0x6140; | |
612 | } | |
613 | ||
614 | static const VMStateDescription vmstate_bonito = { | |
615 | .name = "Bonito", | |
616 | .version_id = 1, | |
617 | .minimum_version_id = 1, | |
35d08458 | 618 | .fields = (VMStateField[]) { |
d0f7453d HC |
619 | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), |
620 | VMSTATE_END_OF_LIST() | |
621 | } | |
622 | }; | |
623 | ||
e800894a | 624 | static void bonito_pcihost_realize(DeviceState *dev, Error **errp) |
d0f7453d | 625 | { |
8558d942 | 626 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
f7cf2219 | 627 | BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); |
a0b544c1 | 628 | MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3); |
c5589ee9 | 629 | |
a0b544c1 | 630 | memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE); |
8e5c952b | 631 | phb->bus = pci_register_root_bus(dev, "pci", |
1115ff6d | 632 | pci_bonito_set_irq, pci_bonito_map_irq, |
f7cf2219 | 633 | dev, &bs->pci_mem, get_system_io(), |
4934e479 | 634 | PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS); |
a0b544c1 PMD |
635 | |
636 | for (size_t i = 0; i < 3; i++) { | |
637 | char *name = g_strdup_printf("pci.lomem%zu", i); | |
638 | ||
639 | memory_region_init_alias(&pcimem_lo_alias[i], NULL, name, | |
640 | &bs->pci_mem, i * 64 * MiB, 64 * MiB); | |
641 | memory_region_add_subregion(get_system_memory(), | |
642 | BONITO_PCILO_BASE + i * 64 * MiB, | |
643 | &pcimem_lo_alias[i]); | |
644 | g_free(name); | |
645 | } | |
646 | ||
647 | create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB); | |
d0f7453d HC |
648 | } |
649 | ||
9af21dbe | 650 | static void bonito_realize(PCIDevice *dev, Error **errp) |
d0f7453d | 651 | { |
a2a645d9 | 652 | PCIBonitoState *s = PCI_BONITO(dev); |
c5589ee9 | 653 | SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); |
8558d942 | 654 | PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); |
a0b544c1 PMD |
655 | BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost); |
656 | MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1); | |
d0f7453d | 657 | |
f3db354c FB |
658 | /* |
659 | * Bonito North Bridge, built on FPGA, | |
660 | * VENDOR_ID/DEVICE_ID are "undefined" | |
661 | */ | |
d0f7453d | 662 | pci_config_set_prog_interface(dev->config, 0x00); |
d0f7453d HC |
663 | |
664 | /* set the north bridge register mapping */ | |
40c5dce9 | 665 | memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, |
89200979 | 666 | "north-bridge-register", BONITO_INTERNAL_REG_SIZE); |
750ecd44 | 667 | sysbus_init_mmio(sysbus, &s->iomem); |
89200979 | 668 | sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); |
d0f7453d HC |
669 | |
670 | /* set the north bridge pci configure mapping */ | |
40c5dce9 | 671 | memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, |
183e1d40 | 672 | "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); |
c5589ee9 | 673 | sysbus_init_mmio(sysbus, &phb->conf_mem); |
183e1d40 | 674 | sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); |
d0f7453d HC |
675 | |
676 | /* set the south bridge pci configure mapping */ | |
40c5dce9 | 677 | memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, |
845cbeb8 | 678 | "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); |
c5589ee9 | 679 | sysbus_init_mmio(sysbus, &phb->data_mem); |
845cbeb8 | 680 | sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); |
d0f7453d | 681 | |
25cca0a9 PMD |
682 | create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE); |
683 | ||
40c5dce9 | 684 | memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, |
def344a6 | 685 | "ldma", 0x100); |
750ecd44 | 686 | sysbus_init_mmio(sysbus, &s->iomem_ldma); |
86313bdc | 687 | sysbus_mmio_map(sysbus, 3, 0x1fe00200); |
d0f7453d | 688 | |
a0b544c1 | 689 | /* PCI copier */ |
40c5dce9 | 690 | memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, |
9a542a48 | 691 | "cop", 0x100); |
750ecd44 | 692 | sysbus_init_mmio(sysbus, &s->iomem_cop); |
86313bdc | 693 | sysbus_mmio_map(sysbus, 4, 0x1fe00300); |
d0f7453d | 694 | |
7a296990 PMD |
695 | create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB); |
696 | ||
d0f7453d | 697 | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ |
e37b80fa PB |
698 | memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", |
699 | get_system_io(), 0, BONITO_PCIIO_SIZE); | |
700 | sysbus_init_mmio(sysbus, &s->bonito_pciio); | |
701 | sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); | |
d0f7453d HC |
702 | |
703 | /* add pci local io mapping */ | |
7a296990 PMD |
704 | |
705 | memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]", | |
706 | get_system_io(), 0, 256 * KiB); | |
e37b80fa PB |
707 | sysbus_init_mmio(sysbus, &s->bonito_localio); |
708 | sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); | |
7a296990 PMD |
709 | create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB, |
710 | 256 * KiB); | |
711 | create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB, | |
712 | 256 * KiB); | |
713 | create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB, | |
714 | 256 * KiB); | |
d0f7453d | 715 | |
a0b544c1 PMD |
716 | memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias", |
717 | &bs->pci_mem, 0, BONITO_PCIHI_SIZE); | |
718 | memory_region_add_subregion(get_system_memory(), | |
719 | BONITO_PCIHI_BASE, pcimem_alias); | |
720 | create_unimplemented_device("PCI_2", | |
721 | (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE, | |
722 | 2 * GiB); | |
723 | ||
d0f7453d HC |
724 | /* set the default value of north bridge pci config */ |
725 | pci_set_word(dev->config + PCI_COMMAND, 0x0000); | |
726 | pci_set_word(dev->config + PCI_STATUS, 0x0000); | |
727 | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); | |
728 | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); | |
729 | ||
730 | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); | |
b4bb339b PMD |
731 | pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */ |
732 | ||
d0f7453d HC |
733 | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); |
734 | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); | |
735 | ||
736 | qemu_register_reset(bonito_reset, s); | |
d0f7453d HC |
737 | } |
738 | ||
739 | PCIBus *bonito_init(qemu_irq *pic) | |
740 | { | |
741 | DeviceState *dev; | |
d0f7453d | 742 | BonitoState *pcihost; |
c5589ee9 | 743 | PCIHostState *phb; |
d0f7453d HC |
744 | PCIBonitoState *s; |
745 | PCIDevice *d; | |
746 | ||
3e80f690 | 747 | dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE); |
8558d942 | 748 | phb = PCI_HOST_BRIDGE(dev); |
c5589ee9 AF |
749 | pcihost = BONITO_PCI_HOST_BRIDGE(dev); |
750 | pcihost->pic = pic; | |
3c6ef471 | 751 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
d0f7453d | 752 | |
9307d06d | 753 | d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); |
a2a645d9 | 754 | s = PCI_BONITO(d); |
d0f7453d | 755 | s->pcihost = pcihost; |
c5589ee9 | 756 | pcihost->pci_dev = s; |
9307d06d | 757 | pci_realize_and_unref(d, phb->bus, &error_fatal); |
d0f7453d | 758 | |
c5589ee9 | 759 | return phb->bus; |
d0f7453d HC |
760 | } |
761 | ||
40021f08 AL |
762 | static void bonito_class_init(ObjectClass *klass, void *data) |
763 | { | |
39bffca2 | 764 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
765 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
766 | ||
9af21dbe | 767 | k->realize = bonito_realize; |
40021f08 AL |
768 | k->vendor_id = 0xdf53; |
769 | k->device_id = 0x00d5; | |
770 | k->revision = 0x01; | |
771 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 | 772 | dc->desc = "Host bridge"; |
39bffca2 | 773 | dc->vmsd = &vmstate_bonito; |
08c58f92 MA |
774 | /* |
775 | * PCI-facing part of the host bridge, not usable without the | |
776 | * host-facing part, which can't be device_add'ed, yet. | |
777 | */ | |
e90f2a8c | 778 | dc->user_creatable = false; |
40021f08 AL |
779 | } |
780 | ||
4240abff | 781 | static const TypeInfo bonito_info = { |
a2a645d9 | 782 | .name = TYPE_PCI_BONITO, |
39bffca2 AL |
783 | .parent = TYPE_PCI_DEVICE, |
784 | .instance_size = sizeof(PCIBonitoState), | |
785 | .class_init = bonito_class_init, | |
fd3b02c8 EH |
786 | .interfaces = (InterfaceInfo[]) { |
787 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
788 | { }, | |
789 | }, | |
d0f7453d HC |
790 | }; |
791 | ||
999e12bb AL |
792 | static void bonito_pcihost_class_init(ObjectClass *klass, void *data) |
793 | { | |
e800894a | 794 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 795 | |
e800894a | 796 | dc->realize = bonito_pcihost_realize; |
999e12bb AL |
797 | } |
798 | ||
4240abff | 799 | static const TypeInfo bonito_pcihost_info = { |
c5589ee9 | 800 | .name = TYPE_BONITO_PCI_HOST_BRIDGE, |
8558d942 | 801 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
802 | .instance_size = sizeof(BonitoState), |
803 | .class_init = bonito_pcihost_class_init, | |
d0f7453d HC |
804 | }; |
805 | ||
83f7d43a | 806 | static void bonito_register_types(void) |
d0f7453d | 807 | { |
39bffca2 AL |
808 | type_register_static(&bonito_pcihost_info); |
809 | type_register_static(&bonito_info); | |
d0f7453d | 810 | } |
83f7d43a AF |
811 | |
812 | type_init(bonito_register_types) |