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4d8fde11 AG |
1 | /* |
2 | * QEMU Generic PCI Express Bridge Emulation | |
3 | * | |
4 | * Copyright (C) 2015 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * Code loosely based on q35.c. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | * Check out these documents for more information on the device: | |
27 | * | |
28 | * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt | |
29 | * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf | |
30 | */ | |
97d5408f | 31 | #include "qemu/osdep.h" |
4d8fde11 AG |
32 | #include "hw/hw.h" |
33 | #include "hw/pci-host/gpex.h" | |
34 | ||
35 | /**************************************************************************** | |
36 | * GPEX host | |
37 | */ | |
38 | ||
39 | static void gpex_set_irq(void *opaque, int irq_num, int level) | |
40 | { | |
41 | GPEXHost *s = opaque; | |
42 | ||
43 | qemu_set_irq(s->irq[irq_num], level); | |
44 | } | |
45 | ||
70bfdce6 PS |
46 | int gpex_set_irq_num(GPEXHost *s, int index, int gsi) |
47 | { | |
48 | if (index >= GPEX_NUM_IRQS) { | |
49 | return -EINVAL; | |
50 | } | |
51 | ||
52 | s->irq_num[index] = gsi; | |
53 | return 0; | |
54 | } | |
55 | ||
d464814a PS |
56 | static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) |
57 | { | |
58 | PCIINTxRoute route; | |
59 | GPEXHost *s = opaque; | |
60 | ||
61 | route.mode = PCI_INTX_ENABLED; | |
62 | route.irq = s->irq_num[pin]; | |
63 | ||
64 | return route; | |
65 | } | |
66 | ||
4d8fde11 AG |
67 | static void gpex_host_realize(DeviceState *dev, Error **errp) |
68 | { | |
69 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); | |
70 | GPEXHost *s = GPEX_HOST(dev); | |
71 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
72 | PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); | |
73 | int i; | |
74 | ||
75 | pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); | |
76 | memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX); | |
77 | memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024); | |
78 | ||
79 | sysbus_init_mmio(sbd, &pex->mmio); | |
80 | sysbus_init_mmio(sbd, &s->io_mmio); | |
81 | sysbus_init_mmio(sbd, &s->io_ioport); | |
82 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
83 | sysbus_init_irq(sbd, &s->irq[i]); | |
84 | } | |
85 | ||
86 | pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq, | |
87 | pci_swizzle_map_irq_fn, s, &s->io_mmio, | |
88 | &s->io_ioport, 0, 4, TYPE_PCIE_BUS); | |
89 | ||
90 | qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); | |
d464814a | 91 | pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); |
4d8fde11 AG |
92 | qdev_init_nofail(DEVICE(&s->gpex_root)); |
93 | } | |
94 | ||
95 | static const char *gpex_host_root_bus_path(PCIHostState *host_bridge, | |
96 | PCIBus *rootbus) | |
97 | { | |
98 | return "0000:00"; | |
99 | } | |
100 | ||
101 | static void gpex_host_class_init(ObjectClass *klass, void *data) | |
102 | { | |
103 | DeviceClass *dc = DEVICE_CLASS(klass); | |
104 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); | |
105 | ||
106 | hc->root_bus_path = gpex_host_root_bus_path; | |
107 | dc->realize = gpex_host_realize; | |
108 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
109 | dc->fw_name = "pci"; | |
110 | } | |
111 | ||
112 | static void gpex_host_initfn(Object *obj) | |
113 | { | |
114 | GPEXHost *s = GPEX_HOST(obj); | |
115 | GPEXRootState *root = &s->gpex_root; | |
116 | ||
117 | object_initialize(root, sizeof(*root), TYPE_GPEX_ROOT_DEVICE); | |
118 | object_property_add_child(obj, "gpex_root", OBJECT(root), NULL); | |
446de8b6 | 119 | qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); |
4d8fde11 AG |
120 | qdev_prop_set_bit(DEVICE(root), "multifunction", false); |
121 | } | |
122 | ||
123 | static const TypeInfo gpex_host_info = { | |
124 | .name = TYPE_GPEX_HOST, | |
125 | .parent = TYPE_PCIE_HOST_BRIDGE, | |
126 | .instance_size = sizeof(GPEXHost), | |
127 | .instance_init = gpex_host_initfn, | |
128 | .class_init = gpex_host_class_init, | |
129 | }; | |
130 | ||
131 | /**************************************************************************** | |
132 | * GPEX Root D0:F0 | |
133 | */ | |
134 | ||
135 | static const VMStateDescription vmstate_gpex_root = { | |
136 | .name = "gpex_root", | |
137 | .version_id = 1, | |
138 | .minimum_version_id = 1, | |
139 | .fields = (VMStateField[]) { | |
140 | VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState), | |
141 | VMSTATE_END_OF_LIST() | |
142 | } | |
143 | }; | |
144 | ||
145 | static void gpex_root_class_init(ObjectClass *klass, void *data) | |
146 | { | |
147 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
148 | DeviceClass *dc = DEVICE_CLASS(klass); | |
149 | ||
150 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
151 | dc->desc = "QEMU generic PCIe host bridge"; | |
152 | dc->vmsd = &vmstate_gpex_root; | |
153 | k->vendor_id = PCI_VENDOR_ID_REDHAT; | |
154 | k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST; | |
155 | k->revision = 0; | |
156 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
157 | /* | |
158 | * PCI-facing part of the host bridge, not usable without the | |
159 | * host-facing part, which can't be device_add'ed, yet. | |
160 | */ | |
e90f2a8c | 161 | dc->user_creatable = false; |
4d8fde11 AG |
162 | } |
163 | ||
164 | static const TypeInfo gpex_root_info = { | |
165 | .name = TYPE_GPEX_ROOT_DEVICE, | |
166 | .parent = TYPE_PCI_DEVICE, | |
167 | .instance_size = sizeof(GPEXRootState), | |
168 | .class_init = gpex_root_class_init, | |
fd3b02c8 EH |
169 | .interfaces = (InterfaceInfo[]) { |
170 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
171 | { }, | |
172 | }, | |
4d8fde11 AG |
173 | }; |
174 | ||
175 | static void gpex_register(void) | |
176 | { | |
177 | type_register_static(&gpex_root_info); | |
178 | type_register_static(&gpex_host_info); | |
179 | } | |
180 | ||
181 | type_init(gpex_register) |