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dcdf98a9 BZ |
1 | /* |
2 | * Marvell Discovery II MV64361 System Controller for | |
3 | * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator | |
4 | * | |
5 | * Copyright (c) 2018-2020 BALATON Zoltan | |
6 | * | |
7 | * This work is licensed under the GNU GPL license version 2 or later. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include "qemu/osdep.h" | |
dcdf98a9 BZ |
12 | #include "qemu/units.h" |
13 | #include "qapi/error.h" | |
14 | #include "hw/hw.h" | |
15 | #include "hw/sysbus.h" | |
16 | #include "hw/pci/pci.h" | |
17 | #include "hw/pci/pci_host.h" | |
18 | #include "hw/irq.h" | |
19 | #include "hw/intc/i8259.h" | |
20 | #include "hw/qdev-properties.h" | |
21 | #include "exec/address-spaces.h" | |
22 | #include "qemu/log.h" | |
23 | #include "qemu/error-report.h" | |
24 | #include "trace.h" | |
25 | #include "hw/pci-host/mv64361.h" | |
26 | #include "mv643xx.h" | |
27 | ||
28 | #define TYPE_MV64361_PCI_BRIDGE "mv64361-pcibridge" | |
29 | ||
30 | static void mv64361_pcibridge_class_init(ObjectClass *klass, void *data) | |
31 | { | |
32 | DeviceClass *dc = DEVICE_CLASS(klass); | |
33 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
34 | ||
35 | k->vendor_id = PCI_VENDOR_ID_MARVELL; | |
36 | k->device_id = PCI_DEVICE_ID_MARVELL_MV6436X; | |
37 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
38 | /* | |
39 | * PCI-facing part of the host bridge, | |
40 | * not usable without the host-facing part | |
41 | */ | |
42 | dc->user_creatable = false; | |
43 | } | |
44 | ||
45 | static const TypeInfo mv64361_pcibridge_info = { | |
46 | .name = TYPE_MV64361_PCI_BRIDGE, | |
47 | .parent = TYPE_PCI_DEVICE, | |
48 | .instance_size = sizeof(PCIDevice), | |
49 | .class_init = mv64361_pcibridge_class_init, | |
50 | .interfaces = (InterfaceInfo[]) { | |
51 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
52 | { }, | |
53 | }, | |
54 | }; | |
55 | ||
56 | ||
57 | #define TYPE_MV64361_PCI "mv64361-pcihost" | |
58 | OBJECT_DECLARE_SIMPLE_TYPE(MV64361PCIState, MV64361_PCI) | |
59 | ||
60 | struct MV64361PCIState { | |
61 | PCIHostState parent_obj; | |
62 | ||
63 | uint8_t index; | |
64 | MemoryRegion io; | |
65 | MemoryRegion mem; | |
66 | qemu_irq irq[PCI_NUM_PINS]; | |
67 | ||
68 | uint32_t io_base; | |
69 | uint32_t io_size; | |
70 | uint32_t mem_base[4]; | |
71 | uint32_t mem_size[4]; | |
72 | uint64_t remap[5]; | |
73 | }; | |
74 | ||
75 | static int mv64361_pcihost_map_irq(PCIDevice *pci_dev, int n) | |
76 | { | |
77 | return (n + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; | |
78 | } | |
79 | ||
80 | static void mv64361_pcihost_set_irq(void *opaque, int n, int level) | |
81 | { | |
82 | MV64361PCIState *s = opaque; | |
83 | qemu_set_irq(s->irq[n], level); | |
84 | } | |
85 | ||
86 | static void mv64361_pcihost_realize(DeviceState *dev, Error **errp) | |
87 | { | |
88 | MV64361PCIState *s = MV64361_PCI(dev); | |
89 | PCIHostState *h = PCI_HOST_BRIDGE(dev); | |
90 | char *name; | |
91 | ||
92 | name = g_strdup_printf("pci%d-io", s->index); | |
93 | memory_region_init(&s->io, OBJECT(dev), name, 0x10000); | |
94 | g_free(name); | |
95 | name = g_strdup_printf("pci%d-mem", s->index); | |
96 | memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32); | |
97 | g_free(name); | |
98 | name = g_strdup_printf("pci.%d", s->index); | |
99 | h->bus = pci_register_root_bus(dev, name, mv64361_pcihost_set_irq, | |
100 | mv64361_pcihost_map_irq, dev, | |
101 | &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); | |
102 | g_free(name); | |
103 | pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); | |
104 | } | |
105 | ||
106 | static Property mv64361_pcihost_props[] = { | |
107 | DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0), | |
108 | DEFINE_PROP_END_OF_LIST() | |
109 | }; | |
110 | ||
111 | static void mv64361_pcihost_class_init(ObjectClass *klass, void *data) | |
112 | { | |
113 | DeviceClass *dc = DEVICE_CLASS(klass); | |
114 | ||
115 | dc->realize = mv64361_pcihost_realize; | |
116 | device_class_set_props(dc, mv64361_pcihost_props); | |
117 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
118 | } | |
119 | ||
120 | static const TypeInfo mv64361_pcihost_info = { | |
121 | .name = TYPE_MV64361_PCI, | |
122 | .parent = TYPE_PCI_HOST_BRIDGE, | |
123 | .instance_size = sizeof(MV64361PCIState), | |
124 | .class_init = mv64361_pcihost_class_init, | |
125 | }; | |
126 | ||
127 | static void mv64361_pci_register_types(void) | |
128 | { | |
129 | type_register_static(&mv64361_pcihost_info); | |
130 | type_register_static(&mv64361_pcibridge_info); | |
131 | } | |
132 | ||
133 | type_init(mv64361_pci_register_types) | |
134 | ||
135 | ||
136 | OBJECT_DECLARE_SIMPLE_TYPE(MV64361State, MV64361) | |
137 | ||
138 | struct MV64361State { | |
139 | SysBusDevice parent_obj; | |
140 | ||
141 | MemoryRegion regs; | |
142 | MV64361PCIState pci[2]; | |
143 | MemoryRegion cpu_win[19]; | |
144 | qemu_irq cpu_irq; | |
145 | ||
146 | /* registers state */ | |
147 | uint32_t cpu_conf; | |
148 | uint32_t regs_base; | |
149 | uint32_t base_addr_enable; | |
150 | uint64_t main_int_cr; | |
151 | uint64_t cpu0_int_mask; | |
152 | uint32_t gpp_io; | |
153 | uint32_t gpp_level; | |
154 | uint32_t gpp_value; | |
155 | uint32_t gpp_int_cr; | |
156 | uint32_t gpp_int_mask; | |
157 | bool gpp_int_level; | |
158 | }; | |
159 | ||
160 | enum mv64361_irq_cause { | |
161 | MV64361_IRQ_DEVERR = 1, | |
162 | MV64361_IRQ_DMAERR = 2, | |
163 | MV64361_IRQ_CPUERR = 3, | |
164 | MV64361_IRQ_IDMA0 = 4, | |
165 | MV64361_IRQ_IDMA1 = 5, | |
166 | MV64361_IRQ_IDMA2 = 6, | |
167 | MV64361_IRQ_IDMA3 = 7, | |
168 | MV64361_IRQ_TIMER0 = 8, | |
169 | MV64361_IRQ_TIMER1 = 9, | |
170 | MV64361_IRQ_TIMER2 = 10, | |
171 | MV64361_IRQ_TIMER3 = 11, | |
172 | MV64361_IRQ_PCI0 = 12, | |
173 | MV64361_IRQ_SRAMERR = 13, | |
174 | MV64361_IRQ_GBEERR = 14, | |
175 | MV64361_IRQ_CERR = 15, | |
176 | MV64361_IRQ_PCI1 = 16, | |
177 | MV64361_IRQ_DRAMERR = 17, | |
178 | MV64361_IRQ_WDNMI = 18, | |
179 | MV64361_IRQ_WDE = 19, | |
180 | MV64361_IRQ_PCI0IN = 20, | |
181 | MV64361_IRQ_PCI0OUT = 21, | |
182 | MV64361_IRQ_PCI1IN = 22, | |
183 | MV64361_IRQ_PCI1OUT = 23, | |
184 | MV64361_IRQ_P1_GPP0_7 = 24, | |
185 | MV64361_IRQ_P1_GPP8_15 = 25, | |
186 | MV64361_IRQ_P1_GPP16_23 = 26, | |
187 | MV64361_IRQ_P1_GPP24_31 = 27, | |
188 | MV64361_IRQ_P1_CPU_DB = 28, | |
189 | /* 29-31: reserved */ | |
190 | MV64361_IRQ_GBE0 = 32, | |
191 | MV64361_IRQ_GBE1 = 33, | |
192 | MV64361_IRQ_GBE2 = 34, | |
193 | /* 35: reserved */ | |
194 | MV64361_IRQ_SDMA0 = 36, | |
195 | MV64361_IRQ_TWSI = 37, | |
196 | MV64361_IRQ_SDMA1 = 38, | |
197 | MV64361_IRQ_BRG = 39, | |
198 | MV64361_IRQ_MPSC0 = 40, | |
199 | MV64361_IRQ_MPSC1 = 41, | |
200 | MV64361_IRQ_G0RX = 42, | |
201 | MV64361_IRQ_G0TX = 43, | |
202 | MV64361_IRQ_G0MISC = 44, | |
203 | MV64361_IRQ_G1RX = 45, | |
204 | MV64361_IRQ_G1TX = 46, | |
205 | MV64361_IRQ_G1MISC = 47, | |
206 | MV64361_IRQ_G2RX = 48, | |
207 | MV64361_IRQ_G2TX = 49, | |
208 | MV64361_IRQ_G2MISC = 50, | |
209 | /* 51-55: reserved */ | |
210 | MV64361_IRQ_P0_GPP0_7 = 56, | |
211 | MV64361_IRQ_P0_GPP8_15 = 57, | |
212 | MV64361_IRQ_P0_GPP16_23 = 58, | |
213 | MV64361_IRQ_P0_GPP24_31 = 59, | |
214 | MV64361_IRQ_P0_CPU_DB = 60, | |
215 | /* 61-63: reserved */ | |
216 | }; | |
217 | ||
218 | PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n) | |
219 | { | |
220 | MV64361State *mv = MV64361(dev); | |
221 | return PCI_HOST_BRIDGE(&mv->pci[n])->bus; | |
222 | } | |
223 | ||
224 | static void unmap_region(MemoryRegion *mr) | |
225 | { | |
226 | if (memory_region_is_mapped(mr)) { | |
227 | memory_region_del_subregion(get_system_memory(), mr); | |
228 | object_unparent(OBJECT(mr)); | |
229 | } | |
230 | } | |
231 | ||
232 | static void map_pci_region(MemoryRegion *mr, MemoryRegion *parent, | |
233 | struct Object *owner, const char *name, | |
234 | hwaddr poffs, uint64_t size, hwaddr moffs) | |
235 | { | |
236 | memory_region_init_alias(mr, owner, name, parent, poffs, size); | |
237 | memory_region_add_subregion(get_system_memory(), moffs, mr); | |
238 | trace_mv64361_region_map(name, poffs, size, moffs); | |
239 | } | |
240 | ||
241 | static void set_mem_windows(MV64361State *s, uint32_t val) | |
242 | { | |
243 | MV64361PCIState *p; | |
244 | MemoryRegion *mr; | |
245 | uint32_t mask; | |
246 | int i; | |
247 | ||
248 | val &= 0x1fffff; | |
249 | for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { | |
250 | if ((val & mask) != (s->base_addr_enable & mask)) { | |
251 | trace_mv64361_region_enable(!(val & mask) ? "enable" : "disable", i); | |
252 | /* | |
253 | * 0-3 are SDRAM chip selects but we map all RAM directly | |
254 | * 4-7 are device chip selects (not sure what those are) | |
255 | * 8 is Boot device (ROM) chip select but we map that directly too | |
256 | */ | |
257 | if (i == 9) { | |
258 | p = &s->pci[0]; | |
259 | mr = &s->cpu_win[i]; | |
260 | unmap_region(mr); | |
261 | if (!(val & mask)) { | |
262 | map_pci_region(mr, &p->io, OBJECT(s), "pci0-io-win", | |
263 | p->remap[4], (p->io_size + 1) << 16, | |
264 | (p->io_base & 0xfffff) << 16); | |
265 | } | |
266 | } else if (i == 10) { | |
267 | p = &s->pci[0]; | |
268 | mr = &s->cpu_win[i]; | |
269 | unmap_region(mr); | |
270 | if (!(val & mask)) { | |
271 | map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem0-win", | |
272 | p->remap[0], (p->mem_size[0] + 1) << 16, | |
273 | (p->mem_base[0] & 0xfffff) << 16); | |
274 | } | |
275 | } else if (i == 11) { | |
276 | p = &s->pci[0]; | |
277 | mr = &s->cpu_win[i]; | |
278 | unmap_region(mr); | |
279 | if (!(val & mask)) { | |
280 | map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem1-win", | |
281 | p->remap[1], (p->mem_size[1] + 1) << 16, | |
282 | (p->mem_base[1] & 0xfffff) << 16); | |
283 | } | |
284 | } else if (i == 12) { | |
285 | p = &s->pci[0]; | |
286 | mr = &s->cpu_win[i]; | |
287 | unmap_region(mr); | |
288 | if (!(val & mask)) { | |
289 | map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem2-win", | |
290 | p->remap[2], (p->mem_size[2] + 1) << 16, | |
291 | (p->mem_base[2] & 0xfffff) << 16); | |
292 | } | |
293 | } else if (i == 13) { | |
294 | p = &s->pci[0]; | |
295 | mr = &s->cpu_win[i]; | |
296 | unmap_region(mr); | |
297 | if (!(val & mask)) { | |
298 | map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem3-win", | |
299 | p->remap[3], (p->mem_size[3] + 1) << 16, | |
300 | (p->mem_base[3] & 0xfffff) << 16); | |
301 | } | |
302 | } else if (i == 14) { | |
303 | p = &s->pci[1]; | |
304 | mr = &s->cpu_win[i]; | |
305 | unmap_region(mr); | |
306 | if (!(val & mask)) { | |
307 | map_pci_region(mr, &p->io, OBJECT(s), "pci1-io-win", | |
308 | p->remap[4], (p->io_size + 1) << 16, | |
309 | (p->io_base & 0xfffff) << 16); | |
310 | } | |
311 | } else if (i == 15) { | |
312 | p = &s->pci[1]; | |
313 | mr = &s->cpu_win[i]; | |
314 | unmap_region(mr); | |
315 | if (!(val & mask)) { | |
316 | map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem0-win", | |
317 | p->remap[0], (p->mem_size[0] + 1) << 16, | |
318 | (p->mem_base[0] & 0xfffff) << 16); | |
319 | } | |
320 | } else if (i == 16) { | |
321 | p = &s->pci[1]; | |
322 | mr = &s->cpu_win[i]; | |
323 | unmap_region(mr); | |
324 | if (!(val & mask)) { | |
325 | map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem1-win", | |
326 | p->remap[1], (p->mem_size[1] + 1) << 16, | |
327 | (p->mem_base[1] & 0xfffff) << 16); | |
328 | } | |
329 | } else if (i == 17) { | |
330 | p = &s->pci[1]; | |
331 | mr = &s->cpu_win[i]; | |
332 | unmap_region(mr); | |
333 | if (!(val & mask)) { | |
334 | map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem2-win", | |
335 | p->remap[2], (p->mem_size[2] + 1) << 16, | |
336 | (p->mem_base[2] & 0xfffff) << 16); | |
337 | } | |
338 | } else if (i == 18) { | |
339 | p = &s->pci[1]; | |
340 | mr = &s->cpu_win[i]; | |
341 | unmap_region(mr); | |
342 | if (!(val & mask)) { | |
343 | map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem3-win", | |
344 | p->remap[3], (p->mem_size[3] + 1) << 16, | |
345 | (p->mem_base[3] & 0xfffff) << 16); | |
346 | } | |
347 | /* 19 is integrated SRAM */ | |
348 | } else if (i == 20) { | |
349 | mr = &s->regs; | |
350 | unmap_region(mr); | |
351 | if (!(val & mask)) { | |
352 | memory_region_add_subregion(get_system_memory(), | |
353 | (s->regs_base & 0xfffff) << 16, mr); | |
354 | } | |
355 | } | |
356 | } | |
357 | } | |
358 | s->base_addr_enable = val; | |
359 | } | |
360 | ||
361 | static void mv64361_update_irq(void *opaque, int n, int level) | |
362 | { | |
363 | MV64361State *s = opaque; | |
364 | uint64_t val = s->main_int_cr; | |
365 | ||
366 | if (level) { | |
367 | val |= BIT_ULL(n); | |
368 | } else { | |
369 | val &= ~BIT_ULL(n); | |
370 | } | |
371 | if ((s->main_int_cr & s->cpu0_int_mask) != (val & s->cpu0_int_mask)) { | |
372 | qemu_set_irq(s->cpu_irq, level); | |
373 | } | |
374 | s->main_int_cr = val; | |
375 | } | |
376 | ||
377 | static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size) | |
378 | { | |
379 | MV64361State *s = MV64361(opaque); | |
380 | uint32_t ret = 0; | |
381 | ||
382 | switch (addr) { | |
383 | case MV64340_CPU_CONFIG: | |
384 | ret = s->cpu_conf; | |
385 | break; | |
386 | case MV64340_PCI_0_IO_BASE_ADDR: | |
387 | ret = s->pci[0].io_base; | |
388 | break; | |
389 | case MV64340_PCI_0_IO_SIZE: | |
390 | ret = s->pci[0].io_size; | |
391 | break; | |
392 | case MV64340_PCI_0_IO_ADDR_REMAP: | |
393 | ret = s->pci[0].remap[4] >> 16; | |
394 | break; | |
395 | case MV64340_PCI_0_MEMORY0_BASE_ADDR: | |
396 | ret = s->pci[0].mem_base[0]; | |
397 | break; | |
398 | case MV64340_PCI_0_MEMORY0_SIZE: | |
399 | ret = s->pci[0].mem_size[0]; | |
400 | break; | |
401 | case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP: | |
402 | ret = (s->pci[0].remap[0] & 0xffff0000) >> 16; | |
403 | break; | |
404 | case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP: | |
405 | ret = s->pci[0].remap[0] >> 32; | |
406 | break; | |
407 | case MV64340_PCI_0_MEMORY1_BASE_ADDR: | |
408 | ret = s->pci[0].mem_base[1]; | |
409 | break; | |
410 | case MV64340_PCI_0_MEMORY1_SIZE: | |
411 | ret = s->pci[0].mem_size[1]; | |
412 | break; | |
413 | case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP: | |
414 | ret = (s->pci[0].remap[1] & 0xffff0000) >> 16; | |
415 | break; | |
416 | case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP: | |
417 | ret = s->pci[0].remap[1] >> 32; | |
418 | break; | |
419 | case MV64340_PCI_0_MEMORY2_BASE_ADDR: | |
420 | ret = s->pci[0].mem_base[2]; | |
421 | break; | |
422 | case MV64340_PCI_0_MEMORY2_SIZE: | |
423 | ret = s->pci[0].mem_size[2]; | |
424 | break; | |
425 | case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP: | |
426 | ret = (s->pci[0].remap[2] & 0xffff0000) >> 16; | |
427 | break; | |
428 | case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP: | |
429 | ret = s->pci[0].remap[2] >> 32; | |
430 | break; | |
431 | case MV64340_PCI_0_MEMORY3_BASE_ADDR: | |
432 | ret = s->pci[0].mem_base[3]; | |
433 | break; | |
434 | case MV64340_PCI_0_MEMORY3_SIZE: | |
435 | ret = s->pci[0].mem_size[3]; | |
436 | break; | |
437 | case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP: | |
438 | ret = (s->pci[0].remap[3] & 0xffff0000) >> 16; | |
439 | break; | |
440 | case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP: | |
441 | ret = s->pci[0].remap[3] >> 32; | |
442 | break; | |
443 | case MV64340_PCI_1_IO_BASE_ADDR: | |
444 | ret = s->pci[1].io_base; | |
445 | break; | |
446 | case MV64340_PCI_1_IO_SIZE: | |
447 | ret = s->pci[1].io_size; | |
448 | break; | |
449 | case MV64340_PCI_1_IO_ADDR_REMAP: | |
450 | ret = s->pci[1].remap[4] >> 16; | |
451 | break; | |
452 | case MV64340_PCI_1_MEMORY0_BASE_ADDR: | |
453 | ret = s->pci[1].mem_base[0]; | |
454 | break; | |
455 | case MV64340_PCI_1_MEMORY0_SIZE: | |
456 | ret = s->pci[1].mem_size[0]; | |
457 | break; | |
458 | case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP: | |
459 | ret = (s->pci[1].remap[0] & 0xffff0000) >> 16; | |
460 | break; | |
461 | case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP: | |
462 | ret = s->pci[1].remap[0] >> 32; | |
463 | break; | |
464 | case MV64340_PCI_1_MEMORY1_BASE_ADDR: | |
465 | ret = s->pci[1].mem_base[1]; | |
466 | break; | |
467 | case MV64340_PCI_1_MEMORY1_SIZE: | |
468 | ret = s->pci[1].mem_size[1]; | |
469 | break; | |
470 | case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP: | |
471 | ret = (s->pci[1].remap[1] & 0xffff0000) >> 16; | |
472 | break; | |
473 | case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP: | |
474 | ret = s->pci[1].remap[1] >> 32; | |
475 | break; | |
476 | case MV64340_PCI_1_MEMORY2_BASE_ADDR: | |
477 | ret = s->pci[1].mem_base[2]; | |
478 | break; | |
479 | case MV64340_PCI_1_MEMORY2_SIZE: | |
480 | ret = s->pci[1].mem_size[2]; | |
481 | break; | |
482 | case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP: | |
483 | ret = (s->pci[1].remap[2] & 0xffff0000) >> 16; | |
484 | break; | |
485 | case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP: | |
486 | ret = s->pci[1].remap[2] >> 32; | |
487 | break; | |
488 | case MV64340_PCI_1_MEMORY3_BASE_ADDR: | |
489 | ret = s->pci[1].mem_base[3]; | |
490 | break; | |
491 | case MV64340_PCI_1_MEMORY3_SIZE: | |
492 | ret = s->pci[1].mem_size[3]; | |
493 | break; | |
494 | case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP: | |
495 | ret = (s->pci[1].remap[3] & 0xffff0000) >> 16; | |
496 | break; | |
497 | case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP: | |
498 | ret = s->pci[1].remap[3] >> 32; | |
499 | break; | |
500 | case MV64340_INTERNAL_SPACE_BASE_ADDR: | |
501 | ret = s->regs_base; | |
502 | break; | |
503 | case MV64340_BASE_ADDR_ENABLE: | |
504 | ret = s->base_addr_enable; | |
505 | break; | |
506 | case MV64340_PCI_0_CONFIG_ADDR: | |
507 | ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), 0, size); | |
508 | break; | |
509 | case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ... | |
510 | MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3: | |
511 | ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), | |
512 | addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, size); | |
513 | break; | |
514 | case MV64340_PCI_1_CONFIG_ADDR: | |
515 | ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size); | |
516 | break; | |
517 | case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ... | |
518 | MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3: | |
519 | ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), | |
520 | addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, size); | |
521 | break; | |
522 | case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG: | |
523 | /* FIXME: Should this be sent via the PCI bus somehow? */ | |
524 | if (s->gpp_int_level && (s->gpp_value & BIT(31))) { | |
525 | ret = pic_read_irq(isa_pic); | |
526 | } | |
527 | break; | |
528 | case MV64340_MAIN_INTERRUPT_CAUSE_LOW: | |
529 | ret = s->main_int_cr; | |
530 | break; | |
531 | case MV64340_MAIN_INTERRUPT_CAUSE_HIGH: | |
532 | ret = s->main_int_cr >> 32; | |
533 | break; | |
534 | case MV64340_CPU_INTERRUPT0_MASK_LOW: | |
535 | ret = s->cpu0_int_mask; | |
536 | break; | |
537 | case MV64340_CPU_INTERRUPT0_MASK_HIGH: | |
538 | ret = s->cpu0_int_mask >> 32; | |
539 | break; | |
540 | case MV64340_CPU_INTERRUPT0_SELECT_CAUSE: | |
541 | ret = s->main_int_cr; | |
542 | if (s->main_int_cr & s->cpu0_int_mask) { | |
543 | if (!(s->main_int_cr & s->cpu0_int_mask & 0xffffffff)) { | |
544 | ret = s->main_int_cr >> 32 | BIT(30); | |
545 | } else if ((s->main_int_cr & s->cpu0_int_mask) >> 32) { | |
546 | ret |= BIT(31); | |
547 | } | |
548 | } | |
549 | break; | |
550 | case MV64340_CUNIT_ARBITER_CONTROL_REG: | |
551 | ret = 0x11ff0000 | (s->gpp_int_level << 10); | |
552 | break; | |
553 | case MV64340_GPP_IO_CONTROL: | |
554 | ret = s->gpp_io; | |
555 | break; | |
556 | case MV64340_GPP_LEVEL_CONTROL: | |
557 | ret = s->gpp_level; | |
558 | break; | |
559 | case MV64340_GPP_VALUE: | |
560 | ret = s->gpp_value; | |
561 | break; | |
562 | case MV64340_GPP_VALUE_SET: | |
563 | case MV64340_GPP_VALUE_CLEAR: | |
564 | ret = 0; | |
565 | break; | |
566 | case MV64340_GPP_INTERRUPT_CAUSE: | |
567 | ret = s->gpp_int_cr; | |
568 | break; | |
569 | case MV64340_GPP_INTERRUPT_MASK0: | |
570 | case MV64340_GPP_INTERRUPT_MASK1: | |
571 | ret = s->gpp_int_mask; | |
572 | break; | |
573 | default: | |
574 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%" | |
575 | HWADDR_PRIx "\n", __func__, addr); | |
576 | break; | |
577 | } | |
578 | if (addr != MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG) { | |
579 | trace_mv64361_reg_read(addr, ret); | |
580 | } | |
581 | return ret; | |
582 | } | |
583 | ||
584 | static void warn_swap_bit(uint64_t val) | |
585 | { | |
586 | if ((val & 0x3000000ULL) >> 24 != 1) { | |
587 | qemu_log_mask(LOG_UNIMP, "%s: Data swap not implemented", __func__); | |
588 | } | |
589 | } | |
590 | ||
591 | static void mv64361_set_pci_mem_remap(MV64361State *s, int bus, int idx, | |
592 | uint64_t val, bool high) | |
593 | { | |
594 | if (high) { | |
595 | s->pci[bus].remap[idx] = val; | |
596 | } else { | |
597 | s->pci[bus].remap[idx] &= 0xffffffff00000000ULL; | |
598 | s->pci[bus].remap[idx] |= (val & 0xffffULL) << 16; | |
599 | } | |
600 | } | |
601 | ||
602 | static void mv64361_write(void *opaque, hwaddr addr, uint64_t val, | |
603 | unsigned int size) | |
604 | { | |
605 | MV64361State *s = MV64361(opaque); | |
606 | ||
607 | trace_mv64361_reg_write(addr, val); | |
608 | switch (addr) { | |
609 | case MV64340_CPU_CONFIG: | |
610 | s->cpu_conf = val & 0xe4e3bffULL; | |
611 | s->cpu_conf |= BIT(23); | |
612 | break; | |
613 | case MV64340_PCI_0_IO_BASE_ADDR: | |
614 | s->pci[0].io_base = val & 0x30fffffULL; | |
615 | warn_swap_bit(val); | |
616 | if (!(s->cpu_conf & BIT(27))) { | |
617 | s->pci[0].remap[4] = (val & 0xffffULL) << 16; | |
618 | } | |
619 | break; | |
620 | case MV64340_PCI_0_IO_SIZE: | |
621 | s->pci[0].io_size = val & 0xffffULL; | |
622 | break; | |
623 | case MV64340_PCI_0_IO_ADDR_REMAP: | |
624 | s->pci[0].remap[4] = (val & 0xffffULL) << 16; | |
625 | break; | |
626 | case MV64340_PCI_0_MEMORY0_BASE_ADDR: | |
627 | s->pci[0].mem_base[0] = val & 0x70fffffULL; | |
628 | warn_swap_bit(val); | |
629 | if (!(s->cpu_conf & BIT(27))) { | |
630 | mv64361_set_pci_mem_remap(s, 0, 0, val, false); | |
631 | } | |
632 | break; | |
633 | case MV64340_PCI_0_MEMORY0_SIZE: | |
634 | s->pci[0].mem_size[0] = val & 0xffffULL; | |
635 | break; | |
636 | case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP: | |
637 | case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP: | |
638 | mv64361_set_pci_mem_remap(s, 0, 0, val, | |
639 | (addr == MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP)); | |
640 | break; | |
641 | case MV64340_PCI_0_MEMORY1_BASE_ADDR: | |
642 | s->pci[0].mem_base[1] = val & 0x70fffffULL; | |
643 | warn_swap_bit(val); | |
644 | if (!(s->cpu_conf & BIT(27))) { | |
645 | mv64361_set_pci_mem_remap(s, 0, 1, val, false); | |
646 | } | |
647 | break; | |
648 | case MV64340_PCI_0_MEMORY1_SIZE: | |
649 | s->pci[0].mem_size[1] = val & 0xffffULL; | |
650 | break; | |
651 | case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP: | |
652 | case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP: | |
653 | mv64361_set_pci_mem_remap(s, 0, 1, val, | |
654 | (addr == MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP)); | |
655 | break; | |
656 | case MV64340_PCI_0_MEMORY2_BASE_ADDR: | |
657 | s->pci[0].mem_base[2] = val & 0x70fffffULL; | |
658 | warn_swap_bit(val); | |
659 | if (!(s->cpu_conf & BIT(27))) { | |
660 | mv64361_set_pci_mem_remap(s, 0, 2, val, false); | |
661 | } | |
662 | break; | |
663 | case MV64340_PCI_0_MEMORY2_SIZE: | |
664 | s->pci[0].mem_size[2] = val & 0xffffULL; | |
665 | break; | |
666 | case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP: | |
667 | case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP: | |
668 | mv64361_set_pci_mem_remap(s, 0, 2, val, | |
669 | (addr == MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP)); | |
670 | break; | |
671 | case MV64340_PCI_0_MEMORY3_BASE_ADDR: | |
672 | s->pci[0].mem_base[3] = val & 0x70fffffULL; | |
673 | warn_swap_bit(val); | |
674 | if (!(s->cpu_conf & BIT(27))) { | |
675 | mv64361_set_pci_mem_remap(s, 0, 3, val, false); | |
676 | } | |
677 | break; | |
678 | case MV64340_PCI_0_MEMORY3_SIZE: | |
679 | s->pci[0].mem_size[3] = val & 0xffffULL; | |
680 | break; | |
681 | case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP: | |
682 | case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP: | |
683 | mv64361_set_pci_mem_remap(s, 0, 3, val, | |
684 | (addr == MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP)); | |
685 | break; | |
686 | case MV64340_PCI_1_IO_BASE_ADDR: | |
687 | s->pci[1].io_base = val & 0x30fffffULL; | |
688 | warn_swap_bit(val); | |
dcdf98a9 BZ |
689 | if (!(s->cpu_conf & BIT(27))) { |
690 | s->pci[1].remap[4] = (val & 0xffffULL) << 16; | |
691 | } | |
692 | break; | |
693 | case MV64340_PCI_1_IO_SIZE: | |
694 | s->pci[1].io_size = val & 0xffffULL; | |
695 | break; | |
696 | case MV64340_PCI_1_MEMORY0_BASE_ADDR: | |
697 | s->pci[1].mem_base[0] = val & 0x70fffffULL; | |
698 | warn_swap_bit(val); | |
699 | if (!(s->cpu_conf & BIT(27))) { | |
700 | mv64361_set_pci_mem_remap(s, 1, 0, val, false); | |
701 | } | |
702 | break; | |
703 | case MV64340_PCI_1_MEMORY0_SIZE: | |
704 | s->pci[1].mem_size[0] = val & 0xffffULL; | |
705 | break; | |
706 | case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP: | |
707 | case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP: | |
708 | mv64361_set_pci_mem_remap(s, 1, 0, val, | |
709 | (addr == MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP)); | |
710 | break; | |
711 | case MV64340_PCI_1_MEMORY1_BASE_ADDR: | |
712 | s->pci[1].mem_base[1] = val & 0x70fffffULL; | |
713 | warn_swap_bit(val); | |
714 | if (!(s->cpu_conf & BIT(27))) { | |
715 | mv64361_set_pci_mem_remap(s, 1, 1, val, false); | |
716 | } | |
717 | break; | |
718 | case MV64340_PCI_1_MEMORY1_SIZE: | |
719 | s->pci[1].mem_size[1] = val & 0xffffULL; | |
720 | break; | |
721 | case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP: | |
722 | case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP: | |
723 | mv64361_set_pci_mem_remap(s, 1, 1, val, | |
724 | (addr == MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP)); | |
725 | break; | |
726 | case MV64340_PCI_1_MEMORY2_BASE_ADDR: | |
727 | s->pci[1].mem_base[2] = val & 0x70fffffULL; | |
728 | warn_swap_bit(val); | |
729 | if (!(s->cpu_conf & BIT(27))) { | |
730 | mv64361_set_pci_mem_remap(s, 1, 2, val, false); | |
731 | } | |
732 | break; | |
733 | case MV64340_PCI_1_MEMORY2_SIZE: | |
734 | s->pci[1].mem_size[2] = val & 0xffffULL; | |
735 | break; | |
736 | case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP: | |
737 | case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP: | |
738 | mv64361_set_pci_mem_remap(s, 1, 2, val, | |
739 | (addr == MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP)); | |
740 | break; | |
741 | case MV64340_PCI_1_MEMORY3_BASE_ADDR: | |
742 | s->pci[1].mem_base[3] = val & 0x70fffffULL; | |
743 | warn_swap_bit(val); | |
744 | if (!(s->cpu_conf & BIT(27))) { | |
745 | mv64361_set_pci_mem_remap(s, 1, 3, val, false); | |
746 | } | |
747 | break; | |
748 | case MV64340_PCI_1_MEMORY3_SIZE: | |
749 | s->pci[1].mem_size[3] = val & 0xffffULL; | |
750 | break; | |
751 | case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP: | |
752 | case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP: | |
753 | mv64361_set_pci_mem_remap(s, 1, 3, val, | |
754 | (addr == MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP)); | |
755 | break; | |
756 | case MV64340_INTERNAL_SPACE_BASE_ADDR: | |
757 | s->regs_base = val & 0xfffffULL; | |
758 | break; | |
759 | case MV64340_BASE_ADDR_ENABLE: | |
760 | set_mem_windows(s, val); | |
761 | break; | |
762 | case MV64340_PCI_0_CONFIG_ADDR: | |
763 | pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), 0, val, size); | |
764 | break; | |
765 | case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ... | |
766 | MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3: | |
767 | pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), | |
768 | addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, val, size); | |
769 | break; | |
770 | case MV64340_PCI_1_CONFIG_ADDR: | |
771 | pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size); | |
772 | break; | |
773 | case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ... | |
774 | MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3: | |
775 | pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), | |
776 | addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, val, size); | |
777 | break; | |
778 | case MV64340_CPU_INTERRUPT0_MASK_LOW: | |
779 | s->cpu0_int_mask &= 0xffffffff00000000ULL; | |
780 | s->cpu0_int_mask |= val & 0xffffffffULL; | |
781 | break; | |
782 | case MV64340_CPU_INTERRUPT0_MASK_HIGH: | |
783 | s->cpu0_int_mask &= 0xffffffffULL; | |
784 | s->cpu0_int_mask |= val << 32; | |
785 | break; | |
786 | case MV64340_CUNIT_ARBITER_CONTROL_REG: | |
787 | s->gpp_int_level = !!(val & BIT(10)); | |
788 | break; | |
789 | case MV64340_GPP_IO_CONTROL: | |
790 | s->gpp_io = val; | |
791 | break; | |
792 | case MV64340_GPP_LEVEL_CONTROL: | |
793 | s->gpp_level = val; | |
794 | break; | |
795 | case MV64340_GPP_VALUE: | |
796 | s->gpp_value &= ~s->gpp_io; | |
797 | s->gpp_value |= val & s->gpp_io; | |
798 | break; | |
799 | case MV64340_GPP_VALUE_SET: | |
800 | s->gpp_value |= val & s->gpp_io; | |
801 | break; | |
802 | case MV64340_GPP_VALUE_CLEAR: | |
803 | s->gpp_value &= ~(val & s->gpp_io); | |
804 | break; | |
805 | case MV64340_GPP_INTERRUPT_CAUSE: | |
806 | if (!s->gpp_int_level && val != s->gpp_int_cr) { | |
807 | int i; | |
808 | uint32_t ch = s->gpp_int_cr ^ val; | |
809 | s->gpp_int_cr = val; | |
810 | for (i = 0; i < 4; i++) { | |
811 | if ((ch & 0xff << i) && !(val & 0xff << i)) { | |
812 | mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + i, 0); | |
813 | } | |
814 | } | |
815 | } else { | |
816 | s->gpp_int_cr = val; | |
817 | } | |
818 | break; | |
819 | case MV64340_GPP_INTERRUPT_MASK0: | |
820 | case MV64340_GPP_INTERRUPT_MASK1: | |
821 | s->gpp_int_mask = val; | |
822 | break; | |
823 | default: | |
824 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%" | |
825 | HWADDR_PRIx " = %"PRIx64"\n", __func__, addr, val); | |
826 | break; | |
827 | } | |
828 | } | |
829 | ||
830 | static const MemoryRegionOps mv64361_ops = { | |
831 | .read = mv64361_read, | |
832 | .write = mv64361_write, | |
833 | .valid.min_access_size = 1, | |
834 | .valid.max_access_size = 4, | |
835 | .endianness = DEVICE_LITTLE_ENDIAN, | |
836 | }; | |
837 | ||
838 | static void mv64361_gpp_irq(void *opaque, int n, int level) | |
839 | { | |
840 | MV64361State *s = opaque; | |
841 | uint32_t mask = BIT(n); | |
842 | uint32_t val = s->gpp_value & ~mask; | |
843 | ||
844 | if (s->gpp_level & mask) { | |
845 | level = !level; | |
846 | } | |
847 | val |= level << n; | |
848 | if (val > s->gpp_value) { | |
849 | s->gpp_value = val; | |
850 | s->gpp_int_cr |= mask; | |
851 | if (s->gpp_int_mask & mask) { | |
852 | mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + n / 8, 1); | |
853 | } | |
854 | } else if (val < s->gpp_value) { | |
855 | int b = n / 8; | |
856 | s->gpp_value = val; | |
857 | if (s->gpp_int_level && !(val & 0xff << b)) { | |
858 | mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + b, 0); | |
859 | } | |
860 | } | |
861 | } | |
862 | ||
863 | static void mv64361_realize(DeviceState *dev, Error **errp) | |
864 | { | |
865 | MV64361State *s = MV64361(dev); | |
866 | int i; | |
867 | ||
868 | s->base_addr_enable = 0x1fffff; | |
869 | memory_region_init_io(&s->regs, OBJECT(s), &mv64361_ops, s, | |
870 | TYPE_MV64361, 0x10000); | |
bd20cde5 | 871 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs); |
dcdf98a9 BZ |
872 | for (i = 0; i < 2; i++) { |
873 | g_autofree char *name = g_strdup_printf("pcihost%d", i); | |
874 | object_initialize_child(OBJECT(dev), name, &s->pci[i], | |
875 | TYPE_MV64361_PCI); | |
876 | DeviceState *pci = DEVICE(&s->pci[i]); | |
877 | qdev_prop_set_uint8(pci, "index", i); | |
878 | sysbus_realize_and_unref(SYS_BUS_DEVICE(pci), &error_fatal); | |
879 | } | |
880 | sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq); | |
881 | qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32); | |
882 | /* FIXME: PCI IRQ connections may be board specific */ | |
883 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
884 | s->pci[1].irq[i] = qdev_get_gpio_in_named(dev, "gpp", 12 + i); | |
885 | } | |
886 | } | |
887 | ||
888 | static void mv64361_reset(DeviceState *dev) | |
889 | { | |
890 | MV64361State *s = MV64361(dev); | |
891 | int i, j; | |
892 | ||
893 | /* | |
894 | * These values may be board specific | |
895 | * Real chip supports init from an eprom but that's not modelled | |
896 | */ | |
897 | set_mem_windows(s, 0x1fffff); | |
898 | s->cpu_conf = 0x28000ff; | |
899 | s->regs_base = 0x100f100; | |
900 | s->pci[0].io_base = 0x100f800; | |
901 | s->pci[0].io_size = 0xff; | |
902 | s->pci[0].mem_base[0] = 0x100c000; | |
903 | s->pci[0].mem_size[0] = 0x1fff; | |
904 | s->pci[0].mem_base[1] = 0x100f900; | |
905 | s->pci[0].mem_size[1] = 0xff; | |
906 | s->pci[0].mem_base[2] = 0x100f400; | |
907 | s->pci[0].mem_size[2] = 0x1ff; | |
908 | s->pci[0].mem_base[3] = 0x100f600; | |
909 | s->pci[0].mem_size[3] = 0x1ff; | |
910 | s->pci[1].io_base = 0x100fe00; | |
911 | s->pci[1].io_size = 0xff; | |
912 | s->pci[1].mem_base[0] = 0x1008000; | |
913 | s->pci[1].mem_size[0] = 0x3fff; | |
914 | s->pci[1].mem_base[1] = 0x100fd00; | |
915 | s->pci[1].mem_size[1] = 0xff; | |
916 | s->pci[1].mem_base[2] = 0x1002600; | |
917 | s->pci[1].mem_size[2] = 0x1ff; | |
918 | s->pci[1].mem_base[3] = 0x100ff80; | |
919 | s->pci[1].mem_size[3] = 0x7f; | |
920 | for (i = 0; i < 2; i++) { | |
921 | for (j = 0; j < 4; j++) { | |
922 | s->pci[i].remap[j] = s->pci[i].mem_base[j] << 16; | |
923 | } | |
924 | } | |
925 | s->pci[0].remap[1] = 0; | |
926 | s->pci[1].remap[1] = 0; | |
927 | set_mem_windows(s, 0xfbfff); | |
928 | } | |
929 | ||
930 | static void mv64361_class_init(ObjectClass *klass, void *data) | |
931 | { | |
932 | DeviceClass *dc = DEVICE_CLASS(klass); | |
933 | ||
934 | dc->realize = mv64361_realize; | |
935 | dc->reset = mv64361_reset; | |
936 | } | |
937 | ||
938 | static const TypeInfo mv64361_type_info = { | |
939 | .name = TYPE_MV64361, | |
940 | .parent = TYPE_SYS_BUS_DEVICE, | |
941 | .instance_size = sizeof(MV64361State), | |
942 | .class_init = mv64361_class_init, | |
943 | }; | |
944 | ||
945 | static void mv64361_register_types(void) | |
946 | { | |
947 | type_register_static(&mv64361_type_info); | |
948 | } | |
949 | ||
950 | type_init(mv64361_register_types) |