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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a | 26 | #include "hw/i386/pc.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/pci/pci_host.h" | |
0d09e41a | 29 | #include "hw/isa/isa.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
1de7afc9 | 31 | #include "qemu/range.h" |
0d09e41a PB |
32 | #include "hw/xen/xen.h" |
33 | #include "hw/pci-host/pam.h" | |
1ec4ba74 | 34 | #include "sysemu/sysemu.h" |
87ecb68b | 35 | |
56594fe3 IY |
36 | /* |
37 | * I440FX chipset data sheet. | |
38 | * http://download.intel.com/design/chipsets/datashts/29054901.pdf | |
39 | */ | |
40 | ||
67c332fd AF |
41 | typedef struct I440FXState { |
42 | PCIHostState parent_obj; | |
43 | } I440FXState; | |
502a5395 | 44 | |
ab431c28 | 45 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 46 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 47 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 48 | #define PIIX_PIRQC 0x60 |
e735b55a | 49 | |
1ec4ba74 LE |
50 | /* |
51 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address | |
52 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). | |
53 | */ | |
54 | #define RCR_IOPORT 0xcf9 | |
55 | ||
fd37d881 JQ |
56 | typedef struct PIIX3State { |
57 | PCIDevice dev; | |
ab431c28 IY |
58 | |
59 | /* | |
60 | * bitmap to track pic levels. | |
61 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
62 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
63 | * | |
64 | * PIRQ is mapped to PIC pins, we track it by | |
65 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
66 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
67 | */ | |
68 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
69 | #error "unable to encode pic state in 64bit in pic_levels." | |
70 | #endif | |
71 | uint64_t pic_levels; | |
72 | ||
bd7dce87 | 73 | qemu_irq *pic; |
e735b55a IY |
74 | |
75 | /* This member isn't used. Just for save/load compatibility */ | |
76 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
1ec4ba74 LE |
77 | |
78 | /* Reset Control Register contents */ | |
79 | uint8_t rcr; | |
80 | ||
81 | /* IO memory region for Reset Control Register (RCR_IOPORT) */ | |
82 | MemoryRegion rcr_mem; | |
7cd9eee0 | 83 | } PIIX3State; |
bd7dce87 | 84 | |
57a0f0c6 DW |
85 | #define TYPE_I440FX_PCI_DEVICE "i440FX" |
86 | #define I440FX_PCI_DEVICE(obj) \ | |
87 | OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) | |
88 | ||
0a3bacf3 | 89 | struct PCII440FXState { |
2aedfa46 HT |
90 | /*< private >*/ |
91 | PCIDevice parent_obj; | |
92 | /*< public >*/ | |
93 | ||
ae0a5466 AK |
94 | MemoryRegion *system_memory; |
95 | MemoryRegion *pci_address_space; | |
96 | MemoryRegion *ram_memory; | |
97 | MemoryRegion pci_hole; | |
98 | MemoryRegion pci_hole_64bit; | |
99 | PAMMemoryRegion pam_regions[13]; | |
100 | MemoryRegion smram_region; | |
6c009fa4 | 101 | uint8_t smm_enabled; |
0a3bacf3 JQ |
102 | }; |
103 | ||
f2c688bb IY |
104 | |
105 | #define I440FX_PAM 0x59 | |
106 | #define I440FX_PAM_SIZE 7 | |
107 | #define I440FX_SMRAM 0x72 | |
108 | ||
ab431c28 | 109 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 110 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
111 | static void piix3_write_config_xen(PCIDevice *dev, |
112 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
113 | |
114 | /* return the global irq number corresponding to a given device irq | |
115 | pin. We could also use the bus number to have a more precise | |
116 | mapping. */ | |
ab431c28 | 117 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
118 | { |
119 | int slot_addend; | |
120 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 121 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 122 | } |
502a5395 | 123 | |
0a3bacf3 | 124 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 125 | { |
410edd92 | 126 | int i; |
2aedfa46 | 127 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 128 | |
72124c01 | 129 | memory_region_transaction_begin(); |
410edd92 IY |
130 | for (i = 0; i < 13; i++) { |
131 | pam_update(&d->pam_regions[i], i, | |
2aedfa46 | 132 | pd->config[I440FX_PAM + ((i + 1) / 2)]); |
ee0ea1d0 | 133 | } |
2aedfa46 | 134 | smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled); |
72124c01 | 135 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
136 | } |
137 | ||
f885f1ea | 138 | static void i440fx_set_smm(int val, void *arg) |
ee0ea1d0 | 139 | { |
f885f1ea | 140 | PCII440FXState *d = arg; |
2aedfa46 | 141 | PCIDevice *pd = PCI_DEVICE(d); |
f885f1ea | 142 | |
410edd92 | 143 | memory_region_transaction_begin(); |
2aedfa46 | 144 | smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM], |
410edd92 IY |
145 | &d->smram_region); |
146 | memory_region_transaction_commit(); | |
ee0ea1d0 FB |
147 | } |
148 | ||
149 | ||
0a3bacf3 | 150 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
151 | uint32_t address, uint32_t val, int len) |
152 | { | |
57a0f0c6 | 153 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 154 | |
ee0ea1d0 | 155 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 156 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
157 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
158 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 159 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 160 | } |
ee0ea1d0 FB |
161 | } |
162 | ||
0c7d19e5 | 163 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 164 | { |
0a3bacf3 | 165 | PCII440FXState *d = opaque; |
2aedfa46 | 166 | PCIDevice *pd = PCI_DEVICE(d); |
52fc1d83 | 167 | int ret, i; |
ee0ea1d0 | 168 | |
2aedfa46 | 169 | ret = pci_device_load(pd, f); |
ee0ea1d0 FB |
170 | if (ret < 0) |
171 | return ret; | |
172 | i440fx_update_memory_mappings(d); | |
6c009fa4 | 173 | qemu_get_8s(f, &d->smm_enabled); |
52fc1d83 | 174 | |
e735b55a IY |
175 | if (version_id == 2) { |
176 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
177 | qemu_get_be32(f); /* dummy load for compatibility */ | |
178 | } | |
179 | } | |
52fc1d83 | 180 | |
ee0ea1d0 FB |
181 | return 0; |
182 | } | |
183 | ||
e59fb374 | 184 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
185 | { |
186 | PCII440FXState *d = opaque; | |
187 | ||
188 | i440fx_update_memory_mappings(d); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static const VMStateDescription vmstate_i440fx = { | |
193 | .name = "I440FX", | |
194 | .version_id = 3, | |
195 | .minimum_version_id = 3, | |
196 | .minimum_version_id_old = 1, | |
197 | .load_state_old = i440fx_load_old, | |
752ff2fa | 198 | .post_load = i440fx_post_load, |
0c7d19e5 | 199 | .fields = (VMStateField []) { |
2aedfa46 | 200 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
0c7d19e5 JQ |
201 | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
202 | VMSTATE_END_OF_LIST() | |
203 | } | |
204 | }; | |
205 | ||
a3560fbf | 206 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 207 | { |
a3560fbf | 208 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
502a5395 | 209 | |
a3560fbf | 210 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 211 | "pci-conf-idx", 4); |
a3560fbf | 212 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 213 | "pci-conf-data", 4); |
a3560fbf | 214 | } |
502a5395 | 215 | |
a3560fbf HT |
216 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
217 | { | |
218 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
219 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
220 | ||
221 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
222 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
223 | ||
224 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
225 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
8a14daa5 | 226 | } |
502a5395 | 227 | |
0a3bacf3 | 228 | static int i440fx_initfn(PCIDevice *dev) |
8a14daa5 | 229 | { |
57a0f0c6 | 230 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
ee0ea1d0 | 231 | |
2aedfa46 | 232 | dev->config[I440FX_SMRAM] = 0x02; |
ee0ea1d0 | 233 | |
f885f1ea | 234 | cpu_smm_register(&i440fx_set_smm, d); |
81a322d4 | 235 | return 0; |
8a14daa5 GH |
236 | } |
237 | ||
41445300 AP |
238 | static PCIBus *i440fx_common_init(const char *device_name, |
239 | PCII440FXState **pi440fx_state, | |
240 | int *piix3_devfn, | |
60573079 | 241 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
242 | MemoryRegion *address_space_mem, |
243 | MemoryRegion *address_space_io, | |
ae0a5466 | 244 | ram_addr_t ram_size, |
a8170e5e AK |
245 | hwaddr pci_hole_start, |
246 | hwaddr pci_hole_size, | |
247 | hwaddr pci_hole64_start, | |
248 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
249 | MemoryRegion *pci_address_space, |
250 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
251 | { |
252 | DeviceState *dev; | |
253 | PCIBus *b; | |
254 | PCIDevice *d; | |
8558d942 | 255 | PCIHostState *s; |
7cd9eee0 | 256 | PIIX3State *piix3; |
ae0a5466 | 257 | PCII440FXState *f; |
2725aec7 | 258 | unsigned i; |
8a14daa5 GH |
259 | |
260 | dev = qdev_create(NULL, "i440FX-pcihost"); | |
8558d942 | 261 | s = PCI_HOST_BRIDGE(dev); |
67c332fd | 262 | b = pci_bus_new(dev, NULL, pci_address_space, |
60a0e443 | 263 | address_space_io, 0, TYPE_PCI_BUS); |
8a14daa5 | 264 | s->bus = b; |
f05f6b4a | 265 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 266 | qdev_init_nofail(dev); |
8a14daa5 | 267 | |
41445300 | 268 | d = pci_create_simple(b, 0, device_name); |
57a0f0c6 | 269 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
270 | f = *pi440fx_state; |
271 | f->system_memory = address_space_mem; | |
272 | f->pci_address_space = pci_address_space; | |
273 | f->ram_memory = ram_memory; | |
40c5dce9 | 274 | memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, |
ae0a5466 AK |
275 | pci_hole_start, pci_hole_size); |
276 | memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); | |
40c5dce9 | 277 | memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64", |
ae0a5466 AK |
278 | f->pci_address_space, |
279 | pci_hole64_start, pci_hole64_size); | |
280 | if (pci_hole64_size) { | |
281 | memory_region_add_subregion(f->system_memory, pci_hole64_start, | |
282 | &f->pci_hole_64bit); | |
283 | } | |
40c5dce9 | 284 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 285 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
286 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
287 | &f->smram_region, 1); | |
288 | memory_region_set_enabled(&f->smram_region, false); | |
3cd2cf43 | 289 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 290 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
2725aec7 | 291 | for (i = 0; i < 12; ++i) { |
3cd2cf43 | 292 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
293 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
294 | PAM_EXPAN_SIZE); | |
2725aec7 | 295 | } |
8a14daa5 | 296 | |
bf09551a SS |
297 | /* Xen supports additional interrupt routes from the PCI devices to |
298 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
299 | * connected to the IOAPIC directly. | |
300 | * These additional routes can be discovered through ACPI. */ | |
301 | if (xen_enabled()) { | |
302 | piix3 = DO_UPCAST(PIIX3State, dev, | |
303 | pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); | |
304 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, | |
305 | piix3, XEN_PIIX_NUM_PIRQS); | |
306 | } else { | |
307 | piix3 = DO_UPCAST(PIIX3State, dev, | |
308 | pci_create_simple_multifunction(b, -1, true, "PIIX3")); | |
309 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, | |
310 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 311 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 312 | } |
7cd9eee0 | 313 | piix3->pic = pic; |
d93a8a43 | 314 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); |
41445300 | 315 | |
7cd9eee0 | 316 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 317 | |
ec5f92ce | 318 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 319 | if (ram_size > 255) { |
ec5f92ce | 320 | ram_size = 255; |
2aedfa46 HT |
321 | } |
322 | d->config[0x57] = ram_size; | |
ec5f92ce | 323 | |
ae0a5466 AK |
324 | i440fx_update_memory_mappings(f); |
325 | ||
502a5395 PB |
326 | return b; |
327 | } | |
328 | ||
41445300 | 329 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, |
60573079 | 330 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
331 | MemoryRegion *address_space_mem, |
332 | MemoryRegion *address_space_io, | |
ae0a5466 | 333 | ram_addr_t ram_size, |
a8170e5e AK |
334 | hwaddr pci_hole_start, |
335 | hwaddr pci_hole_size, | |
336 | hwaddr pci_hole64_start, | |
337 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
338 | MemoryRegion *pci_memory, MemoryRegion *ram_memory) |
339 | ||
41445300 AP |
340 | { |
341 | PCIBus *b; | |
342 | ||
57a0f0c6 DW |
343 | b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state, |
344 | piix3_devfn, isa_bus, pic, | |
ae0a5466 AK |
345 | address_space_mem, address_space_io, ram_size, |
346 | pci_hole_start, pci_hole_size, | |
d50c6c8b | 347 | pci_hole64_start, pci_hole64_size, |
ae0a5466 | 348 | pci_memory, ram_memory); |
41445300 AP |
349 | return b; |
350 | } | |
351 | ||
502a5395 | 352 | /* PIIX3 PCI to ISA bridge */ |
ab431c28 IY |
353 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
354 | { | |
355 | qemu_set_irq(piix3->pic[pic_irq], | |
356 | !!(piix3->pic_levels & | |
09de0f46 | 357 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
358 | (pic_irq * PIIX_NUM_PIRQS)))); |
359 | } | |
502a5395 | 360 | |
afe3ef1d | 361 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
362 | { |
363 | int pic_irq; | |
364 | uint64_t mask; | |
365 | ||
366 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
367 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
368 | return; | |
369 | } | |
370 | ||
371 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
372 | piix3->pic_levels &= ~mask; | |
373 | piix3->pic_levels |= mask * !!level; | |
374 | ||
afe3ef1d | 375 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
376 | } |
377 | ||
378 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 379 | { |
7cd9eee0 | 380 | PIIX3State *piix3 = opaque; |
afe3ef1d | 381 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 382 | } |
502a5395 | 383 | |
3afa9bb4 MT |
384 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
385 | { | |
386 | PIIX3State *piix3 = opaque; | |
387 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
388 | PCIINTxRoute route; | |
389 | ||
390 | if (irq < PIIX_NUM_PIC_IRQS) { | |
391 | route.mode = PCI_INTX_ENABLED; | |
392 | route.irq = irq; | |
393 | } else { | |
394 | route.mode = PCI_INTX_DISABLED; | |
395 | route.irq = -1; | |
396 | } | |
397 | return route; | |
398 | } | |
399 | ||
ab431c28 IY |
400 | /* irq routing is changed. so rebuild bitmap */ |
401 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
402 | { | |
403 | int pirq; | |
404 | ||
405 | piix3->pic_levels = 0; | |
406 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
407 | piix3_set_irq_level(piix3, pirq, | |
afe3ef1d | 408 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
ab431c28 IY |
409 | } |
410 | } | |
411 | ||
412 | static void piix3_write_config(PCIDevice *dev, | |
413 | uint32_t address, uint32_t val, int len) | |
414 | { | |
415 | pci_default_write_config(dev, address, val, len); | |
416 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
417 | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); | |
418 | int pic_irq; | |
0ae16251 JK |
419 | |
420 | pci_bus_fire_intx_routing_notifier(piix3->dev.bus); | |
ab431c28 IY |
421 | piix3_update_irq_levels(piix3); |
422 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
423 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 424 | } |
502a5395 PB |
425 | } |
426 | } | |
427 | ||
bf09551a SS |
428 | static void piix3_write_config_xen(PCIDevice *dev, |
429 | uint32_t address, uint32_t val, int len) | |
430 | { | |
431 | xen_piix_pci_write_config_client(address, val, len); | |
432 | piix3_write_config(dev, address, val, len); | |
433 | } | |
434 | ||
15a1956a | 435 | static void piix3_reset(void *opaque) |
502a5395 | 436 | { |
fd37d881 JQ |
437 | PIIX3State *d = opaque; |
438 | uint8_t *pci_conf = d->dev.config; | |
502a5395 | 439 | |
c9721215 | 440 | pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
502a5395 PB |
441 | pci_conf[0x05] = 0x00; |
442 | pci_conf[0x06] = 0x00; | |
c9721215 | 443 | pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
502a5395 PB |
444 | pci_conf[0x4c] = 0x4d; |
445 | pci_conf[0x4e] = 0x03; | |
446 | pci_conf[0x4f] = 0x00; | |
447 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
448 | pci_conf[0x61] = 0x80; |
449 | pci_conf[0x62] = 0x80; | |
450 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
451 | pci_conf[0x69] = 0x02; |
452 | pci_conf[0x70] = 0x80; | |
453 | pci_conf[0x76] = 0x0c; | |
454 | pci_conf[0x77] = 0x0c; | |
455 | pci_conf[0x78] = 0x02; | |
456 | pci_conf[0x79] = 0x00; | |
457 | pci_conf[0x80] = 0x00; | |
458 | pci_conf[0x82] = 0x00; | |
459 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
460 | pci_conf[0xa2] = 0x00; |
461 | pci_conf[0xa3] = 0x00; | |
462 | pci_conf[0xa4] = 0x00; | |
463 | pci_conf[0xa5] = 0x00; | |
464 | pci_conf[0xa6] = 0x00; | |
465 | pci_conf[0xa7] = 0x00; | |
466 | pci_conf[0xa8] = 0x0f; | |
467 | pci_conf[0xaa] = 0x00; | |
468 | pci_conf[0xab] = 0x00; | |
469 | pci_conf[0xac] = 0x00; | |
470 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
471 | |
472 | d->pic_levels = 0; | |
1ec4ba74 | 473 | d->rcr = 0; |
ab431c28 IY |
474 | } |
475 | ||
476 | static int piix3_post_load(void *opaque, int version_id) | |
477 | { | |
478 | PIIX3State *piix3 = opaque; | |
479 | piix3_update_irq_levels(piix3); | |
480 | return 0; | |
e735b55a | 481 | } |
15a1956a | 482 | |
e735b55a IY |
483 | static void piix3_pre_save(void *opaque) |
484 | { | |
485 | int i; | |
486 | PIIX3State *piix3 = opaque; | |
487 | ||
488 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
489 | piix3->pci_irq_levels_vmstate[i] = | |
490 | pci_bus_get_irq_level(piix3->dev.bus, i); | |
491 | } | |
502a5395 PB |
492 | } |
493 | ||
1ec4ba74 LE |
494 | static bool piix3_rcr_needed(void *opaque) |
495 | { | |
496 | PIIX3State *piix3 = opaque; | |
497 | ||
498 | return (piix3->rcr != 0); | |
499 | } | |
500 | ||
501 | static const VMStateDescription vmstate_piix3_rcr = { | |
502 | .name = "PIIX3/rcr", | |
503 | .version_id = 1, | |
504 | .minimum_version_id = 1, | |
505 | .fields = (VMStateField []) { | |
506 | VMSTATE_UINT8(rcr, PIIX3State), | |
507 | VMSTATE_END_OF_LIST() | |
508 | } | |
509 | }; | |
510 | ||
d1f171bd JQ |
511 | static const VMStateDescription vmstate_piix3 = { |
512 | .name = "PIIX3", | |
513 | .version_id = 3, | |
514 | .minimum_version_id = 2, | |
515 | .minimum_version_id_old = 2, | |
ab431c28 | 516 | .post_load = piix3_post_load, |
e735b55a | 517 | .pre_save = piix3_pre_save, |
1ec4ba74 | 518 | .fields = (VMStateField[]) { |
d1f171bd | 519 | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
e735b55a IY |
520 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
521 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 522 | VMSTATE_END_OF_LIST() |
1ec4ba74 LE |
523 | }, |
524 | .subsections = (VMStateSubsection[]) { | |
525 | { | |
526 | .vmsd = &vmstate_piix3_rcr, | |
527 | .needed = piix3_rcr_needed, | |
528 | }, | |
529 | { 0 } | |
530 | } | |
531 | }; | |
532 | ||
533 | ||
534 | static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) | |
535 | { | |
536 | PIIX3State *d = opaque; | |
537 | ||
538 | if (val & 4) { | |
539 | qemu_system_reset_request(); | |
540 | return; | |
da64182c | 541 | } |
1ec4ba74 LE |
542 | d->rcr = val & 2; /* keep System Reset type only */ |
543 | } | |
544 | ||
545 | static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) | |
546 | { | |
547 | PIIX3State *d = opaque; | |
548 | ||
549 | return d->rcr; | |
550 | } | |
551 | ||
552 | static const MemoryRegionOps rcr_ops = { | |
553 | .read = rcr_read, | |
554 | .write = rcr_write, | |
555 | .endianness = DEVICE_LITTLE_ENDIAN | |
d1f171bd | 556 | }; |
1941d19c | 557 | |
fd37d881 | 558 | static int piix3_initfn(PCIDevice *dev) |
502a5395 | 559 | { |
fd37d881 | 560 | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
502a5395 | 561 | |
d93a8a43 | 562 | isa_bus_new(DEVICE(d), pci_address_space_io(dev)); |
1ec4ba74 | 563 | |
40c5dce9 PB |
564 | memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, |
565 | "piix3-reset-control", 1); | |
1ec4ba74 LE |
566 | memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
567 | &d->rcr_mem, 1); | |
568 | ||
a08d4367 | 569 | qemu_register_reset(piix3_reset, d); |
81a322d4 | 570 | return 0; |
502a5395 | 571 | } |
5c2b87e3 | 572 | |
40021f08 AL |
573 | static void piix3_class_init(ObjectClass *klass, void *data) |
574 | { | |
39bffca2 | 575 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
576 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
577 | ||
39bffca2 AL |
578 | dc->desc = "ISA bridge"; |
579 | dc->vmsd = &vmstate_piix3; | |
580 | dc->no_user = 1, | |
40021f08 AL |
581 | k->no_hotplug = 1; |
582 | k->init = piix3_initfn; | |
583 | k->config_write = piix3_write_config; | |
584 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
585 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
586 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 AL |
587 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
588 | } | |
589 | ||
4240abff | 590 | static const TypeInfo piix3_info = { |
39bffca2 AL |
591 | .name = "PIIX3", |
592 | .parent = TYPE_PCI_DEVICE, | |
593 | .instance_size = sizeof(PIIX3State), | |
594 | .class_init = piix3_class_init, | |
e855761c AL |
595 | }; |
596 | ||
40021f08 AL |
597 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
598 | { | |
39bffca2 | 599 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
600 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
601 | ||
39bffca2 AL |
602 | dc->desc = "ISA bridge"; |
603 | dc->vmsd = &vmstate_piix3; | |
604 | dc->no_user = 1; | |
40021f08 AL |
605 | k->no_hotplug = 1; |
606 | k->init = piix3_initfn; | |
607 | k->config_write = piix3_write_config_xen; | |
608 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
609 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
610 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 | 611 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
e855761c AL |
612 | }; |
613 | ||
4240abff | 614 | static const TypeInfo piix3_xen_info = { |
39bffca2 AL |
615 | .name = "PIIX3-xen", |
616 | .parent = TYPE_PCI_DEVICE, | |
617 | .instance_size = sizeof(PIIX3State), | |
618 | .class_init = piix3_xen_class_init, | |
40021f08 AL |
619 | }; |
620 | ||
621 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
622 | { | |
39bffca2 | 623 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
624 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
625 | ||
626 | k->no_hotplug = 1; | |
627 | k->init = i440fx_initfn; | |
628 | k->config_write = i440fx_write_config; | |
629 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
630 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
631 | k->revision = 0x02; | |
632 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
633 | dc->desc = "Host bridge"; |
634 | dc->no_user = 1; | |
635 | dc->vmsd = &vmstate_i440fx; | |
40021f08 AL |
636 | } |
637 | ||
4240abff | 638 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 639 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
640 | .parent = TYPE_PCI_DEVICE, |
641 | .instance_size = sizeof(PCII440FXState), | |
642 | .class_init = i440fx_class_init, | |
8a14daa5 GH |
643 | }; |
644 | ||
568f0690 DG |
645 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
646 | PCIBus *rootbus) | |
647 | { | |
648 | /* For backwards compat with old device paths */ | |
649 | return "0000"; | |
650 | } | |
651 | ||
999e12bb AL |
652 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
653 | { | |
39bffca2 | 654 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 655 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 656 | |
568f0690 | 657 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 658 | dc->realize = i440fx_pcihost_realize; |
39bffca2 AL |
659 | dc->fw_name = "pci"; |
660 | dc->no_user = 1; | |
999e12bb AL |
661 | } |
662 | ||
4240abff | 663 | static const TypeInfo i440fx_pcihost_info = { |
39bffca2 | 664 | .name = "i440FX-pcihost", |
8558d942 | 665 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 666 | .instance_size = sizeof(I440FXState), |
a3560fbf | 667 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 668 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
669 | }; |
670 | ||
83f7d43a | 671 | static void i440fx_register_types(void) |
8a14daa5 | 672 | { |
39bffca2 AL |
673 | type_register_static(&i440fx_info); |
674 | type_register_static(&piix3_info); | |
675 | type_register_static(&piix3_xen_info); | |
676 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 677 | } |
83f7d43a AF |
678 | |
679 | type_init(i440fx_register_types) |