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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a | 26 | #include "hw/i386/pc.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/pci/pci_host.h" | |
0d09e41a | 29 | #include "hw/isa/isa.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
1de7afc9 | 31 | #include "qemu/range.h" |
0d09e41a PB |
32 | #include "hw/xen/xen.h" |
33 | #include "hw/pci-host/pam.h" | |
1ec4ba74 | 34 | #include "sysemu/sysemu.h" |
87ecb68b | 35 | |
56594fe3 IY |
36 | /* |
37 | * I440FX chipset data sheet. | |
38 | * http://download.intel.com/design/chipsets/datashts/29054901.pdf | |
39 | */ | |
40 | ||
1d0d4aa4 IM |
41 | #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" |
42 | #define I440FX_PCI_HOST_BRIDGE(obj) \ | |
43 | OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE) | |
44 | ||
67c332fd AF |
45 | typedef struct I440FXState { |
46 | PCIHostState parent_obj; | |
47 | } I440FXState; | |
502a5395 | 48 | |
ab431c28 | 49 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 50 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 51 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 52 | #define PIIX_PIRQC 0x60 |
e735b55a | 53 | |
1ec4ba74 LE |
54 | /* |
55 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address | |
56 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). | |
57 | */ | |
58 | #define RCR_IOPORT 0xcf9 | |
59 | ||
fd37d881 JQ |
60 | typedef struct PIIX3State { |
61 | PCIDevice dev; | |
ab431c28 IY |
62 | |
63 | /* | |
64 | * bitmap to track pic levels. | |
65 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
66 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
67 | * | |
68 | * PIRQ is mapped to PIC pins, we track it by | |
69 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
70 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
71 | */ | |
72 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
73 | #error "unable to encode pic state in 64bit in pic_levels." | |
74 | #endif | |
75 | uint64_t pic_levels; | |
76 | ||
bd7dce87 | 77 | qemu_irq *pic; |
e735b55a IY |
78 | |
79 | /* This member isn't used. Just for save/load compatibility */ | |
80 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
1ec4ba74 LE |
81 | |
82 | /* Reset Control Register contents */ | |
83 | uint8_t rcr; | |
84 | ||
85 | /* IO memory region for Reset Control Register (RCR_IOPORT) */ | |
86 | MemoryRegion rcr_mem; | |
7cd9eee0 | 87 | } PIIX3State; |
bd7dce87 | 88 | |
57a0f0c6 DW |
89 | #define TYPE_I440FX_PCI_DEVICE "i440FX" |
90 | #define I440FX_PCI_DEVICE(obj) \ | |
91 | OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) | |
92 | ||
0a3bacf3 | 93 | struct PCII440FXState { |
2aedfa46 HT |
94 | /*< private >*/ |
95 | PCIDevice parent_obj; | |
96 | /*< public >*/ | |
97 | ||
ae0a5466 AK |
98 | MemoryRegion *system_memory; |
99 | MemoryRegion *pci_address_space; | |
100 | MemoryRegion *ram_memory; | |
101 | MemoryRegion pci_hole; | |
102 | MemoryRegion pci_hole_64bit; | |
103 | PAMMemoryRegion pam_regions[13]; | |
104 | MemoryRegion smram_region; | |
6c009fa4 | 105 | uint8_t smm_enabled; |
0a3bacf3 JQ |
106 | }; |
107 | ||
f2c688bb IY |
108 | |
109 | #define I440FX_PAM 0x59 | |
110 | #define I440FX_PAM_SIZE 7 | |
111 | #define I440FX_SMRAM 0x72 | |
112 | ||
ab431c28 | 113 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 114 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
115 | static void piix3_write_config_xen(PCIDevice *dev, |
116 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
117 | |
118 | /* return the global irq number corresponding to a given device irq | |
119 | pin. We could also use the bus number to have a more precise | |
120 | mapping. */ | |
ab431c28 | 121 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
122 | { |
123 | int slot_addend; | |
124 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 125 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 126 | } |
502a5395 | 127 | |
0a3bacf3 | 128 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 129 | { |
410edd92 | 130 | int i; |
2aedfa46 | 131 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 132 | |
72124c01 | 133 | memory_region_transaction_begin(); |
410edd92 IY |
134 | for (i = 0; i < 13; i++) { |
135 | pam_update(&d->pam_regions[i], i, | |
2aedfa46 | 136 | pd->config[I440FX_PAM + ((i + 1) / 2)]); |
ee0ea1d0 | 137 | } |
2aedfa46 | 138 | smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled); |
72124c01 | 139 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
140 | } |
141 | ||
f885f1ea | 142 | static void i440fx_set_smm(int val, void *arg) |
ee0ea1d0 | 143 | { |
f885f1ea | 144 | PCII440FXState *d = arg; |
2aedfa46 | 145 | PCIDevice *pd = PCI_DEVICE(d); |
f885f1ea | 146 | |
410edd92 | 147 | memory_region_transaction_begin(); |
2aedfa46 | 148 | smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM], |
410edd92 IY |
149 | &d->smram_region); |
150 | memory_region_transaction_commit(); | |
ee0ea1d0 FB |
151 | } |
152 | ||
153 | ||
0a3bacf3 | 154 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
155 | uint32_t address, uint32_t val, int len) |
156 | { | |
57a0f0c6 | 157 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 158 | |
ee0ea1d0 | 159 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 160 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
161 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
162 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 163 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 164 | } |
ee0ea1d0 FB |
165 | } |
166 | ||
0c7d19e5 | 167 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 168 | { |
0a3bacf3 | 169 | PCII440FXState *d = opaque; |
2aedfa46 | 170 | PCIDevice *pd = PCI_DEVICE(d); |
52fc1d83 | 171 | int ret, i; |
ee0ea1d0 | 172 | |
2aedfa46 | 173 | ret = pci_device_load(pd, f); |
ee0ea1d0 FB |
174 | if (ret < 0) |
175 | return ret; | |
176 | i440fx_update_memory_mappings(d); | |
6c009fa4 | 177 | qemu_get_8s(f, &d->smm_enabled); |
52fc1d83 | 178 | |
e735b55a IY |
179 | if (version_id == 2) { |
180 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
181 | qemu_get_be32(f); /* dummy load for compatibility */ | |
182 | } | |
183 | } | |
52fc1d83 | 184 | |
ee0ea1d0 FB |
185 | return 0; |
186 | } | |
187 | ||
e59fb374 | 188 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
189 | { |
190 | PCII440FXState *d = opaque; | |
191 | ||
192 | i440fx_update_memory_mappings(d); | |
193 | return 0; | |
194 | } | |
195 | ||
196 | static const VMStateDescription vmstate_i440fx = { | |
197 | .name = "I440FX", | |
198 | .version_id = 3, | |
199 | .minimum_version_id = 3, | |
200 | .minimum_version_id_old = 1, | |
201 | .load_state_old = i440fx_load_old, | |
752ff2fa | 202 | .post_load = i440fx_post_load, |
0c7d19e5 | 203 | .fields = (VMStateField []) { |
2aedfa46 | 204 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
0c7d19e5 JQ |
205 | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
206 | VMSTATE_END_OF_LIST() | |
207 | } | |
208 | }; | |
209 | ||
a3560fbf | 210 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 211 | { |
a3560fbf | 212 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
502a5395 | 213 | |
a3560fbf | 214 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 215 | "pci-conf-idx", 4); |
a3560fbf | 216 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 217 | "pci-conf-data", 4); |
a3560fbf | 218 | } |
502a5395 | 219 | |
a3560fbf HT |
220 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
221 | { | |
222 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
223 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
224 | ||
225 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
226 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
227 | ||
228 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
229 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
8a14daa5 | 230 | } |
502a5395 | 231 | |
0a3bacf3 | 232 | static int i440fx_initfn(PCIDevice *dev) |
8a14daa5 | 233 | { |
57a0f0c6 | 234 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
ee0ea1d0 | 235 | |
2aedfa46 | 236 | dev->config[I440FX_SMRAM] = 0x02; |
ee0ea1d0 | 237 | |
f885f1ea | 238 | cpu_smm_register(&i440fx_set_smm, d); |
81a322d4 | 239 | return 0; |
8a14daa5 GH |
240 | } |
241 | ||
41445300 AP |
242 | static PCIBus *i440fx_common_init(const char *device_name, |
243 | PCII440FXState **pi440fx_state, | |
244 | int *piix3_devfn, | |
60573079 | 245 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
246 | MemoryRegion *address_space_mem, |
247 | MemoryRegion *address_space_io, | |
ae0a5466 | 248 | ram_addr_t ram_size, |
a8170e5e AK |
249 | hwaddr pci_hole_start, |
250 | hwaddr pci_hole_size, | |
251 | hwaddr pci_hole64_start, | |
252 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
253 | MemoryRegion *pci_address_space, |
254 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
255 | { |
256 | DeviceState *dev; | |
257 | PCIBus *b; | |
258 | PCIDevice *d; | |
8558d942 | 259 | PCIHostState *s; |
7cd9eee0 | 260 | PIIX3State *piix3; |
ae0a5466 | 261 | PCII440FXState *f; |
2725aec7 | 262 | unsigned i; |
8a14daa5 | 263 | |
1d0d4aa4 | 264 | dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE); |
8558d942 | 265 | s = PCI_HOST_BRIDGE(dev); |
67c332fd | 266 | b = pci_bus_new(dev, NULL, pci_address_space, |
60a0e443 | 267 | address_space_io, 0, TYPE_PCI_BUS); |
8a14daa5 | 268 | s->bus = b; |
f05f6b4a | 269 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 270 | qdev_init_nofail(dev); |
8a14daa5 | 271 | |
41445300 | 272 | d = pci_create_simple(b, 0, device_name); |
57a0f0c6 | 273 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
274 | f = *pi440fx_state; |
275 | f->system_memory = address_space_mem; | |
276 | f->pci_address_space = pci_address_space; | |
277 | f->ram_memory = ram_memory; | |
40c5dce9 | 278 | memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, |
ae0a5466 AK |
279 | pci_hole_start, pci_hole_size); |
280 | memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); | |
40c5dce9 | 281 | memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64", |
ae0a5466 AK |
282 | f->pci_address_space, |
283 | pci_hole64_start, pci_hole64_size); | |
284 | if (pci_hole64_size) { | |
285 | memory_region_add_subregion(f->system_memory, pci_hole64_start, | |
286 | &f->pci_hole_64bit); | |
287 | } | |
40c5dce9 | 288 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 289 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
290 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
291 | &f->smram_region, 1); | |
292 | memory_region_set_enabled(&f->smram_region, false); | |
3cd2cf43 | 293 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 294 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
2725aec7 | 295 | for (i = 0; i < 12; ++i) { |
3cd2cf43 | 296 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
297 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
298 | PAM_EXPAN_SIZE); | |
2725aec7 | 299 | } |
8a14daa5 | 300 | |
bf09551a SS |
301 | /* Xen supports additional interrupt routes from the PCI devices to |
302 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
303 | * connected to the IOAPIC directly. | |
304 | * These additional routes can be discovered through ACPI. */ | |
305 | if (xen_enabled()) { | |
306 | piix3 = DO_UPCAST(PIIX3State, dev, | |
307 | pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); | |
308 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, | |
309 | piix3, XEN_PIIX_NUM_PIRQS); | |
310 | } else { | |
311 | piix3 = DO_UPCAST(PIIX3State, dev, | |
312 | pci_create_simple_multifunction(b, -1, true, "PIIX3")); | |
313 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, | |
314 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 315 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 316 | } |
7cd9eee0 | 317 | piix3->pic = pic; |
d93a8a43 | 318 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); |
41445300 | 319 | |
7cd9eee0 | 320 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 321 | |
ec5f92ce | 322 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 323 | if (ram_size > 255) { |
ec5f92ce | 324 | ram_size = 255; |
2aedfa46 HT |
325 | } |
326 | d->config[0x57] = ram_size; | |
ec5f92ce | 327 | |
ae0a5466 AK |
328 | i440fx_update_memory_mappings(f); |
329 | ||
502a5395 PB |
330 | return b; |
331 | } | |
332 | ||
41445300 | 333 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, |
60573079 | 334 | ISABus **isa_bus, qemu_irq *pic, |
aee97b84 AK |
335 | MemoryRegion *address_space_mem, |
336 | MemoryRegion *address_space_io, | |
ae0a5466 | 337 | ram_addr_t ram_size, |
a8170e5e AK |
338 | hwaddr pci_hole_start, |
339 | hwaddr pci_hole_size, | |
340 | hwaddr pci_hole64_start, | |
341 | hwaddr pci_hole64_size, | |
ae0a5466 AK |
342 | MemoryRegion *pci_memory, MemoryRegion *ram_memory) |
343 | ||
41445300 AP |
344 | { |
345 | PCIBus *b; | |
346 | ||
57a0f0c6 DW |
347 | b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state, |
348 | piix3_devfn, isa_bus, pic, | |
ae0a5466 AK |
349 | address_space_mem, address_space_io, ram_size, |
350 | pci_hole_start, pci_hole_size, | |
d50c6c8b | 351 | pci_hole64_start, pci_hole64_size, |
ae0a5466 | 352 | pci_memory, ram_memory); |
41445300 AP |
353 | return b; |
354 | } | |
355 | ||
502a5395 | 356 | /* PIIX3 PCI to ISA bridge */ |
ab431c28 IY |
357 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
358 | { | |
359 | qemu_set_irq(piix3->pic[pic_irq], | |
360 | !!(piix3->pic_levels & | |
09de0f46 | 361 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
362 | (pic_irq * PIIX_NUM_PIRQS)))); |
363 | } | |
502a5395 | 364 | |
afe3ef1d | 365 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
366 | { |
367 | int pic_irq; | |
368 | uint64_t mask; | |
369 | ||
370 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
371 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
372 | return; | |
373 | } | |
374 | ||
375 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
376 | piix3->pic_levels &= ~mask; | |
377 | piix3->pic_levels |= mask * !!level; | |
378 | ||
afe3ef1d | 379 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
380 | } |
381 | ||
382 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 383 | { |
7cd9eee0 | 384 | PIIX3State *piix3 = opaque; |
afe3ef1d | 385 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 386 | } |
502a5395 | 387 | |
3afa9bb4 MT |
388 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
389 | { | |
390 | PIIX3State *piix3 = opaque; | |
391 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
392 | PCIINTxRoute route; | |
393 | ||
394 | if (irq < PIIX_NUM_PIC_IRQS) { | |
395 | route.mode = PCI_INTX_ENABLED; | |
396 | route.irq = irq; | |
397 | } else { | |
398 | route.mode = PCI_INTX_DISABLED; | |
399 | route.irq = -1; | |
400 | } | |
401 | return route; | |
402 | } | |
403 | ||
ab431c28 IY |
404 | /* irq routing is changed. so rebuild bitmap */ |
405 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
406 | { | |
407 | int pirq; | |
408 | ||
409 | piix3->pic_levels = 0; | |
410 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
411 | piix3_set_irq_level(piix3, pirq, | |
afe3ef1d | 412 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
ab431c28 IY |
413 | } |
414 | } | |
415 | ||
416 | static void piix3_write_config(PCIDevice *dev, | |
417 | uint32_t address, uint32_t val, int len) | |
418 | { | |
419 | pci_default_write_config(dev, address, val, len); | |
420 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
421 | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); | |
422 | int pic_irq; | |
0ae16251 JK |
423 | |
424 | pci_bus_fire_intx_routing_notifier(piix3->dev.bus); | |
ab431c28 IY |
425 | piix3_update_irq_levels(piix3); |
426 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
427 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 428 | } |
502a5395 PB |
429 | } |
430 | } | |
431 | ||
bf09551a SS |
432 | static void piix3_write_config_xen(PCIDevice *dev, |
433 | uint32_t address, uint32_t val, int len) | |
434 | { | |
435 | xen_piix_pci_write_config_client(address, val, len); | |
436 | piix3_write_config(dev, address, val, len); | |
437 | } | |
438 | ||
15a1956a | 439 | static void piix3_reset(void *opaque) |
502a5395 | 440 | { |
fd37d881 JQ |
441 | PIIX3State *d = opaque; |
442 | uint8_t *pci_conf = d->dev.config; | |
502a5395 | 443 | |
c9721215 | 444 | pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
502a5395 PB |
445 | pci_conf[0x05] = 0x00; |
446 | pci_conf[0x06] = 0x00; | |
c9721215 | 447 | pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
502a5395 PB |
448 | pci_conf[0x4c] = 0x4d; |
449 | pci_conf[0x4e] = 0x03; | |
450 | pci_conf[0x4f] = 0x00; | |
451 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
452 | pci_conf[0x61] = 0x80; |
453 | pci_conf[0x62] = 0x80; | |
454 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
455 | pci_conf[0x69] = 0x02; |
456 | pci_conf[0x70] = 0x80; | |
457 | pci_conf[0x76] = 0x0c; | |
458 | pci_conf[0x77] = 0x0c; | |
459 | pci_conf[0x78] = 0x02; | |
460 | pci_conf[0x79] = 0x00; | |
461 | pci_conf[0x80] = 0x00; | |
462 | pci_conf[0x82] = 0x00; | |
463 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
464 | pci_conf[0xa2] = 0x00; |
465 | pci_conf[0xa3] = 0x00; | |
466 | pci_conf[0xa4] = 0x00; | |
467 | pci_conf[0xa5] = 0x00; | |
468 | pci_conf[0xa6] = 0x00; | |
469 | pci_conf[0xa7] = 0x00; | |
470 | pci_conf[0xa8] = 0x0f; | |
471 | pci_conf[0xaa] = 0x00; | |
472 | pci_conf[0xab] = 0x00; | |
473 | pci_conf[0xac] = 0x00; | |
474 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
475 | |
476 | d->pic_levels = 0; | |
1ec4ba74 | 477 | d->rcr = 0; |
ab431c28 IY |
478 | } |
479 | ||
480 | static int piix3_post_load(void *opaque, int version_id) | |
481 | { | |
482 | PIIX3State *piix3 = opaque; | |
483 | piix3_update_irq_levels(piix3); | |
484 | return 0; | |
e735b55a | 485 | } |
15a1956a | 486 | |
e735b55a IY |
487 | static void piix3_pre_save(void *opaque) |
488 | { | |
489 | int i; | |
490 | PIIX3State *piix3 = opaque; | |
491 | ||
492 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
493 | piix3->pci_irq_levels_vmstate[i] = | |
494 | pci_bus_get_irq_level(piix3->dev.bus, i); | |
495 | } | |
502a5395 PB |
496 | } |
497 | ||
1ec4ba74 LE |
498 | static bool piix3_rcr_needed(void *opaque) |
499 | { | |
500 | PIIX3State *piix3 = opaque; | |
501 | ||
502 | return (piix3->rcr != 0); | |
503 | } | |
504 | ||
505 | static const VMStateDescription vmstate_piix3_rcr = { | |
506 | .name = "PIIX3/rcr", | |
507 | .version_id = 1, | |
508 | .minimum_version_id = 1, | |
509 | .fields = (VMStateField []) { | |
510 | VMSTATE_UINT8(rcr, PIIX3State), | |
511 | VMSTATE_END_OF_LIST() | |
512 | } | |
513 | }; | |
514 | ||
d1f171bd JQ |
515 | static const VMStateDescription vmstate_piix3 = { |
516 | .name = "PIIX3", | |
517 | .version_id = 3, | |
518 | .minimum_version_id = 2, | |
519 | .minimum_version_id_old = 2, | |
ab431c28 | 520 | .post_load = piix3_post_load, |
e735b55a | 521 | .pre_save = piix3_pre_save, |
1ec4ba74 | 522 | .fields = (VMStateField[]) { |
d1f171bd | 523 | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
e735b55a IY |
524 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
525 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 526 | VMSTATE_END_OF_LIST() |
1ec4ba74 LE |
527 | }, |
528 | .subsections = (VMStateSubsection[]) { | |
529 | { | |
530 | .vmsd = &vmstate_piix3_rcr, | |
531 | .needed = piix3_rcr_needed, | |
532 | }, | |
533 | { 0 } | |
534 | } | |
535 | }; | |
536 | ||
537 | ||
538 | static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) | |
539 | { | |
540 | PIIX3State *d = opaque; | |
541 | ||
542 | if (val & 4) { | |
543 | qemu_system_reset_request(); | |
544 | return; | |
da64182c | 545 | } |
1ec4ba74 LE |
546 | d->rcr = val & 2; /* keep System Reset type only */ |
547 | } | |
548 | ||
549 | static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) | |
550 | { | |
551 | PIIX3State *d = opaque; | |
552 | ||
553 | return d->rcr; | |
554 | } | |
555 | ||
556 | static const MemoryRegionOps rcr_ops = { | |
557 | .read = rcr_read, | |
558 | .write = rcr_write, | |
559 | .endianness = DEVICE_LITTLE_ENDIAN | |
d1f171bd | 560 | }; |
1941d19c | 561 | |
fd37d881 | 562 | static int piix3_initfn(PCIDevice *dev) |
502a5395 | 563 | { |
fd37d881 | 564 | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
502a5395 | 565 | |
d93a8a43 | 566 | isa_bus_new(DEVICE(d), pci_address_space_io(dev)); |
1ec4ba74 | 567 | |
40c5dce9 PB |
568 | memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, |
569 | "piix3-reset-control", 1); | |
1ec4ba74 LE |
570 | memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
571 | &d->rcr_mem, 1); | |
572 | ||
a08d4367 | 573 | qemu_register_reset(piix3_reset, d); |
81a322d4 | 574 | return 0; |
502a5395 | 575 | } |
5c2b87e3 | 576 | |
40021f08 AL |
577 | static void piix3_class_init(ObjectClass *klass, void *data) |
578 | { | |
39bffca2 | 579 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
580 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
581 | ||
39bffca2 AL |
582 | dc->desc = "ISA bridge"; |
583 | dc->vmsd = &vmstate_piix3; | |
584 | dc->no_user = 1, | |
40021f08 AL |
585 | k->no_hotplug = 1; |
586 | k->init = piix3_initfn; | |
587 | k->config_write = piix3_write_config; | |
588 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
589 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
590 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 AL |
591 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
592 | } | |
593 | ||
4240abff | 594 | static const TypeInfo piix3_info = { |
39bffca2 AL |
595 | .name = "PIIX3", |
596 | .parent = TYPE_PCI_DEVICE, | |
597 | .instance_size = sizeof(PIIX3State), | |
598 | .class_init = piix3_class_init, | |
e855761c AL |
599 | }; |
600 | ||
40021f08 AL |
601 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
602 | { | |
39bffca2 | 603 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
604 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
605 | ||
39bffca2 AL |
606 | dc->desc = "ISA bridge"; |
607 | dc->vmsd = &vmstate_piix3; | |
608 | dc->no_user = 1; | |
40021f08 AL |
609 | k->no_hotplug = 1; |
610 | k->init = piix3_initfn; | |
611 | k->config_write = piix3_write_config_xen; | |
612 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
613 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
614 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 | 615 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
e855761c AL |
616 | }; |
617 | ||
4240abff | 618 | static const TypeInfo piix3_xen_info = { |
39bffca2 AL |
619 | .name = "PIIX3-xen", |
620 | .parent = TYPE_PCI_DEVICE, | |
621 | .instance_size = sizeof(PIIX3State), | |
622 | .class_init = piix3_xen_class_init, | |
40021f08 AL |
623 | }; |
624 | ||
625 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
626 | { | |
39bffca2 | 627 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
628 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
629 | ||
630 | k->no_hotplug = 1; | |
631 | k->init = i440fx_initfn; | |
632 | k->config_write = i440fx_write_config; | |
633 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
634 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
635 | k->revision = 0x02; | |
636 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
637 | dc->desc = "Host bridge"; |
638 | dc->no_user = 1; | |
639 | dc->vmsd = &vmstate_i440fx; | |
40021f08 AL |
640 | } |
641 | ||
4240abff | 642 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 643 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
644 | .parent = TYPE_PCI_DEVICE, |
645 | .instance_size = sizeof(PCII440FXState), | |
646 | .class_init = i440fx_class_init, | |
8a14daa5 GH |
647 | }; |
648 | ||
568f0690 DG |
649 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
650 | PCIBus *rootbus) | |
651 | { | |
652 | /* For backwards compat with old device paths */ | |
653 | return "0000"; | |
654 | } | |
655 | ||
999e12bb AL |
656 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
657 | { | |
39bffca2 | 658 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 659 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 660 | |
568f0690 | 661 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 662 | dc->realize = i440fx_pcihost_realize; |
39bffca2 AL |
663 | dc->fw_name = "pci"; |
664 | dc->no_user = 1; | |
999e12bb AL |
665 | } |
666 | ||
4240abff | 667 | static const TypeInfo i440fx_pcihost_info = { |
1d0d4aa4 | 668 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
8558d942 | 669 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 670 | .instance_size = sizeof(I440FXState), |
a3560fbf | 671 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 672 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
673 | }; |
674 | ||
83f7d43a | 675 | static void i440fx_register_types(void) |
8a14daa5 | 676 | { |
39bffca2 AL |
677 | type_register_static(&i440fx_info); |
678 | type_register_static(&piix3_info); | |
679 | type_register_static(&piix3_xen_info); | |
680 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 681 | } |
83f7d43a AF |
682 | |
683 | type_init(i440fx_register_types) |