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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
b6a0aa05 | 25 | #include "qemu/osdep.h" |
0d09e41a | 26 | #include "hw/i386/pc.h" |
64552b6b | 27 | #include "hw/irq.h" |
83c9f4ca PB |
28 | #include "hw/pci/pci.h" |
29 | #include "hw/pci/pci_host.h" | |
a27bd6c7 | 30 | #include "hw/qdev-properties.h" |
0d09e41a | 31 | #include "hw/isa/isa.h" |
83c9f4ca | 32 | #include "hw/sysbus.h" |
da34e65c | 33 | #include "qapi/error.h" |
1de7afc9 | 34 | #include "qemu/range.h" |
0d09e41a | 35 | #include "hw/xen/xen.h" |
ca77ee28 | 36 | #include "migration/qemu-file-types.h" |
d6454270 | 37 | #include "migration/vmstate.h" |
0d09e41a | 38 | #include "hw/pci-host/pam.h" |
71e8a915 | 39 | #include "sysemu/reset.h" |
54d31236 | 40 | #include "sysemu/runstate.h" |
39848901 IM |
41 | #include "hw/i386/ioapic.h" |
42 | #include "qapi/visitor.h" | |
8d211f62 | 43 | #include "qemu/error-report.h" |
87ecb68b | 44 | |
56594fe3 IY |
45 | /* |
46 | * I440FX chipset data sheet. | |
9b178f0e | 47 | * https://wiki.qemu.org/File:29054901.pdf |
56594fe3 IY |
48 | */ |
49 | ||
1d0d4aa4 IM |
50 | #define I440FX_PCI_HOST_BRIDGE(obj) \ |
51 | OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE) | |
52 | ||
67c332fd AF |
53 | typedef struct I440FXState { |
54 | PCIHostState parent_obj; | |
01c9742d | 55 | Range pci_hole; |
39848901 | 56 | uint64_t pci_hole64_size; |
9fa99d25 | 57 | bool pci_hole64_fix; |
04c7d8b8 | 58 | uint32_t short_root_bus; |
67c332fd | 59 | } I440FXState; |
502a5395 | 60 | |
ab431c28 | 61 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 62 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 63 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 64 | #define PIIX_PIRQC 0x60 |
e735b55a | 65 | |
fd37d881 JQ |
66 | typedef struct PIIX3State { |
67 | PCIDevice dev; | |
ab431c28 IY |
68 | |
69 | /* | |
70 | * bitmap to track pic levels. | |
71 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
72 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
73 | * | |
74 | * PIRQ is mapped to PIC pins, we track it by | |
75 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
76 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
77 | */ | |
78 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
79 | #error "unable to encode pic state in 64bit in pic_levels." | |
80 | #endif | |
81 | uint64_t pic_levels; | |
82 | ||
bd7dce87 | 83 | qemu_irq *pic; |
e735b55a IY |
84 | |
85 | /* This member isn't used. Just for save/load compatibility */ | |
86 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
1ec4ba74 LE |
87 | |
88 | /* Reset Control Register contents */ | |
89 | uint8_t rcr; | |
90 | ||
91 | /* IO memory region for Reset Control Register (RCR_IOPORT) */ | |
92 | MemoryRegion rcr_mem; | |
7cd9eee0 | 93 | } PIIX3State; |
bd7dce87 | 94 | |
b7c69719 GA |
95 | #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" |
96 | #define PIIX3_PCI_DEVICE(obj) \ | |
97 | OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE) | |
98 | ||
57a0f0c6 DW |
99 | #define I440FX_PCI_DEVICE(obj) \ |
100 | OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) | |
101 | ||
ee31e901 LQ |
102 | #define TYPE_PIIX3_DEVICE "PIIX3" |
103 | #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" | |
104 | ||
0a3bacf3 | 105 | struct PCII440FXState { |
2aedfa46 HT |
106 | /*< private >*/ |
107 | PCIDevice parent_obj; | |
108 | /*< public >*/ | |
109 | ||
ae0a5466 AK |
110 | MemoryRegion *system_memory; |
111 | MemoryRegion *pci_address_space; | |
112 | MemoryRegion *ram_memory; | |
ae0a5466 AK |
113 | PAMMemoryRegion pam_regions[13]; |
114 | MemoryRegion smram_region; | |
fe6567d5 | 115 | MemoryRegion smram, low_smram; |
0a3bacf3 JQ |
116 | }; |
117 | ||
f2c688bb IY |
118 | |
119 | #define I440FX_PAM 0x59 | |
120 | #define I440FX_PAM_SIZE 7 | |
121 | #define I440FX_SMRAM 0x72 | |
122 | ||
9fa99d25 MA |
123 | /* Keep it 2G to comply with older win32 guests */ |
124 | #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) | |
125 | ||
e33d22fa EH |
126 | /* Older coreboot versions (4.0 and older) read a config register that doesn't |
127 | * exist in real hardware, to get the RAM size from QEMU. | |
128 | */ | |
129 | #define I440FX_COREBOOT_RAM_SIZE 0x57 | |
130 | ||
ab431c28 | 131 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 132 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
133 | static void piix3_write_config_xen(PCIDevice *dev, |
134 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
135 | |
136 | /* return the global irq number corresponding to a given device irq | |
137 | pin. We could also use the bus number to have a more precise | |
138 | mapping. */ | |
ab431c28 | 139 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
140 | { |
141 | int slot_addend; | |
142 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 143 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 144 | } |
502a5395 | 145 | |
0a3bacf3 | 146 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 147 | { |
410edd92 | 148 | int i; |
2aedfa46 | 149 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 150 | |
72124c01 | 151 | memory_region_transaction_begin(); |
0118c01c | 152 | for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { |
410edd92 | 153 | pam_update(&d->pam_regions[i], i, |
66175626 | 154 | pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); |
ee0ea1d0 | 155 | } |
3de70c08 PB |
156 | memory_region_set_enabled(&d->smram_region, |
157 | !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); | |
fe6567d5 PB |
158 | memory_region_set_enabled(&d->smram, |
159 | pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); | |
72124c01 | 160 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
161 | } |
162 | ||
ee0ea1d0 | 163 | |
0a3bacf3 | 164 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
165 | uint32_t address, uint32_t val, int len) |
166 | { | |
57a0f0c6 | 167 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 168 | |
ee0ea1d0 | 169 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 170 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
171 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
172 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 173 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 174 | } |
ee0ea1d0 FB |
175 | } |
176 | ||
0c7d19e5 | 177 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 178 | { |
0a3bacf3 | 179 | PCII440FXState *d = opaque; |
2aedfa46 | 180 | PCIDevice *pd = PCI_DEVICE(d); |
52fc1d83 | 181 | int ret, i; |
f809c605 | 182 | uint8_t smm_enabled; |
ee0ea1d0 | 183 | |
2aedfa46 | 184 | ret = pci_device_load(pd, f); |
ee0ea1d0 FB |
185 | if (ret < 0) |
186 | return ret; | |
187 | i440fx_update_memory_mappings(d); | |
f809c605 | 188 | qemu_get_8s(f, &smm_enabled); |
52fc1d83 | 189 | |
e735b55a IY |
190 | if (version_id == 2) { |
191 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
192 | qemu_get_be32(f); /* dummy load for compatibility */ | |
193 | } | |
194 | } | |
52fc1d83 | 195 | |
ee0ea1d0 FB |
196 | return 0; |
197 | } | |
198 | ||
e59fb374 | 199 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
200 | { |
201 | PCII440FXState *d = opaque; | |
202 | ||
203 | i440fx_update_memory_mappings(d); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static const VMStateDescription vmstate_i440fx = { | |
208 | .name = "I440FX", | |
209 | .version_id = 3, | |
210 | .minimum_version_id = 3, | |
211 | .minimum_version_id_old = 1, | |
212 | .load_state_old = i440fx_load_old, | |
752ff2fa | 213 | .post_load = i440fx_post_load, |
d49805ae | 214 | .fields = (VMStateField[]) { |
2aedfa46 | 215 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
f809c605 PB |
216 | /* Used to be smm_enabled, which was basically always zero because |
217 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. | |
218 | */ | |
219 | VMSTATE_UNUSED(1), | |
0c7d19e5 JQ |
220 | VMSTATE_END_OF_LIST() |
221 | } | |
222 | }; | |
223 | ||
39848901 | 224 | static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, |
d7bce999 | 225 | const char *name, void *opaque, |
39848901 IM |
226 | Error **errp) |
227 | { | |
228 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
a0efbf16 MA |
229 | uint64_t val64; |
230 | uint32_t value; | |
39848901 | 231 | |
a0efbf16 MA |
232 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); |
233 | value = val64; | |
234 | assert(value == val64); | |
51e72bc1 | 235 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
236 | } |
237 | ||
238 | static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, | |
d7bce999 | 239 | const char *name, void *opaque, |
39848901 IM |
240 | Error **errp) |
241 | { | |
242 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
a0efbf16 MA |
243 | uint64_t val64; |
244 | uint32_t value; | |
39848901 | 245 | |
a0efbf16 MA |
246 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; |
247 | value = val64; | |
248 | assert(value == val64); | |
51e72bc1 | 249 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
250 | } |
251 | ||
9fa99d25 MA |
252 | /* |
253 | * The 64bit PCI hole start is set by the Guest firmware | |
254 | * as the address of the first 64bit PCI MEM resource. | |
255 | * If no PCI device has resources on the 64bit area, | |
256 | * the 64bit PCI hole will start after "over 4G RAM" and the | |
257 | * reserved space for memory hotplug if any. | |
258 | */ | |
ccef5b1f | 259 | static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) |
39848901 | 260 | { |
2028fdf3 | 261 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
9fa99d25 | 262 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
2028fdf3 | 263 | Range w64; |
a0efbf16 | 264 | uint64_t value; |
2028fdf3 MT |
265 | |
266 | pci_bus_get_w64_range(h->bus, &w64); | |
a0efbf16 | 267 | value = range_is_empty(&w64) ? 0 : range_lob(&w64); |
9fa99d25 MA |
268 | if (!value && s->pci_hole64_fix) { |
269 | value = pc_pci_hole64_start(); | |
270 | } | |
ccef5b1f LE |
271 | return value; |
272 | } | |
273 | ||
274 | static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, | |
275 | const char *name, | |
276 | void *opaque, Error **errp) | |
277 | { | |
278 | uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); | |
279 | ||
280 | visit_type_uint64(v, name, &hole64_start, errp); | |
39848901 IM |
281 | } |
282 | ||
9fa99d25 MA |
283 | /* |
284 | * The 64bit PCI hole end is set by the Guest firmware | |
285 | * as the address of the last 64bit PCI MEM resource. | |
286 | * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE | |
287 | * that can be configured by the user. | |
288 | */ | |
39848901 | 289 | static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, |
d7bce999 | 290 | const char *name, void *opaque, |
39848901 IM |
291 | Error **errp) |
292 | { | |
2028fdf3 | 293 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
9fa99d25 | 294 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
ed6bb4b5 | 295 | uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); |
2028fdf3 | 296 | Range w64; |
9fa99d25 | 297 | uint64_t value, hole64_end; |
2028fdf3 MT |
298 | |
299 | pci_bus_get_w64_range(h->bus, &w64); | |
a0efbf16 | 300 | value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; |
9fa99d25 MA |
301 | hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); |
302 | if (s->pci_hole64_fix && value < hole64_end) { | |
303 | value = hole64_end; | |
304 | } | |
a0efbf16 | 305 | visit_type_uint64(v, name, &value, errp); |
39848901 IM |
306 | } |
307 | ||
a3560fbf | 308 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 309 | { |
a3560fbf | 310 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
502a5395 | 311 | |
a3560fbf | 312 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 313 | "pci-conf-idx", 4); |
a3560fbf | 314 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 315 | "pci-conf-data", 4); |
39848901 | 316 | |
1e507bb0 | 317 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", |
39848901 IM |
318 | i440fx_pcihost_get_pci_hole_start, |
319 | NULL, NULL, NULL, NULL); | |
320 | ||
1e507bb0 | 321 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", |
39848901 IM |
322 | i440fx_pcihost_get_pci_hole_end, |
323 | NULL, NULL, NULL, NULL); | |
324 | ||
1e507bb0 | 325 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", |
39848901 IM |
326 | i440fx_pcihost_get_pci_hole64_start, |
327 | NULL, NULL, NULL, NULL); | |
328 | ||
1e507bb0 | 329 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", |
39848901 IM |
330 | i440fx_pcihost_get_pci_hole64_end, |
331 | NULL, NULL, NULL, NULL); | |
a3560fbf | 332 | } |
502a5395 | 333 | |
a3560fbf HT |
334 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
335 | { | |
336 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
337 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
338 | ||
339 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
340 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
341 | ||
342 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
343 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
37abf8d2 PH |
344 | |
345 | /* register i440fx 0xcf8 port as coalesced pio */ | |
346 | memory_region_set_flush_coalesced(&s->data_mem); | |
347 | memory_region_add_coalescing(&s->conf_mem, 0, 4); | |
8a14daa5 | 348 | } |
502a5395 | 349 | |
9af21dbe | 350 | static void i440fx_realize(PCIDevice *dev, Error **errp) |
8a14daa5 | 351 | { |
2aedfa46 | 352 | dev->config[I440FX_SMRAM] = 0x02; |
8d211f62 BD |
353 | |
354 | if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { | |
3dc6f869 | 355 | warn_report("i440fx doesn't support emulated iommu"); |
8d211f62 | 356 | } |
8a14daa5 GH |
357 | } |
358 | ||
7bb836e4 MT |
359 | PCIBus *i440fx_init(const char *host_type, const char *pci_type, |
360 | PCII440FXState **pi440fx_state, | |
44fc8c5e IM |
361 | int *piix3_devfn, |
362 | ISABus **isa_bus, qemu_irq *pic, | |
363 | MemoryRegion *address_space_mem, | |
364 | MemoryRegion *address_space_io, | |
365 | ram_addr_t ram_size, | |
ddaaefb4 | 366 | ram_addr_t below_4g_mem_size, |
39848901 | 367 | ram_addr_t above_4g_mem_size, |
44fc8c5e IM |
368 | MemoryRegion *pci_address_space, |
369 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
370 | { |
371 | DeviceState *dev; | |
372 | PCIBus *b; | |
373 | PCIDevice *d; | |
8558d942 | 374 | PCIHostState *s; |
7cd9eee0 | 375 | PIIX3State *piix3; |
ae0a5466 | 376 | PCII440FXState *f; |
2725aec7 | 377 | unsigned i; |
39848901 | 378 | I440FXState *i440fx; |
8a14daa5 | 379 | |
7bb836e4 | 380 | dev = qdev_create(NULL, host_type); |
8558d942 | 381 | s = PCI_HOST_BRIDGE(dev); |
1115ff6d DG |
382 | b = pci_root_bus_new(dev, NULL, pci_address_space, |
383 | address_space_io, 0, TYPE_PCI_BUS); | |
8a14daa5 | 384 | s->bus = b; |
f05f6b4a | 385 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 386 | qdev_init_nofail(dev); |
8a14daa5 | 387 | |
7bb836e4 | 388 | d = pci_create_simple(b, 0, pci_type); |
57a0f0c6 | 389 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
390 | f = *pi440fx_state; |
391 | f->system_memory = address_space_mem; | |
392 | f->pci_address_space = pci_address_space; | |
393 | f->ram_memory = ram_memory; | |
39848901 IM |
394 | |
395 | i440fx = I440FX_PCI_HOST_BRIDGE(dev); | |
a0efbf16 MA |
396 | range_set_bounds(&i440fx->pci_hole, below_4g_mem_size, |
397 | IO_APIC_DEFAULT_ADDRESS - 1); | |
39848901 | 398 | |
83d08f26 MT |
399 | /* setup pci memory mapping */ |
400 | pc_pci_as_mapping_init(OBJECT(f), f->system_memory, | |
401 | f->pci_address_space); | |
402 | ||
fe6567d5 | 403 | /* if *disabled* show SMRAM to all CPUs */ |
40c5dce9 | 404 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 405 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
406 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
407 | &f->smram_region, 1); | |
fe6567d5 PB |
408 | memory_region_set_enabled(&f->smram_region, true); |
409 | ||
410 | /* smram, as seen by SMM CPUs */ | |
411 | memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32); | |
412 | memory_region_set_enabled(&f->smram, true); | |
413 | memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", | |
f809c605 | 414 | f->ram_memory, 0xa0000, 0x20000); |
fe6567d5 PB |
415 | memory_region_set_enabled(&f->low_smram, true); |
416 | memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram); | |
417 | object_property_add_const_link(qdev_get_machine(), "smram", | |
418 | OBJECT(&f->smram), &error_abort); | |
419 | ||
3cd2cf43 | 420 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 421 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
0118c01c | 422 | for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { |
3cd2cf43 | 423 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
424 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
425 | PAM_EXPAN_SIZE); | |
2725aec7 | 426 | } |
8a14daa5 | 427 | |
bf09551a SS |
428 | /* Xen supports additional interrupt routes from the PCI devices to |
429 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
430 | * connected to the IOAPIC directly. | |
431 | * These additional routes can be discovered through ACPI. */ | |
432 | if (xen_enabled()) { | |
b7c69719 | 433 | PCIDevice *pci_dev = pci_create_simple_multifunction(b, |
ee31e901 | 434 | -1, true, TYPE_PIIX3_XEN_DEVICE); |
b7c69719 | 435 | piix3 = PIIX3_PCI_DEVICE(pci_dev); |
bf09551a SS |
436 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
437 | piix3, XEN_PIIX_NUM_PIRQS); | |
438 | } else { | |
b7c69719 | 439 | PCIDevice *pci_dev = pci_create_simple_multifunction(b, |
ee31e901 | 440 | -1, true, TYPE_PIIX3_DEVICE); |
b7c69719 | 441 | piix3 = PIIX3_PCI_DEVICE(pci_dev); |
bf09551a SS |
442 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, |
443 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 444 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 445 | } |
7cd9eee0 | 446 | piix3->pic = pic; |
d93a8a43 | 447 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); |
41445300 | 448 | |
7cd9eee0 | 449 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 450 | |
ec5f92ce | 451 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 452 | if (ram_size > 255) { |
ec5f92ce | 453 | ram_size = 255; |
2aedfa46 | 454 | } |
e33d22fa | 455 | d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; |
ec5f92ce | 456 | |
ae0a5466 AK |
457 | i440fx_update_memory_mappings(f); |
458 | ||
502a5395 PB |
459 | return b; |
460 | } | |
461 | ||
277e9340 MT |
462 | PCIBus *find_i440fx(void) |
463 | { | |
464 | PCIHostState *s = OBJECT_CHECK(PCIHostState, | |
465 | object_resolve_path("/machine/i440fx", NULL), | |
466 | TYPE_PCI_HOST_BRIDGE); | |
467 | return s ? s->bus : NULL; | |
468 | } | |
469 | ||
502a5395 | 470 | /* PIIX3 PCI to ISA bridge */ |
ab431c28 IY |
471 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
472 | { | |
473 | qemu_set_irq(piix3->pic[pic_irq], | |
474 | !!(piix3->pic_levels & | |
09de0f46 | 475 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
476 | (pic_irq * PIIX_NUM_PIRQS)))); |
477 | } | |
502a5395 | 478 | |
2c9ecdeb | 479 | static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
480 | { |
481 | int pic_irq; | |
482 | uint64_t mask; | |
483 | ||
484 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
485 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
486 | return; | |
487 | } | |
488 | ||
489 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
490 | piix3->pic_levels &= ~mask; | |
491 | piix3->pic_levels |= mask * !!level; | |
2c9ecdeb PD |
492 | } |
493 | ||
494 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) | |
495 | { | |
496 | int pic_irq; | |
497 | ||
498 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
499 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
500 | return; | |
501 | } | |
502 | ||
503 | piix3_set_irq_level_internal(piix3, pirq, level); | |
ab431c28 | 504 | |
afe3ef1d | 505 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
506 | } |
507 | ||
508 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 509 | { |
7cd9eee0 | 510 | PIIX3State *piix3 = opaque; |
afe3ef1d | 511 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 512 | } |
502a5395 | 513 | |
3afa9bb4 MT |
514 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
515 | { | |
516 | PIIX3State *piix3 = opaque; | |
517 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
518 | PCIINTxRoute route; | |
519 | ||
520 | if (irq < PIIX_NUM_PIC_IRQS) { | |
521 | route.mode = PCI_INTX_ENABLED; | |
522 | route.irq = irq; | |
523 | } else { | |
524 | route.mode = PCI_INTX_DISABLED; | |
525 | route.irq = -1; | |
526 | } | |
527 | return route; | |
528 | } | |
529 | ||
ab431c28 IY |
530 | /* irq routing is changed. so rebuild bitmap */ |
531 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
532 | { | |
fd56e061 | 533 | PCIBus *bus = pci_get_bus(&piix3->dev); |
ab431c28 IY |
534 | int pirq; |
535 | ||
536 | piix3->pic_levels = 0; | |
537 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
fd56e061 | 538 | piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); |
ab431c28 IY |
539 | } |
540 | } | |
541 | ||
542 | static void piix3_write_config(PCIDevice *dev, | |
543 | uint32_t address, uint32_t val, int len) | |
544 | { | |
545 | pci_default_write_config(dev, address, val, len); | |
546 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
b7c69719 | 547 | PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); |
ab431c28 | 548 | int pic_irq; |
0ae16251 | 549 | |
fd56e061 | 550 | pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); |
ab431c28 IY |
551 | piix3_update_irq_levels(piix3); |
552 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
553 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 554 | } |
502a5395 PB |
555 | } |
556 | } | |
557 | ||
bf09551a SS |
558 | static void piix3_write_config_xen(PCIDevice *dev, |
559 | uint32_t address, uint32_t val, int len) | |
560 | { | |
561 | xen_piix_pci_write_config_client(address, val, len); | |
562 | piix3_write_config(dev, address, val, len); | |
563 | } | |
564 | ||
15a1956a | 565 | static void piix3_reset(void *opaque) |
502a5395 | 566 | { |
fd37d881 JQ |
567 | PIIX3State *d = opaque; |
568 | uint8_t *pci_conf = d->dev.config; | |
502a5395 | 569 | |
c9721215 | 570 | pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
502a5395 PB |
571 | pci_conf[0x05] = 0x00; |
572 | pci_conf[0x06] = 0x00; | |
c9721215 | 573 | pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
502a5395 PB |
574 | pci_conf[0x4c] = 0x4d; |
575 | pci_conf[0x4e] = 0x03; | |
576 | pci_conf[0x4f] = 0x00; | |
577 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
578 | pci_conf[0x61] = 0x80; |
579 | pci_conf[0x62] = 0x80; | |
580 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
581 | pci_conf[0x69] = 0x02; |
582 | pci_conf[0x70] = 0x80; | |
583 | pci_conf[0x76] = 0x0c; | |
584 | pci_conf[0x77] = 0x0c; | |
585 | pci_conf[0x78] = 0x02; | |
586 | pci_conf[0x79] = 0x00; | |
587 | pci_conf[0x80] = 0x00; | |
588 | pci_conf[0x82] = 0x00; | |
589 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
590 | pci_conf[0xa2] = 0x00; |
591 | pci_conf[0xa3] = 0x00; | |
592 | pci_conf[0xa4] = 0x00; | |
593 | pci_conf[0xa5] = 0x00; | |
594 | pci_conf[0xa6] = 0x00; | |
595 | pci_conf[0xa7] = 0x00; | |
596 | pci_conf[0xa8] = 0x0f; | |
597 | pci_conf[0xaa] = 0x00; | |
598 | pci_conf[0xab] = 0x00; | |
599 | pci_conf[0xac] = 0x00; | |
600 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
601 | |
602 | d->pic_levels = 0; | |
1ec4ba74 | 603 | d->rcr = 0; |
ab431c28 IY |
604 | } |
605 | ||
606 | static int piix3_post_load(void *opaque, int version_id) | |
607 | { | |
608 | PIIX3State *piix3 = opaque; | |
2c9ecdeb PD |
609 | int pirq; |
610 | ||
611 | /* Because the i8259 has not been deserialized yet, qemu_irq_raise | |
612 | * might bring the system to a different state than the saved one; | |
613 | * for example, the interrupt could be masked but the i8259 would | |
614 | * not know that yet and would trigger an interrupt in the CPU. | |
615 | * | |
616 | * Here, we update irq levels without raising the interrupt. | |
617 | * Interrupt state will be deserialized separately through the i8259. | |
618 | */ | |
619 | piix3->pic_levels = 0; | |
620 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
621 | piix3_set_irq_level_internal(piix3, pirq, | |
fd56e061 | 622 | pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); |
2c9ecdeb | 623 | } |
ab431c28 | 624 | return 0; |
e735b55a | 625 | } |
15a1956a | 626 | |
44b1ff31 | 627 | static int piix3_pre_save(void *opaque) |
e735b55a IY |
628 | { |
629 | int i; | |
630 | PIIX3State *piix3 = opaque; | |
631 | ||
632 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
633 | piix3->pci_irq_levels_vmstate[i] = | |
fd56e061 | 634 | pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); |
e735b55a | 635 | } |
44b1ff31 DDAG |
636 | |
637 | return 0; | |
502a5395 PB |
638 | } |
639 | ||
1ec4ba74 LE |
640 | static bool piix3_rcr_needed(void *opaque) |
641 | { | |
642 | PIIX3State *piix3 = opaque; | |
643 | ||
644 | return (piix3->rcr != 0); | |
645 | } | |
646 | ||
647 | static const VMStateDescription vmstate_piix3_rcr = { | |
648 | .name = "PIIX3/rcr", | |
649 | .version_id = 1, | |
650 | .minimum_version_id = 1, | |
5cd8cada | 651 | .needed = piix3_rcr_needed, |
d49805ae | 652 | .fields = (VMStateField[]) { |
1ec4ba74 LE |
653 | VMSTATE_UINT8(rcr, PIIX3State), |
654 | VMSTATE_END_OF_LIST() | |
655 | } | |
656 | }; | |
657 | ||
d1f171bd JQ |
658 | static const VMStateDescription vmstate_piix3 = { |
659 | .name = "PIIX3", | |
660 | .version_id = 3, | |
661 | .minimum_version_id = 2, | |
ab431c28 | 662 | .post_load = piix3_post_load, |
e735b55a | 663 | .pre_save = piix3_pre_save, |
d49805ae | 664 | .fields = (VMStateField[]) { |
d1f171bd | 665 | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
e735b55a IY |
666 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
667 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 668 | VMSTATE_END_OF_LIST() |
1ec4ba74 | 669 | }, |
5cd8cada JQ |
670 | .subsections = (const VMStateDescription*[]) { |
671 | &vmstate_piix3_rcr, | |
672 | NULL | |
1ec4ba74 LE |
673 | } |
674 | }; | |
675 | ||
676 | ||
677 | static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) | |
678 | { | |
679 | PIIX3State *d = opaque; | |
680 | ||
681 | if (val & 4) { | |
cf83f140 | 682 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
1ec4ba74 | 683 | return; |
da64182c | 684 | } |
1ec4ba74 LE |
685 | d->rcr = val & 2; /* keep System Reset type only */ |
686 | } | |
687 | ||
688 | static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) | |
689 | { | |
690 | PIIX3State *d = opaque; | |
691 | ||
692 | return d->rcr; | |
693 | } | |
694 | ||
695 | static const MemoryRegionOps rcr_ops = { | |
696 | .read = rcr_read, | |
697 | .write = rcr_write, | |
698 | .endianness = DEVICE_LITTLE_ENDIAN | |
d1f171bd | 699 | }; |
1941d19c | 700 | |
9af21dbe | 701 | static void piix3_realize(PCIDevice *dev, Error **errp) |
502a5395 | 702 | { |
b7c69719 | 703 | PIIX3State *d = PIIX3_PCI_DEVICE(dev); |
502a5395 | 704 | |
d10e5432 MA |
705 | if (!isa_bus_new(DEVICE(d), get_system_memory(), |
706 | pci_address_space_io(dev), errp)) { | |
707 | return; | |
708 | } | |
1ec4ba74 | 709 | |
40c5dce9 PB |
710 | memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, |
711 | "piix3-reset-control", 1); | |
1ec4ba74 LE |
712 | memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
713 | &d->rcr_mem, 1); | |
714 | ||
a08d4367 | 715 | qemu_register_reset(piix3_reset, d); |
502a5395 | 716 | } |
5c2b87e3 | 717 | |
b7c69719 | 718 | static void pci_piix3_class_init(ObjectClass *klass, void *data) |
40021f08 | 719 | { |
39bffca2 | 720 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
721 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
722 | ||
39bffca2 AL |
723 | dc->desc = "ISA bridge"; |
724 | dc->vmsd = &vmstate_piix3; | |
2897ae02 | 725 | dc->hotpluggable = false; |
9af21dbe | 726 | k->realize = piix3_realize; |
40021f08 | 727 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
c9721215 DW |
728 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
729 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 | 730 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
81aab2ff MA |
731 | /* |
732 | * Reason: part of PIIX3 southbridge, needs to be wired up by | |
733 | * pc_piix.c's pc_init1() | |
734 | */ | |
e90f2a8c | 735 | dc->user_creatable = false; |
40021f08 AL |
736 | } |
737 | ||
b7c69719 GA |
738 | static const TypeInfo piix3_pci_type_info = { |
739 | .name = TYPE_PIIX3_PCI_DEVICE, | |
740 | .parent = TYPE_PCI_DEVICE, | |
741 | .instance_size = sizeof(PIIX3State), | |
742 | .abstract = true, | |
743 | .class_init = pci_piix3_class_init, | |
fd3b02c8 EH |
744 | .interfaces = (InterfaceInfo[]) { |
745 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
746 | { }, | |
747 | }, | |
b7c69719 GA |
748 | }; |
749 | ||
750 | static void piix3_class_init(ObjectClass *klass, void *data) | |
751 | { | |
752 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
753 | ||
754 | k->config_write = piix3_write_config; | |
755 | } | |
756 | ||
4240abff | 757 | static const TypeInfo piix3_info = { |
ee31e901 | 758 | .name = TYPE_PIIX3_DEVICE, |
b7c69719 | 759 | .parent = TYPE_PIIX3_PCI_DEVICE, |
39bffca2 | 760 | .class_init = piix3_class_init, |
e855761c AL |
761 | }; |
762 | ||
40021f08 AL |
763 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
764 | { | |
765 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
766 | ||
40021f08 | 767 | k->config_write = piix3_write_config_xen; |
e855761c AL |
768 | }; |
769 | ||
4240abff | 770 | static const TypeInfo piix3_xen_info = { |
ee31e901 | 771 | .name = TYPE_PIIX3_XEN_DEVICE, |
b7c69719 | 772 | .parent = TYPE_PIIX3_PCI_DEVICE, |
39bffca2 | 773 | .class_init = piix3_xen_class_init, |
40021f08 AL |
774 | }; |
775 | ||
776 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
777 | { | |
39bffca2 | 778 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
779 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
780 | ||
9af21dbe | 781 | k->realize = i440fx_realize; |
40021f08 AL |
782 | k->config_write = i440fx_write_config; |
783 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
784 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
785 | k->revision = 0x02; | |
786 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 | 787 | dc->desc = "Host bridge"; |
39bffca2 | 788 | dc->vmsd = &vmstate_i440fx; |
08c58f92 MA |
789 | /* |
790 | * PCI-facing part of the host bridge, not usable without the | |
791 | * host-facing part, which can't be device_add'ed, yet. | |
792 | */ | |
e90f2a8c | 793 | dc->user_creatable = false; |
2897ae02 | 794 | dc->hotpluggable = false; |
40021f08 AL |
795 | } |
796 | ||
4240abff | 797 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 798 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
799 | .parent = TYPE_PCI_DEVICE, |
800 | .instance_size = sizeof(PCII440FXState), | |
801 | .class_init = i440fx_class_init, | |
fd3b02c8 EH |
802 | .interfaces = (InterfaceInfo[]) { |
803 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
804 | { }, | |
805 | }, | |
8a14daa5 GH |
806 | }; |
807 | ||
595a4f07 TC |
808 | /* IGD Passthrough Host Bridge. */ |
809 | typedef struct { | |
810 | uint8_t offset; | |
811 | uint8_t len; | |
812 | } IGDHostInfo; | |
813 | ||
814 | /* Here we just expose minimal host bridge offset subset. */ | |
815 | static const IGDHostInfo igd_host_bridge_infos[] = { | |
816 | {0x08, 2}, /* revision id */ | |
817 | {0x2c, 2}, /* sybsystem vendor id */ | |
818 | {0x2e, 2}, /* sybsystem id */ | |
819 | {0x50, 2}, /* SNB: processor graphics control register */ | |
820 | {0x52, 2}, /* processor graphics control register */ | |
821 | {0xa4, 4}, /* SNB: graphics base of stolen memory */ | |
822 | {0xa8, 4}, /* SNB: base of GTT stolen memory */ | |
823 | }; | |
824 | ||
05607921 | 825 | static void host_pci_config_read(int pos, int len, uint32_t *val, Error **errp) |
595a4f07 | 826 | { |
05607921 | 827 | int rc, config_fd; |
595a4f07 | 828 | /* Access real host bridge. */ |
05607921 PMD |
829 | char *path = g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s", |
830 | 0, 0, 0, 0, "config"); | |
595a4f07 TC |
831 | |
832 | config_fd = open(path, O_RDWR); | |
833 | if (config_fd < 0) { | |
05607921 PMD |
834 | error_setg_errno(errp, errno, "Failed to open: %s", path); |
835 | goto out; | |
595a4f07 TC |
836 | } |
837 | ||
838 | if (lseek(config_fd, pos, SEEK_SET) != pos) { | |
05607921 PMD |
839 | error_setg_errno(errp, errno, "Failed to seek: %s", path); |
840 | goto out_close_fd; | |
595a4f07 | 841 | } |
349a3b1c | 842 | |
595a4f07 | 843 | do { |
349a3b1c | 844 | rc = read(config_fd, (uint8_t *)val, len); |
595a4f07 TC |
845 | } while (rc < 0 && (errno == EINTR || errno == EAGAIN)); |
846 | if (rc != len) { | |
05607921 | 847 | error_setg_errno(errp, errno, "Failed to read: %s", path); |
595a4f07 | 848 | } |
349a3b1c | 849 | |
05607921 | 850 | out_close_fd: |
e3fce97c | 851 | close(config_fd); |
05607921 PMD |
852 | out: |
853 | g_free(path); | |
595a4f07 TC |
854 | } |
855 | ||
05607921 | 856 | static void igd_pt_i440fx_realize(PCIDevice *pci_dev, Error **errp) |
595a4f07 TC |
857 | { |
858 | uint32_t val = 0; | |
05607921 | 859 | int i, num; |
595a4f07 | 860 | int pos, len; |
05607921 | 861 | Error *local_err = NULL; |
595a4f07 TC |
862 | |
863 | num = ARRAY_SIZE(igd_host_bridge_infos); | |
864 | for (i = 0; i < num; i++) { | |
865 | pos = igd_host_bridge_infos[i].offset; | |
866 | len = igd_host_bridge_infos[i].len; | |
05607921 PMD |
867 | host_pci_config_read(pos, len, &val, &local_err); |
868 | if (local_err) { | |
869 | error_propagate(errp, local_err); | |
870 | return; | |
595a4f07 TC |
871 | } |
872 | pci_default_write_config(pci_dev, pos, val, len); | |
873 | } | |
595a4f07 TC |
874 | } |
875 | ||
876 | static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data) | |
877 | { | |
878 | DeviceClass *dc = DEVICE_CLASS(klass); | |
879 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
880 | ||
05607921 | 881 | k->realize = igd_pt_i440fx_realize; |
595a4f07 TC |
882 | dc->desc = "IGD Passthrough Host bridge"; |
883 | } | |
884 | ||
885 | static const TypeInfo igd_passthrough_i440fx_info = { | |
886 | .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE, | |
887 | .parent = TYPE_I440FX_PCI_DEVICE, | |
888 | .instance_size = sizeof(PCII440FXState), | |
889 | .class_init = igd_passthrough_i440fx_class_init, | |
890 | }; | |
891 | ||
568f0690 DG |
892 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
893 | PCIBus *rootbus) | |
894 | { | |
04c7d8b8 CR |
895 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge); |
896 | ||
568f0690 | 897 | /* For backwards compat with old device paths */ |
04c7d8b8 CR |
898 | if (s->short_root_bus) { |
899 | return "0000"; | |
900 | } | |
901 | return "0000:00"; | |
568f0690 DG |
902 | } |
903 | ||
39848901 IM |
904 | static Property i440fx_props[] = { |
905 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, | |
9fa99d25 | 906 | pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), |
04c7d8b8 | 907 | DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), |
9fa99d25 | 908 | DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), |
39848901 IM |
909 | DEFINE_PROP_END_OF_LIST(), |
910 | }; | |
911 | ||
999e12bb AL |
912 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
913 | { | |
39bffca2 | 914 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 915 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 916 | |
568f0690 | 917 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 918 | dc->realize = i440fx_pcihost_realize; |
39bffca2 | 919 | dc->fw_name = "pci"; |
39848901 | 920 | dc->props = i440fx_props; |
bf8d4924 | 921 | /* Reason: needs to be wired up by pc_init1 */ |
e90f2a8c | 922 | dc->user_creatable = false; |
999e12bb AL |
923 | } |
924 | ||
4240abff | 925 | static const TypeInfo i440fx_pcihost_info = { |
1d0d4aa4 | 926 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
8558d942 | 927 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 928 | .instance_size = sizeof(I440FXState), |
a3560fbf | 929 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 930 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
931 | }; |
932 | ||
83f7d43a | 933 | static void i440fx_register_types(void) |
8a14daa5 | 934 | { |
39bffca2 | 935 | type_register_static(&i440fx_info); |
595a4f07 | 936 | type_register_static(&igd_passthrough_i440fx_info); |
b7c69719 | 937 | type_register_static(&piix3_pci_type_info); |
39bffca2 AL |
938 | type_register_static(&piix3_info); |
939 | type_register_static(&piix3_xen_info); | |
940 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 941 | } |
83f7d43a AF |
942 | |
943 | type_init(i440fx_register_types) |