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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a | 26 | #include "hw/i386/pc.h" |
83c9f4ca PB |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/pci/pci_host.h" | |
0d09e41a | 29 | #include "hw/isa/isa.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
1de7afc9 | 31 | #include "qemu/range.h" |
0d09e41a PB |
32 | #include "hw/xen/xen.h" |
33 | #include "hw/pci-host/pam.h" | |
1ec4ba74 | 34 | #include "sysemu/sysemu.h" |
39848901 IM |
35 | #include "hw/i386/ioapic.h" |
36 | #include "qapi/visitor.h" | |
87ecb68b | 37 | |
56594fe3 IY |
38 | /* |
39 | * I440FX chipset data sheet. | |
40 | * http://download.intel.com/design/chipsets/datashts/29054901.pdf | |
41 | */ | |
42 | ||
1d0d4aa4 IM |
43 | #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" |
44 | #define I440FX_PCI_HOST_BRIDGE(obj) \ | |
45 | OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE) | |
46 | ||
67c332fd AF |
47 | typedef struct I440FXState { |
48 | PCIHostState parent_obj; | |
39848901 IM |
49 | PcPciInfo pci_info; |
50 | uint64_t pci_hole64_size; | |
67c332fd | 51 | } I440FXState; |
502a5395 | 52 | |
ab431c28 | 53 | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
e735b55a | 54 | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
bf09551a | 55 | #define XEN_PIIX_NUM_PIRQS 128ULL |
ab431c28 | 56 | #define PIIX_PIRQC 0x60 |
e735b55a | 57 | |
1ec4ba74 LE |
58 | /* |
59 | * Reset Control Register: PCI-accessible ISA-Compatible Register at address | |
60 | * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). | |
61 | */ | |
62 | #define RCR_IOPORT 0xcf9 | |
63 | ||
fd37d881 JQ |
64 | typedef struct PIIX3State { |
65 | PCIDevice dev; | |
ab431c28 IY |
66 | |
67 | /* | |
68 | * bitmap to track pic levels. | |
69 | * The pic level is the logical OR of all the PCI irqs mapped to it | |
70 | * So one PIC level is tracked by PIIX_NUM_PIRQS bits. | |
71 | * | |
72 | * PIRQ is mapped to PIC pins, we track it by | |
73 | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with | |
74 | * pic_irq * PIIX_NUM_PIRQS + pirq | |
75 | */ | |
76 | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 | |
77 | #error "unable to encode pic state in 64bit in pic_levels." | |
78 | #endif | |
79 | uint64_t pic_levels; | |
80 | ||
bd7dce87 | 81 | qemu_irq *pic; |
e735b55a IY |
82 | |
83 | /* This member isn't used. Just for save/load compatibility */ | |
84 | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; | |
1ec4ba74 LE |
85 | |
86 | /* Reset Control Register contents */ | |
87 | uint8_t rcr; | |
88 | ||
89 | /* IO memory region for Reset Control Register (RCR_IOPORT) */ | |
90 | MemoryRegion rcr_mem; | |
7cd9eee0 | 91 | } PIIX3State; |
bd7dce87 | 92 | |
57a0f0c6 DW |
93 | #define TYPE_I440FX_PCI_DEVICE "i440FX" |
94 | #define I440FX_PCI_DEVICE(obj) \ | |
95 | OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) | |
96 | ||
0a3bacf3 | 97 | struct PCII440FXState { |
2aedfa46 HT |
98 | /*< private >*/ |
99 | PCIDevice parent_obj; | |
100 | /*< public >*/ | |
101 | ||
ae0a5466 AK |
102 | MemoryRegion *system_memory; |
103 | MemoryRegion *pci_address_space; | |
104 | MemoryRegion *ram_memory; | |
105 | MemoryRegion pci_hole; | |
106 | MemoryRegion pci_hole_64bit; | |
107 | PAMMemoryRegion pam_regions[13]; | |
108 | MemoryRegion smram_region; | |
6c009fa4 | 109 | uint8_t smm_enabled; |
0a3bacf3 JQ |
110 | }; |
111 | ||
f2c688bb IY |
112 | |
113 | #define I440FX_PAM 0x59 | |
114 | #define I440FX_PAM_SIZE 7 | |
115 | #define I440FX_SMRAM 0x72 | |
116 | ||
ab431c28 | 117 | static void piix3_set_irq(void *opaque, int pirq, int level); |
3afa9bb4 | 118 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); |
bf09551a SS |
119 | static void piix3_write_config_xen(PCIDevice *dev, |
120 | uint32_t address, uint32_t val, int len); | |
d2b59317 PB |
121 | |
122 | /* return the global irq number corresponding to a given device irq | |
123 | pin. We could also use the bus number to have a more precise | |
124 | mapping. */ | |
ab431c28 | 125 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
d2b59317 PB |
126 | { |
127 | int slot_addend; | |
128 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
ab431c28 | 129 | return (pci_intx + slot_addend) & 3; |
d2b59317 | 130 | } |
502a5395 | 131 | |
0a3bacf3 | 132 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 133 | { |
410edd92 | 134 | int i; |
2aedfa46 | 135 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 136 | |
72124c01 | 137 | memory_region_transaction_begin(); |
410edd92 IY |
138 | for (i = 0; i < 13; i++) { |
139 | pam_update(&d->pam_regions[i], i, | |
2aedfa46 | 140 | pd->config[I440FX_PAM + ((i + 1) / 2)]); |
ee0ea1d0 | 141 | } |
2aedfa46 | 142 | smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled); |
72124c01 | 143 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
144 | } |
145 | ||
f885f1ea | 146 | static void i440fx_set_smm(int val, void *arg) |
ee0ea1d0 | 147 | { |
f885f1ea | 148 | PCII440FXState *d = arg; |
2aedfa46 | 149 | PCIDevice *pd = PCI_DEVICE(d); |
f885f1ea | 150 | |
410edd92 | 151 | memory_region_transaction_begin(); |
2aedfa46 | 152 | smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM], |
410edd92 IY |
153 | &d->smram_region); |
154 | memory_region_transaction_commit(); | |
ee0ea1d0 FB |
155 | } |
156 | ||
157 | ||
0a3bacf3 | 158 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
159 | uint32_t address, uint32_t val, int len) |
160 | { | |
57a0f0c6 | 161 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 162 | |
ee0ea1d0 | 163 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 164 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
165 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
166 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 167 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 168 | } |
ee0ea1d0 FB |
169 | } |
170 | ||
0c7d19e5 | 171 | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
ee0ea1d0 | 172 | { |
0a3bacf3 | 173 | PCII440FXState *d = opaque; |
2aedfa46 | 174 | PCIDevice *pd = PCI_DEVICE(d); |
52fc1d83 | 175 | int ret, i; |
ee0ea1d0 | 176 | |
2aedfa46 | 177 | ret = pci_device_load(pd, f); |
ee0ea1d0 FB |
178 | if (ret < 0) |
179 | return ret; | |
180 | i440fx_update_memory_mappings(d); | |
6c009fa4 | 181 | qemu_get_8s(f, &d->smm_enabled); |
52fc1d83 | 182 | |
e735b55a IY |
183 | if (version_id == 2) { |
184 | for (i = 0; i < PIIX_NUM_PIRQS; i++) { | |
185 | qemu_get_be32(f); /* dummy load for compatibility */ | |
186 | } | |
187 | } | |
52fc1d83 | 188 | |
ee0ea1d0 FB |
189 | return 0; |
190 | } | |
191 | ||
e59fb374 | 192 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
193 | { |
194 | PCII440FXState *d = opaque; | |
195 | ||
196 | i440fx_update_memory_mappings(d); | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static const VMStateDescription vmstate_i440fx = { | |
201 | .name = "I440FX", | |
202 | .version_id = 3, | |
203 | .minimum_version_id = 3, | |
204 | .minimum_version_id_old = 1, | |
205 | .load_state_old = i440fx_load_old, | |
752ff2fa | 206 | .post_load = i440fx_post_load, |
0c7d19e5 | 207 | .fields = (VMStateField []) { |
2aedfa46 | 208 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
0c7d19e5 JQ |
209 | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
210 | VMSTATE_END_OF_LIST() | |
211 | } | |
212 | }; | |
213 | ||
39848901 IM |
214 | static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, |
215 | void *opaque, const char *name, | |
216 | Error **errp) | |
217 | { | |
218 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
219 | uint32_t value = s->pci_info.w32.begin; | |
220 | ||
221 | visit_type_uint32(v, &value, name, errp); | |
222 | } | |
223 | ||
224 | static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, | |
225 | void *opaque, const char *name, | |
226 | Error **errp) | |
227 | { | |
228 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
229 | uint32_t value = s->pci_info.w32.end; | |
230 | ||
231 | visit_type_uint32(v, &value, name, errp); | |
232 | } | |
233 | ||
234 | static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, | |
235 | void *opaque, const char *name, | |
236 | Error **errp) | |
237 | { | |
2028fdf3 MT |
238 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
239 | Range w64; | |
240 | ||
241 | pci_bus_get_w64_range(h->bus, &w64); | |
39848901 | 242 | |
2028fdf3 | 243 | visit_type_uint64(v, &w64.begin, name, errp); |
39848901 IM |
244 | } |
245 | ||
246 | static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, | |
247 | void *opaque, const char *name, | |
248 | Error **errp) | |
249 | { | |
2028fdf3 MT |
250 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
251 | Range w64; | |
252 | ||
253 | pci_bus_get_w64_range(h->bus, &w64); | |
39848901 | 254 | |
2028fdf3 | 255 | visit_type_uint64(v, &w64.end, name, errp); |
39848901 IM |
256 | } |
257 | ||
a3560fbf | 258 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 259 | { |
a3560fbf | 260 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
39848901 | 261 | I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj); |
502a5395 | 262 | |
a3560fbf | 263 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 264 | "pci-conf-idx", 4); |
a3560fbf | 265 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 266 | "pci-conf-data", 4); |
39848901 IM |
267 | |
268 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", | |
269 | i440fx_pcihost_get_pci_hole_start, | |
270 | NULL, NULL, NULL, NULL); | |
271 | ||
272 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", | |
273 | i440fx_pcihost_get_pci_hole_end, | |
274 | NULL, NULL, NULL, NULL); | |
275 | ||
276 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", | |
277 | i440fx_pcihost_get_pci_hole64_start, | |
278 | NULL, NULL, NULL, NULL); | |
279 | ||
280 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", | |
281 | i440fx_pcihost_get_pci_hole64_end, | |
282 | NULL, NULL, NULL, NULL); | |
283 | ||
284 | d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; | |
a3560fbf | 285 | } |
502a5395 | 286 | |
a3560fbf HT |
287 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
288 | { | |
289 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
290 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
291 | ||
292 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
293 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
294 | ||
295 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
296 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
8a14daa5 | 297 | } |
502a5395 | 298 | |
0a3bacf3 | 299 | static int i440fx_initfn(PCIDevice *dev) |
8a14daa5 | 300 | { |
57a0f0c6 | 301 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
ee0ea1d0 | 302 | |
2aedfa46 | 303 | dev->config[I440FX_SMRAM] = 0x02; |
ee0ea1d0 | 304 | |
f885f1ea | 305 | cpu_smm_register(&i440fx_set_smm, d); |
81a322d4 | 306 | return 0; |
8a14daa5 GH |
307 | } |
308 | ||
44fc8c5e IM |
309 | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, |
310 | int *piix3_devfn, | |
311 | ISABus **isa_bus, qemu_irq *pic, | |
312 | MemoryRegion *address_space_mem, | |
313 | MemoryRegion *address_space_io, | |
314 | ram_addr_t ram_size, | |
315 | hwaddr pci_hole_start, | |
316 | hwaddr pci_hole_size, | |
39848901 | 317 | ram_addr_t above_4g_mem_size, |
44fc8c5e IM |
318 | MemoryRegion *pci_address_space, |
319 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
320 | { |
321 | DeviceState *dev; | |
322 | PCIBus *b; | |
323 | PCIDevice *d; | |
8558d942 | 324 | PCIHostState *s; |
7cd9eee0 | 325 | PIIX3State *piix3; |
ae0a5466 | 326 | PCII440FXState *f; |
2725aec7 | 327 | unsigned i; |
39848901 | 328 | I440FXState *i440fx; |
1466cef3 | 329 | uint64_t pci_hole64_size; |
8a14daa5 | 330 | |
1d0d4aa4 | 331 | dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE); |
8558d942 | 332 | s = PCI_HOST_BRIDGE(dev); |
67c332fd | 333 | b = pci_bus_new(dev, NULL, pci_address_space, |
60a0e443 | 334 | address_space_io, 0, TYPE_PCI_BUS); |
8a14daa5 | 335 | s->bus = b; |
f05f6b4a | 336 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL); |
f424d5c4 | 337 | qdev_init_nofail(dev); |
8a14daa5 | 338 | |
44fc8c5e | 339 | d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE); |
57a0f0c6 | 340 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
341 | f = *pi440fx_state; |
342 | f->system_memory = address_space_mem; | |
343 | f->pci_address_space = pci_address_space; | |
344 | f->ram_memory = ram_memory; | |
39848901 IM |
345 | |
346 | i440fx = I440FX_PCI_HOST_BRIDGE(dev); | |
347 | /* Set PCI window size the way seabios has always done it. */ | |
348 | /* Power of 2 so bios can cover it with a single MTRR */ | |
349 | if (ram_size <= 0x80000000) { | |
350 | i440fx->pci_info.w32.begin = 0x80000000; | |
351 | } else if (ram_size <= 0xc0000000) { | |
352 | i440fx->pci_info.w32.begin = 0xc0000000; | |
353 | } else { | |
354 | i440fx->pci_info.w32.begin = 0xe0000000; | |
355 | } | |
356 | ||
40c5dce9 | 357 | memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, |
ae0a5466 AK |
358 | pci_hole_start, pci_hole_size); |
359 | memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); | |
39848901 | 360 | |
1466cef3 MT |
361 | pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size); |
362 | ||
39848901 | 363 | pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size, |
1466cef3 | 364 | pci_hole64_size); |
40c5dce9 | 365 | memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64", |
ae0a5466 | 366 | f->pci_address_space, |
39848901 | 367 | i440fx->pci_info.w64.begin, |
1466cef3 MT |
368 | pci_hole64_size); |
369 | if (pci_hole64_size) { | |
39848901 IM |
370 | memory_region_add_subregion(f->system_memory, |
371 | i440fx->pci_info.w64.begin, | |
ae0a5466 AK |
372 | &f->pci_hole_64bit); |
373 | } | |
40c5dce9 | 374 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 375 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
376 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
377 | &f->smram_region, 1); | |
378 | memory_region_set_enabled(&f->smram_region, false); | |
3cd2cf43 | 379 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 380 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
2725aec7 | 381 | for (i = 0; i < 12; ++i) { |
3cd2cf43 | 382 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
383 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
384 | PAM_EXPAN_SIZE); | |
2725aec7 | 385 | } |
8a14daa5 | 386 | |
bf09551a SS |
387 | /* Xen supports additional interrupt routes from the PCI devices to |
388 | * the IOAPIC: the four pins of each PCI device on the bus are also | |
389 | * connected to the IOAPIC directly. | |
390 | * These additional routes can be discovered through ACPI. */ | |
391 | if (xen_enabled()) { | |
392 | piix3 = DO_UPCAST(PIIX3State, dev, | |
393 | pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); | |
394 | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, | |
395 | piix3, XEN_PIIX_NUM_PIRQS); | |
396 | } else { | |
397 | piix3 = DO_UPCAST(PIIX3State, dev, | |
398 | pci_create_simple_multifunction(b, -1, true, "PIIX3")); | |
399 | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, | |
400 | PIIX_NUM_PIRQS); | |
3afa9bb4 | 401 | pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); |
bf09551a | 402 | } |
7cd9eee0 | 403 | piix3->pic = pic; |
d93a8a43 | 404 | *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); |
41445300 | 405 | |
7cd9eee0 | 406 | *piix3_devfn = piix3->dev.devfn; |
85a750ca | 407 | |
ec5f92ce | 408 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 409 | if (ram_size > 255) { |
ec5f92ce | 410 | ram_size = 255; |
2aedfa46 HT |
411 | } |
412 | d->config[0x57] = ram_size; | |
ec5f92ce | 413 | |
ae0a5466 AK |
414 | i440fx_update_memory_mappings(f); |
415 | ||
502a5395 PB |
416 | return b; |
417 | } | |
418 | ||
419 | /* PIIX3 PCI to ISA bridge */ | |
ab431c28 IY |
420 | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
421 | { | |
422 | qemu_set_irq(piix3->pic[pic_irq], | |
423 | !!(piix3->pic_levels & | |
09de0f46 | 424 | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
ab431c28 IY |
425 | (pic_irq * PIIX_NUM_PIRQS)))); |
426 | } | |
502a5395 | 427 | |
afe3ef1d | 428 | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
ab431c28 IY |
429 | { |
430 | int pic_irq; | |
431 | uint64_t mask; | |
432 | ||
433 | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; | |
434 | if (pic_irq >= PIIX_NUM_PIC_IRQS) { | |
435 | return; | |
436 | } | |
437 | ||
438 | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); | |
439 | piix3->pic_levels &= ~mask; | |
440 | piix3->pic_levels |= mask * !!level; | |
441 | ||
afe3ef1d | 442 | piix3_set_irq_pic(piix3, pic_irq); |
ab431c28 IY |
443 | } |
444 | ||
445 | static void piix3_set_irq(void *opaque, int pirq, int level) | |
502a5395 | 446 | { |
7cd9eee0 | 447 | PIIX3State *piix3 = opaque; |
afe3ef1d | 448 | piix3_set_irq_level(piix3, pirq, level); |
ab431c28 | 449 | } |
502a5395 | 450 | |
3afa9bb4 MT |
451 | static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) |
452 | { | |
453 | PIIX3State *piix3 = opaque; | |
454 | int irq = piix3->dev.config[PIIX_PIRQC + pin]; | |
455 | PCIINTxRoute route; | |
456 | ||
457 | if (irq < PIIX_NUM_PIC_IRQS) { | |
458 | route.mode = PCI_INTX_ENABLED; | |
459 | route.irq = irq; | |
460 | } else { | |
461 | route.mode = PCI_INTX_DISABLED; | |
462 | route.irq = -1; | |
463 | } | |
464 | return route; | |
465 | } | |
466 | ||
ab431c28 IY |
467 | /* irq routing is changed. so rebuild bitmap */ |
468 | static void piix3_update_irq_levels(PIIX3State *piix3) | |
469 | { | |
470 | int pirq; | |
471 | ||
472 | piix3->pic_levels = 0; | |
473 | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { | |
474 | piix3_set_irq_level(piix3, pirq, | |
afe3ef1d | 475 | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
ab431c28 IY |
476 | } |
477 | } | |
478 | ||
479 | static void piix3_write_config(PCIDevice *dev, | |
480 | uint32_t address, uint32_t val, int len) | |
481 | { | |
482 | pci_default_write_config(dev, address, val, len); | |
483 | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { | |
484 | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); | |
485 | int pic_irq; | |
0ae16251 JK |
486 | |
487 | pci_bus_fire_intx_routing_notifier(piix3->dev.bus); | |
ab431c28 IY |
488 | piix3_update_irq_levels(piix3); |
489 | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { | |
490 | piix3_set_irq_pic(piix3, pic_irq); | |
d2b59317 | 491 | } |
502a5395 PB |
492 | } |
493 | } | |
494 | ||
bf09551a SS |
495 | static void piix3_write_config_xen(PCIDevice *dev, |
496 | uint32_t address, uint32_t val, int len) | |
497 | { | |
498 | xen_piix_pci_write_config_client(address, val, len); | |
499 | piix3_write_config(dev, address, val, len); | |
500 | } | |
501 | ||
15a1956a | 502 | static void piix3_reset(void *opaque) |
502a5395 | 503 | { |
fd37d881 JQ |
504 | PIIX3State *d = opaque; |
505 | uint8_t *pci_conf = d->dev.config; | |
502a5395 | 506 | |
c9721215 | 507 | pci_conf[0x04] = 0x07; /* master, memory and I/O */ |
502a5395 PB |
508 | pci_conf[0x05] = 0x00; |
509 | pci_conf[0x06] = 0x00; | |
c9721215 | 510 | pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ |
502a5395 PB |
511 | pci_conf[0x4c] = 0x4d; |
512 | pci_conf[0x4e] = 0x03; | |
513 | pci_conf[0x4f] = 0x00; | |
514 | pci_conf[0x60] = 0x80; | |
477afee3 AJ |
515 | pci_conf[0x61] = 0x80; |
516 | pci_conf[0x62] = 0x80; | |
517 | pci_conf[0x63] = 0x80; | |
502a5395 PB |
518 | pci_conf[0x69] = 0x02; |
519 | pci_conf[0x70] = 0x80; | |
520 | pci_conf[0x76] = 0x0c; | |
521 | pci_conf[0x77] = 0x0c; | |
522 | pci_conf[0x78] = 0x02; | |
523 | pci_conf[0x79] = 0x00; | |
524 | pci_conf[0x80] = 0x00; | |
525 | pci_conf[0x82] = 0x00; | |
526 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
527 | pci_conf[0xa2] = 0x00; |
528 | pci_conf[0xa3] = 0x00; | |
529 | pci_conf[0xa4] = 0x00; | |
530 | pci_conf[0xa5] = 0x00; | |
531 | pci_conf[0xa6] = 0x00; | |
532 | pci_conf[0xa7] = 0x00; | |
533 | pci_conf[0xa8] = 0x0f; | |
534 | pci_conf[0xaa] = 0x00; | |
535 | pci_conf[0xab] = 0x00; | |
536 | pci_conf[0xac] = 0x00; | |
537 | pci_conf[0xae] = 0x00; | |
ab431c28 IY |
538 | |
539 | d->pic_levels = 0; | |
1ec4ba74 | 540 | d->rcr = 0; |
ab431c28 IY |
541 | } |
542 | ||
543 | static int piix3_post_load(void *opaque, int version_id) | |
544 | { | |
545 | PIIX3State *piix3 = opaque; | |
546 | piix3_update_irq_levels(piix3); | |
547 | return 0; | |
e735b55a | 548 | } |
15a1956a | 549 | |
e735b55a IY |
550 | static void piix3_pre_save(void *opaque) |
551 | { | |
552 | int i; | |
553 | PIIX3State *piix3 = opaque; | |
554 | ||
555 | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { | |
556 | piix3->pci_irq_levels_vmstate[i] = | |
557 | pci_bus_get_irq_level(piix3->dev.bus, i); | |
558 | } | |
502a5395 PB |
559 | } |
560 | ||
1ec4ba74 LE |
561 | static bool piix3_rcr_needed(void *opaque) |
562 | { | |
563 | PIIX3State *piix3 = opaque; | |
564 | ||
565 | return (piix3->rcr != 0); | |
566 | } | |
567 | ||
568 | static const VMStateDescription vmstate_piix3_rcr = { | |
569 | .name = "PIIX3/rcr", | |
570 | .version_id = 1, | |
571 | .minimum_version_id = 1, | |
572 | .fields = (VMStateField []) { | |
573 | VMSTATE_UINT8(rcr, PIIX3State), | |
574 | VMSTATE_END_OF_LIST() | |
575 | } | |
576 | }; | |
577 | ||
d1f171bd JQ |
578 | static const VMStateDescription vmstate_piix3 = { |
579 | .name = "PIIX3", | |
580 | .version_id = 3, | |
581 | .minimum_version_id = 2, | |
582 | .minimum_version_id_old = 2, | |
ab431c28 | 583 | .post_load = piix3_post_load, |
e735b55a | 584 | .pre_save = piix3_pre_save, |
1ec4ba74 | 585 | .fields = (VMStateField[]) { |
d1f171bd | 586 | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
e735b55a IY |
587 | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
588 | PIIX_NUM_PIRQS, 3), | |
d1f171bd | 589 | VMSTATE_END_OF_LIST() |
1ec4ba74 LE |
590 | }, |
591 | .subsections = (VMStateSubsection[]) { | |
592 | { | |
593 | .vmsd = &vmstate_piix3_rcr, | |
594 | .needed = piix3_rcr_needed, | |
595 | }, | |
596 | { 0 } | |
597 | } | |
598 | }; | |
599 | ||
600 | ||
601 | static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) | |
602 | { | |
603 | PIIX3State *d = opaque; | |
604 | ||
605 | if (val & 4) { | |
606 | qemu_system_reset_request(); | |
607 | return; | |
da64182c | 608 | } |
1ec4ba74 LE |
609 | d->rcr = val & 2; /* keep System Reset type only */ |
610 | } | |
611 | ||
612 | static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) | |
613 | { | |
614 | PIIX3State *d = opaque; | |
615 | ||
616 | return d->rcr; | |
617 | } | |
618 | ||
619 | static const MemoryRegionOps rcr_ops = { | |
620 | .read = rcr_read, | |
621 | .write = rcr_write, | |
622 | .endianness = DEVICE_LITTLE_ENDIAN | |
d1f171bd | 623 | }; |
1941d19c | 624 | |
fd37d881 | 625 | static int piix3_initfn(PCIDevice *dev) |
502a5395 | 626 | { |
fd37d881 | 627 | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
502a5395 | 628 | |
d93a8a43 | 629 | isa_bus_new(DEVICE(d), pci_address_space_io(dev)); |
1ec4ba74 | 630 | |
40c5dce9 PB |
631 | memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, |
632 | "piix3-reset-control", 1); | |
1ec4ba74 LE |
633 | memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, |
634 | &d->rcr_mem, 1); | |
635 | ||
a08d4367 | 636 | qemu_register_reset(piix3_reset, d); |
81a322d4 | 637 | return 0; |
502a5395 | 638 | } |
5c2b87e3 | 639 | |
40021f08 AL |
640 | static void piix3_class_init(ObjectClass *klass, void *data) |
641 | { | |
39bffca2 | 642 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
643 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
644 | ||
39bffca2 AL |
645 | dc->desc = "ISA bridge"; |
646 | dc->vmsd = &vmstate_piix3; | |
647 | dc->no_user = 1, | |
40021f08 AL |
648 | k->no_hotplug = 1; |
649 | k->init = piix3_initfn; | |
650 | k->config_write = piix3_write_config; | |
651 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
652 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
653 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 AL |
654 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
655 | } | |
656 | ||
4240abff | 657 | static const TypeInfo piix3_info = { |
39bffca2 AL |
658 | .name = "PIIX3", |
659 | .parent = TYPE_PCI_DEVICE, | |
660 | .instance_size = sizeof(PIIX3State), | |
661 | .class_init = piix3_class_init, | |
e855761c AL |
662 | }; |
663 | ||
40021f08 AL |
664 | static void piix3_xen_class_init(ObjectClass *klass, void *data) |
665 | { | |
39bffca2 | 666 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
667 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
668 | ||
39bffca2 AL |
669 | dc->desc = "ISA bridge"; |
670 | dc->vmsd = &vmstate_piix3; | |
671 | dc->no_user = 1; | |
40021f08 AL |
672 | k->no_hotplug = 1; |
673 | k->init = piix3_initfn; | |
674 | k->config_write = piix3_write_config_xen; | |
675 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
c9721215 DW |
676 | /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ |
677 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; | |
40021f08 | 678 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
e855761c AL |
679 | }; |
680 | ||
4240abff | 681 | static const TypeInfo piix3_xen_info = { |
39bffca2 AL |
682 | .name = "PIIX3-xen", |
683 | .parent = TYPE_PCI_DEVICE, | |
684 | .instance_size = sizeof(PIIX3State), | |
685 | .class_init = piix3_xen_class_init, | |
40021f08 AL |
686 | }; |
687 | ||
688 | static void i440fx_class_init(ObjectClass *klass, void *data) | |
689 | { | |
39bffca2 | 690 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
691 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
692 | ||
693 | k->no_hotplug = 1; | |
694 | k->init = i440fx_initfn; | |
695 | k->config_write = i440fx_write_config; | |
696 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
697 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
698 | k->revision = 0x02; | |
699 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
700 | dc->desc = "Host bridge"; |
701 | dc->no_user = 1; | |
702 | dc->vmsd = &vmstate_i440fx; | |
40021f08 AL |
703 | } |
704 | ||
4240abff | 705 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 706 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
707 | .parent = TYPE_PCI_DEVICE, |
708 | .instance_size = sizeof(PCII440FXState), | |
709 | .class_init = i440fx_class_init, | |
8a14daa5 GH |
710 | }; |
711 | ||
568f0690 DG |
712 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
713 | PCIBus *rootbus) | |
714 | { | |
715 | /* For backwards compat with old device paths */ | |
716 | return "0000"; | |
717 | } | |
718 | ||
39848901 IM |
719 | static Property i440fx_props[] = { |
720 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, | |
721 | pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), | |
722 | DEFINE_PROP_END_OF_LIST(), | |
723 | }; | |
724 | ||
999e12bb AL |
725 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
726 | { | |
39bffca2 | 727 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 728 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 729 | |
568f0690 | 730 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 731 | dc->realize = i440fx_pcihost_realize; |
39bffca2 AL |
732 | dc->fw_name = "pci"; |
733 | dc->no_user = 1; | |
39848901 | 734 | dc->props = i440fx_props; |
999e12bb AL |
735 | } |
736 | ||
4240abff | 737 | static const TypeInfo i440fx_pcihost_info = { |
1d0d4aa4 | 738 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
8558d942 | 739 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 740 | .instance_size = sizeof(I440FXState), |
a3560fbf | 741 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 742 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
743 | }; |
744 | ||
83f7d43a | 745 | static void i440fx_register_types(void) |
8a14daa5 | 746 | { |
39bffca2 AL |
747 | type_register_static(&i440fx_info); |
748 | type_register_static(&piix3_info); | |
749 | type_register_static(&piix3_xen_info); | |
750 | type_register_static(&i440fx_pcihost_info); | |
8a14daa5 | 751 | } |
83f7d43a AF |
752 | |
753 | type_init(i440fx_register_types) |