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Commit | Line | Data |
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74c62ba8 AJ |
1 | /* |
2 | * QEMU PowerPC E500 embedded processors pci controller emulation | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc4xx_pci.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
83c9f4ca | 17 | #include "hw/hw.h" |
3eddc1be | 18 | #include "hw/ppc/e500-ccsr.h" |
83c9f4ca PB |
19 | #include "hw/pci/pci.h" |
20 | #include "hw/pci/pci_host.h" | |
1de7afc9 | 21 | #include "qemu/bswap.h" |
0d09e41a | 22 | #include "hw/pci-host/ppce500.h" |
74c62ba8 AJ |
23 | |
24 | #ifdef DEBUG_PCI | |
001faf32 | 25 | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
74c62ba8 | 26 | #else |
001faf32 | 27 | #define pci_debug(fmt, ...) |
74c62ba8 AJ |
28 | #endif |
29 | ||
30 | #define PCIE500_CFGADDR 0x0 | |
31 | #define PCIE500_CFGDATA 0x4 | |
32 | #define PCIE500_REG_BASE 0xC00 | |
be13cc7a AG |
33 | #define PCIE500_ALL_SIZE 0x1000 |
34 | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) | |
74c62ba8 | 35 | |
a1bc20df AG |
36 | #define PCIE500_PCI_IOLEN 0x10000ULL |
37 | ||
74c62ba8 AJ |
38 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
39 | #define PPCE500_PCI_CONFIG_DATA 0x4 | |
40 | #define PPCE500_PCI_INTACK 0x8 | |
41 | ||
42 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) | |
43 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) | |
44 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) | |
45 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) | |
46 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) | |
47 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) | |
48 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) | |
49 | ||
50 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) | |
51 | ||
52 | #define PCI_POTAR 0x0 | |
53 | #define PCI_POTEAR 0x4 | |
54 | #define PCI_POWBAR 0x8 | |
55 | #define PCI_POWAR 0x10 | |
56 | ||
57 | #define PCI_PITAR 0x0 | |
58 | #define PCI_PIWBAR 0x8 | |
59 | #define PCI_PIWBEAR 0xC | |
60 | #define PCI_PIWAR 0x10 | |
61 | ||
62 | #define PPCE500_PCI_NR_POBS 5 | |
63 | #define PPCE500_PCI_NR_PIBS 3 | |
64 | ||
65 | struct pci_outbound { | |
66 | uint32_t potar; | |
67 | uint32_t potear; | |
68 | uint32_t powbar; | |
69 | uint32_t powar; | |
70 | }; | |
71 | ||
72 | struct pci_inbound { | |
73 | uint32_t pitar; | |
74 | uint32_t piwbar; | |
75 | uint32_t piwbear; | |
76 | uint32_t piwar; | |
77 | }; | |
78 | ||
9c1a61f0 AF |
79 | #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" |
80 | ||
81 | #define PPC_E500_PCI_HOST_BRIDGE(obj) \ | |
82 | OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) | |
83 | ||
74c62ba8 | 84 | struct PPCE500PCIState { |
67c332fd | 85 | PCIHostState parent_obj; |
9c1a61f0 | 86 | |
74c62ba8 AJ |
87 | struct pci_outbound pob[PPCE500_PCI_NR_POBS]; |
88 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; | |
89 | uint32_t gasket_time; | |
be13cc7a | 90 | qemu_irq irq[4]; |
eafb325f | 91 | uint32_t first_slot; |
be13cc7a | 92 | /* mmio maps */ |
cb4e15c7 | 93 | MemoryRegion container; |
cd5cba79 | 94 | MemoryRegion iomem; |
a1bc20df | 95 | MemoryRegion pio; |
74c62ba8 AJ |
96 | }; |
97 | ||
3eddc1be BB |
98 | #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" |
99 | #define PPC_E500_PCI_BRIDGE(obj) \ | |
100 | OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) | |
101 | ||
102 | struct PPCE500PCIBridgeState { | |
103 | /*< private >*/ | |
104 | PCIDevice parent; | |
105 | /*< public >*/ | |
106 | ||
107 | MemoryRegion bar0; | |
108 | }; | |
109 | ||
110 | typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; | |
74c62ba8 AJ |
111 | typedef struct PPCE500PCIState PPCE500PCIState; |
112 | ||
a8170e5e | 113 | static uint64_t pci_reg_read4(void *opaque, hwaddr addr, |
cd5cba79 | 114 | unsigned size) |
74c62ba8 AJ |
115 | { |
116 | PPCE500PCIState *pci = opaque; | |
117 | unsigned long win; | |
118 | uint32_t value = 0; | |
eeae2e7b | 119 | int idx; |
74c62ba8 AJ |
120 | |
121 | win = addr & 0xfe0; | |
122 | ||
123 | switch (win) { | |
124 | case PPCE500_PCI_OW1: | |
125 | case PPCE500_PCI_OW2: | |
126 | case PPCE500_PCI_OW3: | |
127 | case PPCE500_PCI_OW4: | |
eeae2e7b | 128 | idx = (addr >> 5) & 0x7; |
74c62ba8 | 129 | switch (addr & 0xC) { |
6875dc8e | 130 | case PCI_POTAR: |
eeae2e7b | 131 | value = pci->pob[idx].potar; |
6875dc8e LY |
132 | break; |
133 | case PCI_POTEAR: | |
eeae2e7b | 134 | value = pci->pob[idx].potear; |
6875dc8e LY |
135 | break; |
136 | case PCI_POWBAR: | |
eeae2e7b | 137 | value = pci->pob[idx].powbar; |
6875dc8e LY |
138 | break; |
139 | case PCI_POWAR: | |
eeae2e7b | 140 | value = pci->pob[idx].powar; |
6875dc8e LY |
141 | break; |
142 | default: | |
143 | break; | |
74c62ba8 AJ |
144 | } |
145 | break; | |
146 | ||
147 | case PPCE500_PCI_IW3: | |
148 | case PPCE500_PCI_IW2: | |
149 | case PPCE500_PCI_IW1: | |
eeae2e7b | 150 | idx = ((addr >> 5) & 0x3) - 1; |
74c62ba8 | 151 | switch (addr & 0xC) { |
6875dc8e | 152 | case PCI_PITAR: |
eeae2e7b | 153 | value = pci->pib[idx].pitar; |
6875dc8e LY |
154 | break; |
155 | case PCI_PIWBAR: | |
eeae2e7b | 156 | value = pci->pib[idx].piwbar; |
6875dc8e LY |
157 | break; |
158 | case PCI_PIWBEAR: | |
eeae2e7b | 159 | value = pci->pib[idx].piwbear; |
6875dc8e LY |
160 | break; |
161 | case PCI_PIWAR: | |
eeae2e7b | 162 | value = pci->pib[idx].piwar; |
6875dc8e LY |
163 | break; |
164 | default: | |
165 | break; | |
74c62ba8 AJ |
166 | }; |
167 | break; | |
168 | ||
169 | case PPCE500_PCI_GASKET_TIMR: | |
170 | value = pci->gasket_time; | |
171 | break; | |
172 | ||
173 | default: | |
174 | break; | |
175 | } | |
176 | ||
c0a2a096 BS |
177 | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
178 | win, addr, value); | |
74c62ba8 AJ |
179 | return value; |
180 | } | |
181 | ||
a8170e5e | 182 | static void pci_reg_write4(void *opaque, hwaddr addr, |
cd5cba79 | 183 | uint64_t value, unsigned size) |
74c62ba8 AJ |
184 | { |
185 | PPCE500PCIState *pci = opaque; | |
186 | unsigned long win; | |
eeae2e7b | 187 | int idx; |
74c62ba8 AJ |
188 | |
189 | win = addr & 0xfe0; | |
190 | ||
c0a2a096 | 191 | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
cd5cba79 | 192 | __func__, (unsigned)value, win, addr); |
74c62ba8 AJ |
193 | |
194 | switch (win) { | |
195 | case PPCE500_PCI_OW1: | |
196 | case PPCE500_PCI_OW2: | |
197 | case PPCE500_PCI_OW3: | |
198 | case PPCE500_PCI_OW4: | |
eeae2e7b | 199 | idx = (addr >> 5) & 0x7; |
74c62ba8 | 200 | switch (addr & 0xC) { |
6875dc8e | 201 | case PCI_POTAR: |
eeae2e7b | 202 | pci->pob[idx].potar = value; |
6875dc8e LY |
203 | break; |
204 | case PCI_POTEAR: | |
eeae2e7b | 205 | pci->pob[idx].potear = value; |
6875dc8e LY |
206 | break; |
207 | case PCI_POWBAR: | |
eeae2e7b | 208 | pci->pob[idx].powbar = value; |
6875dc8e LY |
209 | break; |
210 | case PCI_POWAR: | |
eeae2e7b | 211 | pci->pob[idx].powar = value; |
6875dc8e LY |
212 | break; |
213 | default: | |
214 | break; | |
74c62ba8 AJ |
215 | }; |
216 | break; | |
217 | ||
218 | case PPCE500_PCI_IW3: | |
219 | case PPCE500_PCI_IW2: | |
220 | case PPCE500_PCI_IW1: | |
eeae2e7b | 221 | idx = ((addr >> 5) & 0x3) - 1; |
74c62ba8 | 222 | switch (addr & 0xC) { |
6875dc8e | 223 | case PCI_PITAR: |
eeae2e7b | 224 | pci->pib[idx].pitar = value; |
6875dc8e LY |
225 | break; |
226 | case PCI_PIWBAR: | |
eeae2e7b | 227 | pci->pib[idx].piwbar = value; |
6875dc8e LY |
228 | break; |
229 | case PCI_PIWBEAR: | |
eeae2e7b | 230 | pci->pib[idx].piwbear = value; |
6875dc8e LY |
231 | break; |
232 | case PCI_PIWAR: | |
eeae2e7b | 233 | pci->pib[idx].piwar = value; |
6875dc8e LY |
234 | break; |
235 | default: | |
236 | break; | |
74c62ba8 AJ |
237 | }; |
238 | break; | |
239 | ||
240 | case PPCE500_PCI_GASKET_TIMR: | |
241 | pci->gasket_time = value; | |
242 | break; | |
243 | ||
244 | default: | |
245 | break; | |
246 | }; | |
247 | } | |
248 | ||
cd5cba79 AK |
249 | static const MemoryRegionOps e500_pci_reg_ops = { |
250 | .read = pci_reg_read4, | |
251 | .write = pci_reg_write4, | |
252 | .endianness = DEVICE_BIG_ENDIAN, | |
74c62ba8 AJ |
253 | }; |
254 | ||
255 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) | |
256 | { | |
05f57d9d AG |
257 | int devno = pci_dev->devfn >> 3; |
258 | int ret; | |
74c62ba8 | 259 | |
9e2c1298 | 260 | ret = ppce500_pci_map_irq_slot(devno, irq_num); |
74c62ba8 AJ |
261 | |
262 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, | |
263 | pci_dev->devfn, irq_num, ret, devno); | |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
5d4e84c8 | 268 | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
74c62ba8 | 269 | { |
5d4e84c8 JQ |
270 | qemu_irq *pic = opaque; |
271 | ||
74c62ba8 AJ |
272 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level); |
273 | ||
274 | qemu_set_irq(pic[irq_num], level); | |
275 | } | |
276 | ||
e0433ecc JQ |
277 | static const VMStateDescription vmstate_pci_outbound = { |
278 | .name = "pci_outbound", | |
279 | .version_id = 0, | |
280 | .minimum_version_id = 0, | |
3aff6c2f | 281 | .fields = (VMStateField[]) { |
e0433ecc JQ |
282 | VMSTATE_UINT32(potar, struct pci_outbound), |
283 | VMSTATE_UINT32(potear, struct pci_outbound), | |
284 | VMSTATE_UINT32(powbar, struct pci_outbound), | |
285 | VMSTATE_UINT32(powar, struct pci_outbound), | |
286 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 287 | } |
e0433ecc | 288 | }; |
74c62ba8 | 289 | |
e0433ecc JQ |
290 | static const VMStateDescription vmstate_pci_inbound = { |
291 | .name = "pci_inbound", | |
292 | .version_id = 0, | |
293 | .minimum_version_id = 0, | |
3aff6c2f | 294 | .fields = (VMStateField[]) { |
e0433ecc JQ |
295 | VMSTATE_UINT32(pitar, struct pci_inbound), |
296 | VMSTATE_UINT32(piwbar, struct pci_inbound), | |
297 | VMSTATE_UINT32(piwbear, struct pci_inbound), | |
298 | VMSTATE_UINT32(piwar, struct pci_inbound), | |
299 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 300 | } |
e0433ecc | 301 | }; |
74c62ba8 | 302 | |
e0433ecc JQ |
303 | static const VMStateDescription vmstate_ppce500_pci = { |
304 | .name = "ppce500_pci", | |
305 | .version_id = 1, | |
306 | .minimum_version_id = 1, | |
3aff6c2f | 307 | .fields = (VMStateField[]) { |
e0433ecc JQ |
308 | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, |
309 | vmstate_pci_outbound, struct pci_outbound), | |
310 | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, | |
311 | vmstate_pci_outbound, struct pci_inbound), | |
312 | VMSTATE_UINT32(gasket_time, PPCE500PCIState), | |
313 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 314 | } |
e0433ecc | 315 | }; |
74c62ba8 | 316 | |
022c62cb | 317 | #include "exec/address-spaces.h" |
1e39101c | 318 | |
3eddc1be BB |
319 | static int e500_pcihost_bridge_initfn(PCIDevice *d) |
320 | { | |
321 | PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); | |
322 | PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), | |
323 | "/e500-ccsr")); | |
324 | ||
99750506 AG |
325 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
326 | d->config[PCI_HEADER_TYPE] = | |
327 | (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | | |
328 | PCI_HEADER_TYPE_BRIDGE; | |
329 | ||
40c5dce9 | 330 | memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, |
3eddc1be BB |
331 | 0, int128_get64(ccsr->ccsr_space.size)); |
332 | pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); | |
99750506 | 333 | |
3eddc1be BB |
334 | return 0; |
335 | } | |
336 | ||
be13cc7a AG |
337 | static int e500_pcihost_initfn(SysBusDevice *dev) |
338 | { | |
339 | PCIHostState *h; | |
340 | PPCE500PCIState *s; | |
341 | PCIBus *b; | |
342 | int i; | |
aee97b84 | 343 | MemoryRegion *address_space_mem = get_system_memory(); |
be13cc7a | 344 | |
8558d942 | 345 | h = PCI_HOST_BRIDGE(dev); |
9c1a61f0 | 346 | s = PPC_E500_PCI_HOST_BRIDGE(dev); |
be13cc7a AG |
347 | |
348 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
349 | sysbus_init_irq(dev, &s->irq[i]); | |
350 | } | |
351 | ||
40c5dce9 | 352 | memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); |
a1bc20df | 353 | |
9c1a61f0 | 354 | b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, |
aee97b84 | 355 | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
60a0e443 | 356 | &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); |
9c1a61f0 | 357 | h->bus = b; |
be13cc7a AG |
358 | |
359 | pci_create_simple(b, 0, "e500-host-bridge"); | |
360 | ||
40c5dce9 PB |
361 | memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); |
362 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, | |
d0ed8076 | 363 | "pci-conf-idx", 4); |
40c5dce9 | 364 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, |
d0ed8076 | 365 | "pci-conf-data", 4); |
40c5dce9 | 366 | memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, |
cd5cba79 | 367 | "pci.reg", PCIE500_REG_SIZE); |
cb4e15c7 BC |
368 | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
369 | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); | |
370 | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); | |
371 | sysbus_init_mmio(dev, &s->container); | |
a1bc20df | 372 | sysbus_init_mmio(dev, &s->pio); |
be13cc7a AG |
373 | |
374 | return 0; | |
375 | } | |
376 | ||
40021f08 AL |
377 | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
378 | { | |
39bffca2 | 379 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
380 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
381 | ||
3eddc1be | 382 | k->init = e500_pcihost_bridge_initfn; |
40021f08 AL |
383 | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
384 | k->device_id = PCI_DEVICE_ID_MPC8533E; | |
385 | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; | |
39bffca2 | 386 | dc->desc = "Host bridge"; |
08c58f92 MA |
387 | /* |
388 | * PCI-facing part of the host bridge, not usable without the | |
389 | * host-facing part, which can't be device_add'ed, yet. | |
390 | */ | |
391 | dc->cannot_instantiate_with_device_add_yet = true; | |
40021f08 AL |
392 | } |
393 | ||
4240abff | 394 | static const TypeInfo e500_host_bridge_info = { |
39bffca2 AL |
395 | .name = "e500-host-bridge", |
396 | .parent = TYPE_PCI_DEVICE, | |
3eddc1be | 397 | .instance_size = sizeof(PPCE500PCIBridgeState), |
39bffca2 | 398 | .class_init = e500_host_bridge_class_init, |
be13cc7a AG |
399 | }; |
400 | ||
eafb325f AG |
401 | static Property pcihost_properties[] = { |
402 | DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), | |
403 | DEFINE_PROP_END_OF_LIST(), | |
404 | }; | |
405 | ||
999e12bb AL |
406 | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
407 | { | |
39bffca2 | 408 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
409 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
410 | ||
411 | k->init = e500_pcihost_initfn; | |
125ee0ed | 412 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
eafb325f | 413 | dc->props = pcihost_properties; |
39bffca2 | 414 | dc->vmsd = &vmstate_ppce500_pci; |
999e12bb AL |
415 | } |
416 | ||
4240abff | 417 | static const TypeInfo e500_pcihost_info = { |
9c1a61f0 | 418 | .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, |
8558d942 | 419 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
420 | .instance_size = sizeof(PPCE500PCIState), |
421 | .class_init = e500_pcihost_class_init, | |
be13cc7a AG |
422 | }; |
423 | ||
83f7d43a | 424 | static void e500_pci_register_types(void) |
74c62ba8 | 425 | { |
39bffca2 AL |
426 | type_register_static(&e500_pcihost_info); |
427 | type_register_static(&e500_host_bridge_info); | |
74c62ba8 | 428 | } |
83f7d43a AF |
429 | |
430 | type_init(e500_pci_register_types) |