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502a5395 PB |
1 | /* |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
98aca3c8 | 5 | * Copyright (c) 2011-2013 Andreas Färber |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
0d75590d | 26 | #include "qemu/osdep.h" |
a8d25326 | 27 | #include "qemu-common.h" |
ab3dd749 | 28 | #include "qemu/units.h" |
da34e65c | 29 | #include "qapi/error.h" |
83c9f4ca PB |
30 | #include "hw/hw.h" |
31 | #include "hw/pci/pci.h" | |
32 | #include "hw/pci/pci_bus.h" | |
33 | #include "hw/pci/pci_host.h" | |
0d09e41a | 34 | #include "hw/i386/pc.h" |
d0b25425 | 35 | #include "hw/loader.h" |
f40b83a4 | 36 | #include "hw/or-irq.h" |
022c62cb | 37 | #include "exec/address-spaces.h" |
d0b25425 | 38 | #include "elf.h" |
502a5395 | 39 | |
98aca3c8 | 40 | #define TYPE_RAVEN_PCI_DEVICE "raven" |
03a6b667 AF |
41 | #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" |
42 | ||
98aca3c8 AF |
43 | #define RAVEN_PCI_DEVICE(obj) \ |
44 | OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE) | |
45 | ||
46 | typedef struct RavenPCIState { | |
47 | PCIDevice dev; | |
d0b25425 HP |
48 | |
49 | uint32_t elf_machine; | |
50 | char *bios_name; | |
51 | MemoryRegion bios; | |
98aca3c8 AF |
52 | } RavenPCIState; |
53 | ||
03a6b667 AF |
54 | #define RAVEN_PCI_HOST_BRIDGE(obj) \ |
55 | OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) | |
56 | ||
8ca8c7bc | 57 | typedef struct PRePPCIState { |
67c332fd | 58 | PCIHostState parent_obj; |
03a6b667 | 59 | |
f40b83a4 | 60 | qemu_or_irq *or_irq; |
55a22902 | 61 | qemu_irq pci_irqs[PCI_NUM_PINS]; |
98aca3c8 | 62 | PCIBus pci_bus; |
9a183916 | 63 | AddressSpace pci_io_as; |
1ae1dc5b | 64 | MemoryRegion pci_io; |
9a183916 | 65 | MemoryRegion pci_io_non_contiguous; |
1fe9e262 | 66 | MemoryRegion pci_memory; |
49a4e212 | 67 | MemoryRegion pci_intack; |
d16644ec HP |
68 | MemoryRegion bm; |
69 | MemoryRegion bm_ram_alias; | |
70 | MemoryRegion bm_pci_memory_alias; | |
71 | AddressSpace bm_as; | |
98aca3c8 | 72 | RavenPCIState pci_dev; |
9a183916 HP |
73 | |
74 | int contiguous_map; | |
f40b83a4 | 75 | bool is_legacy_prep; |
8ca8c7bc | 76 | } PREPPCIState; |
502a5395 | 77 | |
ab3dd749 | 78 | #define BIOS_SIZE (1 * MiB) |
d0b25425 | 79 | |
f205da68 | 80 | static inline uint32_t raven_pci_io_config(hwaddr addr) |
502a5395 PB |
81 | { |
82 | int i; | |
83 | ||
03a6b667 AF |
84 | for (i = 0; i < 11; i++) { |
85 | if ((addr & (1 << (11 + i))) != 0) { | |
502a5395 | 86 | break; |
03a6b667 | 87 | } |
502a5395 PB |
88 | } |
89 | return (addr & 0x7ff) | (i << 11); | |
90 | } | |
91 | ||
f205da68 HP |
92 | static void raven_pci_io_write(void *opaque, hwaddr addr, |
93 | uint64_t val, unsigned int size) | |
502a5395 PB |
94 | { |
95 | PREPPCIState *s = opaque; | |
67c332fd | 96 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
f205da68 | 97 | pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); |
502a5395 PB |
98 | } |
99 | ||
f205da68 HP |
100 | static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, |
101 | unsigned int size) | |
502a5395 PB |
102 | { |
103 | PREPPCIState *s = opaque; | |
67c332fd | 104 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
f205da68 | 105 | return pci_data_read(phb->bus, raven_pci_io_config(addr), size); |
502a5395 PB |
106 | } |
107 | ||
f205da68 HP |
108 | static const MemoryRegionOps raven_pci_io_ops = { |
109 | .read = raven_pci_io_read, | |
110 | .write = raven_pci_io_write, | |
9c95f183 | 111 | .endianness = DEVICE_LITTLE_ENDIAN, |
502a5395 PB |
112 | }; |
113 | ||
f205da68 HP |
114 | static uint64_t raven_intack_read(void *opaque, hwaddr addr, |
115 | unsigned int size) | |
6c84ce0d HP |
116 | { |
117 | return pic_read_irq(isa_pic); | |
118 | } | |
119 | ||
f205da68 HP |
120 | static const MemoryRegionOps raven_intack_ops = { |
121 | .read = raven_intack_read, | |
6c84ce0d HP |
122 | .valid = { |
123 | .max_access_size = 1, | |
124 | }, | |
125 | }; | |
126 | ||
9a183916 HP |
127 | static inline hwaddr raven_io_address(PREPPCIState *s, |
128 | hwaddr addr) | |
129 | { | |
130 | if (s->contiguous_map == 0) { | |
131 | /* 64 KB contiguous space for IOs */ | |
132 | addr &= 0xFFFF; | |
133 | } else { | |
134 | /* 8 MB non-contiguous space for IOs */ | |
135 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
136 | } | |
137 | ||
138 | /* FIXME: handle endianness switch */ | |
139 | ||
140 | return addr; | |
141 | } | |
142 | ||
143 | static uint64_t raven_io_read(void *opaque, hwaddr addr, | |
144 | unsigned int size) | |
145 | { | |
146 | PREPPCIState *s = opaque; | |
147 | uint8_t buf[4]; | |
148 | ||
149 | addr = raven_io_address(s, addr); | |
5c9eb028 PM |
150 | address_space_read(&s->pci_io_as, addr + 0x80000000, |
151 | MEMTXATTRS_UNSPECIFIED, buf, size); | |
9a183916 HP |
152 | |
153 | if (size == 1) { | |
154 | return buf[0]; | |
155 | } else if (size == 2) { | |
7dc176bc | 156 | return lduw_le_p(buf); |
9a183916 | 157 | } else if (size == 4) { |
7dc176bc | 158 | return ldl_le_p(buf); |
9a183916 HP |
159 | } else { |
160 | g_assert_not_reached(); | |
161 | } | |
162 | } | |
163 | ||
164 | static void raven_io_write(void *opaque, hwaddr addr, | |
165 | uint64_t val, unsigned int size) | |
166 | { | |
167 | PREPPCIState *s = opaque; | |
168 | uint8_t buf[4]; | |
169 | ||
170 | addr = raven_io_address(s, addr); | |
171 | ||
172 | if (size == 1) { | |
173 | buf[0] = val; | |
174 | } else if (size == 2) { | |
7dc176bc | 175 | stw_le_p(buf, val); |
9a183916 | 176 | } else if (size == 4) { |
7dc176bc | 177 | stl_le_p(buf, val); |
9a183916 HP |
178 | } else { |
179 | g_assert_not_reached(); | |
180 | } | |
181 | ||
5c9eb028 PM |
182 | address_space_write(&s->pci_io_as, addr + 0x80000000, |
183 | MEMTXATTRS_UNSPECIFIED, buf, size); | |
9a183916 HP |
184 | } |
185 | ||
186 | static const MemoryRegionOps raven_io_ops = { | |
187 | .read = raven_io_read, | |
188 | .write = raven_io_write, | |
189 | .endianness = DEVICE_LITTLE_ENDIAN, | |
190 | .impl.max_access_size = 4, | |
191 | .valid.unaligned = true, | |
192 | }; | |
193 | ||
f205da68 | 194 | static int raven_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 195 | { |
80b3ada7 | 196 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
d2b59317 PB |
197 | } |
198 | ||
f205da68 | 199 | static void raven_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 200 | { |
55a22902 | 201 | PREPPCIState *s = opaque; |
5d4e84c8 | 202 | |
55a22902 | 203 | qemu_set_irq(s->pci_irqs[irq_num], level); |
502a5395 PB |
204 | } |
205 | ||
d16644ec HP |
206 | static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, |
207 | int devfn) | |
208 | { | |
209 | PREPPCIState *s = opaque; | |
210 | ||
211 | return &s->bm_as; | |
212 | } | |
213 | ||
9a183916 HP |
214 | static void raven_change_gpio(void *opaque, int n, int level) |
215 | { | |
216 | PREPPCIState *s = opaque; | |
217 | ||
218 | s->contiguous_map = level; | |
219 | } | |
220 | ||
8d5ce2e5 | 221 | static void raven_pcihost_realizefn(DeviceState *d, Error **errp) |
502a5395 | 222 | { |
8d5ce2e5 | 223 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
8558d942 | 224 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
03a6b667 | 225 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); |
8ca8c7bc | 226 | MemoryRegion *address_space_mem = get_system_memory(); |
8ca8c7bc AF |
227 | int i; |
228 | ||
f40b83a4 MCA |
229 | if (s->is_legacy_prep) { |
230 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
231 | sysbus_init_irq(dev, &s->pci_irqs[i]); | |
232 | } | |
233 | } else { | |
234 | /* According to PReP specification section 6.1.6 "System Interrupt | |
235 | * Assignments", all PCI interrupts are routed via IRQ 15 */ | |
236 | s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); | |
237 | object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines", | |
238 | &error_fatal); | |
239 | object_property_set_bool(OBJECT(s->or_irq), true, "realized", | |
240 | &error_fatal); | |
241 | sysbus_init_irq(dev, &s->or_irq->out_irq); | |
242 | ||
243 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
244 | s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); | |
245 | } | |
8ca8c7bc | 246 | } |
502a5395 | 247 | |
9a183916 HP |
248 | qdev_init_gpio_in(d, raven_change_gpio, 1); |
249 | ||
55a22902 | 250 | pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS); |
502a5395 | 251 | |
2403837e HP |
252 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, |
253 | "pci-conf-idx", 4); | |
1ae1dc5b | 254 | memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); |
d0ed8076 | 255 | |
2403837e HP |
256 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, |
257 | "pci-conf-data", 4); | |
1ae1dc5b | 258 | memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); |
502a5395 | 259 | |
f205da68 HP |
260 | memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, |
261 | "pciio", 0x00400000); | |
8ca8c7bc | 262 | memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); |
502a5395 | 263 | |
f205da68 | 264 | memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, |
49a4e212 HP |
265 | "pci-intack", 1); |
266 | memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); | |
55526054 | 267 | |
98aca3c8 | 268 | /* TODO Remove once realize propagates to child devices. */ |
685f9a34 | 269 | object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp); |
8d5ce2e5 | 270 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); |
98aca3c8 AF |
271 | } |
272 | ||
273 | static void raven_pcihost_initfn(Object *obj) | |
274 | { | |
275 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
276 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); | |
277 | MemoryRegion *address_space_mem = get_system_memory(); | |
98aca3c8 AF |
278 | DeviceState *pci_dev; |
279 | ||
1ae1dc5b | 280 | memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); |
9a183916 HP |
281 | memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, |
282 | "pci-io-non-contiguous", 0x00800000); | |
97db0466 | 283 | memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); |
1ae1dc5b | 284 | address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); |
9a183916 HP |
285 | |
286 | /* CPU address space */ | |
1ae1dc5b | 287 | memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); |
9a183916 HP |
288 | memory_region_add_subregion_overlap(address_space_mem, 0x80000000, |
289 | &s->pci_io_non_contiguous, 1); | |
1fe9e262 | 290 | memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); |
1115ff6d DG |
291 | pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, |
292 | &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); | |
1ae1dc5b | 293 | |
d16644ec HP |
294 | /* Bus master address space */ |
295 | memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX); | |
296 | memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", | |
297 | &s->pci_memory, 0, | |
298 | memory_region_size(&s->pci_memory)); | |
299 | memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", | |
300 | get_system_memory(), 0, 0x80000000); | |
301 | memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); | |
302 | memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); | |
303 | address_space_init(&s->bm_as, &s->bm, "raven-bm"); | |
304 | pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); | |
305 | ||
98aca3c8 AF |
306 | h->bus = &s->pci_bus; |
307 | ||
213f0c4f | 308 | object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); |
98aca3c8 AF |
309 | pci_dev = DEVICE(&s->pci_dev); |
310 | qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus)); | |
311 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr", | |
312 | NULL); | |
313 | qdev_prop_set_bit(pci_dev, "multifunction", false); | |
55526054 AF |
314 | } |
315 | ||
9af21dbe | 316 | static void raven_realize(PCIDevice *d, Error **errp) |
55526054 | 317 | { |
d0b25425 HP |
318 | RavenPCIState *s = RAVEN_PCI_DEVICE(d); |
319 | char *filename; | |
320 | int bios_size = -1; | |
321 | ||
502a5395 PB |
322 | d->config[0x0C] = 0x08; // cache_line_size |
323 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 PB |
324 | d->config[0x34] = 0x00; // capabilities_pointer |
325 | ||
1cfe48c1 | 326 | memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE, |
f8ed85ac | 327 | &error_fatal); |
d0b25425 HP |
328 | memory_region_set_readonly(&s->bios, true); |
329 | memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), | |
330 | &s->bios); | |
d0b25425 HP |
331 | if (s->bios_name) { |
332 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); | |
333 | if (filename) { | |
334 | if (s->elf_machine != EM_NONE) { | |
4366e1db | 335 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, |
7ef295ea | 336 | NULL, NULL, 1, s->elf_machine, 0, 0); |
d0b25425 HP |
337 | } |
338 | if (bios_size < 0) { | |
339 | bios_size = get_image_size(filename); | |
340 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { | |
341 | hwaddr bios_addr; | |
342 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
343 | bios_addr = (uint32_t)(-BIOS_SIZE); | |
344 | bios_size = load_image_targphys(filename, bios_addr, | |
345 | bios_size); | |
346 | } | |
347 | } | |
348 | } | |
fb38ebfb | 349 | g_free(filename); |
d0b25425 | 350 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
fb38ebfb TH |
351 | memory_region_del_subregion(get_system_memory(), &s->bios); |
352 | error_setg(errp, "Could not load bios image '%s'", s->bios_name); | |
353 | return; | |
d0b25425 | 354 | } |
d0b25425 | 355 | } |
fb38ebfb TH |
356 | |
357 | vmstate_register_ram_global(&s->bios); | |
502a5395 | 358 | } |
55526054 AF |
359 | |
360 | static const VMStateDescription vmstate_raven = { | |
361 | .name = "raven", | |
362 | .version_id = 0, | |
363 | .minimum_version_id = 0, | |
364 | .fields = (VMStateField[]) { | |
365 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), | |
366 | VMSTATE_END_OF_LIST() | |
367 | }, | |
368 | }; | |
369 | ||
40021f08 AL |
370 | static void raven_class_init(ObjectClass *klass, void *data) |
371 | { | |
372 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 373 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 374 | |
9af21dbe | 375 | k->realize = raven_realize; |
40021f08 AL |
376 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; |
377 | k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; | |
378 | k->revision = 0x00; | |
379 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
380 | dc->desc = "PReP Host Bridge - Motorola Raven"; |
381 | dc->vmsd = &vmstate_raven; | |
08c58f92 | 382 | /* |
9280eb34 MA |
383 | * Reason: PCI-facing part of the host bridge, not usable without |
384 | * the host-facing part, which can't be device_add'ed, yet. | |
08c58f92 | 385 | */ |
e90f2a8c | 386 | dc->user_creatable = false; |
40021f08 AL |
387 | } |
388 | ||
4240abff | 389 | static const TypeInfo raven_info = { |
98aca3c8 | 390 | .name = TYPE_RAVEN_PCI_DEVICE, |
39bffca2 AL |
391 | .parent = TYPE_PCI_DEVICE, |
392 | .instance_size = sizeof(RavenPCIState), | |
40021f08 | 393 | .class_init = raven_class_init, |
fd3b02c8 EH |
394 | .interfaces = (InterfaceInfo[]) { |
395 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
396 | { }, | |
397 | }, | |
55526054 AF |
398 | }; |
399 | ||
d0b25425 HP |
400 | static Property raven_pcihost_properties[] = { |
401 | DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, | |
402 | EM_NONE), | |
403 | DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), | |
f40b83a4 MCA |
404 | /* Temporary workaround until legacy prep machine is removed */ |
405 | DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, | |
406 | false), | |
d0b25425 HP |
407 | DEFINE_PROP_END_OF_LIST() |
408 | }; | |
409 | ||
999e12bb AL |
410 | static void raven_pcihost_class_init(ObjectClass *klass, void *data) |
411 | { | |
39bffca2 | 412 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 413 | |
125ee0ed | 414 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
8d5ce2e5 | 415 | dc->realize = raven_pcihost_realizefn; |
d0b25425 | 416 | dc->props = raven_pcihost_properties; |
39bffca2 | 417 | dc->fw_name = "pci"; |
999e12bb AL |
418 | } |
419 | ||
4240abff | 420 | static const TypeInfo raven_pcihost_info = { |
03a6b667 | 421 | .name = TYPE_RAVEN_PCI_HOST_BRIDGE, |
8558d942 | 422 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 423 | .instance_size = sizeof(PREPPCIState), |
98aca3c8 | 424 | .instance_init = raven_pcihost_initfn, |
999e12bb | 425 | .class_init = raven_pcihost_class_init, |
8ca8c7bc AF |
426 | }; |
427 | ||
83f7d43a | 428 | static void raven_register_types(void) |
55526054 | 429 | { |
39bffca2 AL |
430 | type_register_static(&raven_pcihost_info); |
431 | type_register_static(&raven_info); | |
55526054 AF |
432 | } |
433 | ||
83f7d43a | 434 | type_init(raven_register_types) |