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502a5395 PB |
1 | /* |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
98aca3c8 | 5 | * Copyright (c) 2011-2013 Andreas Färber |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/pci/pci.h" | |
28 | #include "hw/pci/pci_bus.h" | |
29 | #include "hw/pci/pci_host.h" | |
0d09e41a | 30 | #include "hw/i386/pc.h" |
d0b25425 | 31 | #include "hw/loader.h" |
022c62cb | 32 | #include "exec/address-spaces.h" |
d0b25425 | 33 | #include "elf.h" |
502a5395 | 34 | |
98aca3c8 | 35 | #define TYPE_RAVEN_PCI_DEVICE "raven" |
03a6b667 AF |
36 | #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" |
37 | ||
98aca3c8 AF |
38 | #define RAVEN_PCI_DEVICE(obj) \ |
39 | OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE) | |
40 | ||
41 | typedef struct RavenPCIState { | |
42 | PCIDevice dev; | |
d0b25425 HP |
43 | |
44 | uint32_t elf_machine; | |
45 | char *bios_name; | |
46 | MemoryRegion bios; | |
98aca3c8 AF |
47 | } RavenPCIState; |
48 | ||
03a6b667 AF |
49 | #define RAVEN_PCI_HOST_BRIDGE(obj) \ |
50 | OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) | |
51 | ||
8ca8c7bc | 52 | typedef struct PRePPCIState { |
67c332fd | 53 | PCIHostState parent_obj; |
03a6b667 | 54 | |
963116b0 | 55 | qemu_irq irq[PCI_NUM_PINS]; |
98aca3c8 | 56 | PCIBus pci_bus; |
49a4e212 | 57 | MemoryRegion pci_intack; |
98aca3c8 | 58 | RavenPCIState pci_dev; |
8ca8c7bc | 59 | } PREPPCIState; |
502a5395 | 60 | |
d0b25425 HP |
61 | #define BIOS_SIZE (1024 * 1024) |
62 | ||
a8170e5e | 63 | static inline uint32_t PPC_PCIIO_config(hwaddr addr) |
502a5395 PB |
64 | { |
65 | int i; | |
66 | ||
03a6b667 AF |
67 | for (i = 0; i < 11; i++) { |
68 | if ((addr & (1 << (11 + i))) != 0) { | |
502a5395 | 69 | break; |
03a6b667 | 70 | } |
502a5395 PB |
71 | } |
72 | return (addr & 0x7ff) | (i << 11); | |
73 | } | |
74 | ||
a8170e5e | 75 | static void ppc_pci_io_write(void *opaque, hwaddr addr, |
7e5610ff | 76 | uint64_t val, unsigned int size) |
502a5395 PB |
77 | { |
78 | PREPPCIState *s = opaque; | |
67c332fd AF |
79 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
80 | pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size); | |
502a5395 PB |
81 | } |
82 | ||
a8170e5e | 83 | static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr, |
7e5610ff | 84 | unsigned int size) |
502a5395 PB |
85 | { |
86 | PREPPCIState *s = opaque; | |
67c332fd AF |
87 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
88 | return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size); | |
502a5395 PB |
89 | } |
90 | ||
f81138ce | 91 | static const MemoryRegionOps PPC_PCIIO_ops = { |
7e5610ff AF |
92 | .read = ppc_pci_io_read, |
93 | .write = ppc_pci_io_write, | |
9c95f183 | 94 | .endianness = DEVICE_LITTLE_ENDIAN, |
502a5395 PB |
95 | }; |
96 | ||
a8170e5e | 97 | static uint64_t ppc_intack_read(void *opaque, hwaddr addr, |
6c84ce0d HP |
98 | unsigned int size) |
99 | { | |
100 | return pic_read_irq(isa_pic); | |
101 | } | |
102 | ||
103 | static const MemoryRegionOps PPC_intack_ops = { | |
104 | .read = ppc_intack_read, | |
105 | .valid = { | |
106 | .max_access_size = 1, | |
107 | }, | |
108 | }; | |
109 | ||
d2b59317 | 110 | static int prep_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 111 | { |
80b3ada7 | 112 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
d2b59317 PB |
113 | } |
114 | ||
5d4e84c8 | 115 | static void prep_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 116 | { |
5d4e84c8 JQ |
117 | qemu_irq *pic = opaque; |
118 | ||
8ca8c7bc | 119 | qemu_set_irq(pic[irq_num] , level); |
502a5395 PB |
120 | } |
121 | ||
8d5ce2e5 | 122 | static void raven_pcihost_realizefn(DeviceState *d, Error **errp) |
502a5395 | 123 | { |
8d5ce2e5 | 124 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
8558d942 | 125 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
03a6b667 | 126 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); |
8ca8c7bc | 127 | MemoryRegion *address_space_mem = get_system_memory(); |
8ca8c7bc AF |
128 | int i; |
129 | ||
768d7e2c HP |
130 | isa_mem_base = 0xc0000000; |
131 | ||
963116b0 | 132 | for (i = 0; i < PCI_NUM_PINS; i++) { |
8ca8c7bc AF |
133 | sysbus_init_irq(dev, &s->irq[i]); |
134 | } | |
502a5395 | 135 | |
963116b0 | 136 | pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS); |
502a5395 | 137 | |
40c5dce9 | 138 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s, |
d0ed8076 | 139 | "pci-conf-idx", 1); |
8ca8c7bc AF |
140 | sysbus_add_io(dev, 0xcf8, &h->conf_mem); |
141 | sysbus_init_ioports(&h->busdev, 0xcf8, 1); | |
d0ed8076 | 142 | |
40c5dce9 | 143 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s, |
d0ed8076 | 144 | "pci-conf-data", 1); |
8ca8c7bc AF |
145 | sysbus_add_io(dev, 0xcfc, &h->data_mem); |
146 | sysbus_init_ioports(&h->busdev, 0xcfc, 1); | |
502a5395 | 147 | |
40c5dce9 | 148 | memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000); |
8ca8c7bc | 149 | memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); |
502a5395 | 150 | |
49a4e212 HP |
151 | memory_region_init_io(&s->pci_intack, OBJECT(s), &PPC_intack_ops, s, |
152 | "pci-intack", 1); | |
153 | memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); | |
55526054 | 154 | |
98aca3c8 | 155 | /* TODO Remove once realize propagates to child devices. */ |
8d5ce2e5 | 156 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); |
98aca3c8 AF |
157 | } |
158 | ||
159 | static void raven_pcihost_initfn(Object *obj) | |
160 | { | |
161 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
162 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); | |
163 | MemoryRegion *address_space_mem = get_system_memory(); | |
164 | MemoryRegion *address_space_io = get_system_io(); | |
165 | DeviceState *pci_dev; | |
166 | ||
dd301ca6 | 167 | pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, |
60a0e443 | 168 | address_space_mem, address_space_io, 0, TYPE_PCI_BUS); |
98aca3c8 AF |
169 | h->bus = &s->pci_bus; |
170 | ||
213f0c4f | 171 | object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); |
98aca3c8 AF |
172 | pci_dev = DEVICE(&s->pci_dev); |
173 | qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus)); | |
174 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr", | |
175 | NULL); | |
176 | qdev_prop_set_bit(pci_dev, "multifunction", false); | |
55526054 AF |
177 | } |
178 | ||
179 | static int raven_init(PCIDevice *d) | |
180 | { | |
d0b25425 HP |
181 | RavenPCIState *s = RAVEN_PCI_DEVICE(d); |
182 | char *filename; | |
183 | int bios_size = -1; | |
184 | ||
502a5395 PB |
185 | d->config[0x0C] = 0x08; // cache_line_size |
186 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 PB |
187 | d->config[0x34] = 0x00; // capabilities_pointer |
188 | ||
d0b25425 HP |
189 | memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE); |
190 | memory_region_set_readonly(&s->bios, true); | |
191 | memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), | |
192 | &s->bios); | |
193 | vmstate_register_ram_global(&s->bios); | |
194 | if (s->bios_name) { | |
195 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); | |
196 | if (filename) { | |
197 | if (s->elf_machine != EM_NONE) { | |
198 | bios_size = load_elf(filename, NULL, NULL, NULL, | |
199 | NULL, NULL, 1, s->elf_machine, 0); | |
200 | } | |
201 | if (bios_size < 0) { | |
202 | bios_size = get_image_size(filename); | |
203 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { | |
204 | hwaddr bios_addr; | |
205 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
206 | bios_addr = (uint32_t)(-BIOS_SIZE); | |
207 | bios_size = load_image_targphys(filename, bios_addr, | |
208 | bios_size); | |
209 | } | |
210 | } | |
211 | } | |
212 | if (bios_size < 0 || bios_size > BIOS_SIZE) { | |
213 | hw_error("qemu: could not load bios image '%s'\n", s->bios_name); | |
214 | } | |
215 | if (filename) { | |
216 | g_free(filename); | |
217 | } | |
218 | } | |
219 | ||
55526054 | 220 | return 0; |
502a5395 | 221 | } |
55526054 AF |
222 | |
223 | static const VMStateDescription vmstate_raven = { | |
224 | .name = "raven", | |
225 | .version_id = 0, | |
226 | .minimum_version_id = 0, | |
227 | .fields = (VMStateField[]) { | |
228 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), | |
229 | VMSTATE_END_OF_LIST() | |
230 | }, | |
231 | }; | |
232 | ||
40021f08 AL |
233 | static void raven_class_init(ObjectClass *klass, void *data) |
234 | { | |
235 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 236 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
237 | |
238 | k->init = raven_init; | |
239 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; | |
240 | k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; | |
241 | k->revision = 0x00; | |
242 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
243 | dc->desc = "PReP Host Bridge - Motorola Raven"; |
244 | dc->vmsd = &vmstate_raven; | |
08c58f92 MA |
245 | /* |
246 | * PCI-facing part of the host bridge, not usable without the | |
247 | * host-facing part, which can't be device_add'ed, yet. | |
248 | */ | |
249 | dc->cannot_instantiate_with_device_add_yet = true; | |
40021f08 AL |
250 | } |
251 | ||
4240abff | 252 | static const TypeInfo raven_info = { |
98aca3c8 | 253 | .name = TYPE_RAVEN_PCI_DEVICE, |
39bffca2 AL |
254 | .parent = TYPE_PCI_DEVICE, |
255 | .instance_size = sizeof(RavenPCIState), | |
40021f08 | 256 | .class_init = raven_class_init, |
55526054 AF |
257 | }; |
258 | ||
d0b25425 HP |
259 | static Property raven_pcihost_properties[] = { |
260 | DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, | |
261 | EM_NONE), | |
262 | DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), | |
263 | DEFINE_PROP_END_OF_LIST() | |
264 | }; | |
265 | ||
999e12bb AL |
266 | static void raven_pcihost_class_init(ObjectClass *klass, void *data) |
267 | { | |
39bffca2 | 268 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 269 | |
125ee0ed | 270 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
8d5ce2e5 | 271 | dc->realize = raven_pcihost_realizefn; |
d0b25425 | 272 | dc->props = raven_pcihost_properties; |
39bffca2 | 273 | dc->fw_name = "pci"; |
999e12bb AL |
274 | } |
275 | ||
4240abff | 276 | static const TypeInfo raven_pcihost_info = { |
03a6b667 | 277 | .name = TYPE_RAVEN_PCI_HOST_BRIDGE, |
8558d942 | 278 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 279 | .instance_size = sizeof(PREPPCIState), |
98aca3c8 | 280 | .instance_init = raven_pcihost_initfn, |
999e12bb | 281 | .class_init = raven_pcihost_class_init, |
8ca8c7bc AF |
282 | }; |
283 | ||
83f7d43a | 284 | static void raven_register_types(void) |
55526054 | 285 | { |
39bffca2 AL |
286 | type_register_static(&raven_pcihost_info); |
287 | type_register_static(&raven_info); | |
55526054 AF |
288 | } |
289 | ||
83f7d43a | 290 | type_init(raven_register_types) |