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502a5395 PB |
1 | /* |
2 | * QEMU PREP PCI host | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
98aca3c8 | 5 | * Copyright (c) 2011-2013 Andreas Färber |
5fafdf24 | 6 | * |
502a5395 PB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
0d75590d | 26 | #include "qemu/osdep.h" |
a8d25326 | 27 | #include "qemu-common.h" |
ab3dd749 | 28 | #include "qemu/units.h" |
da34e65c | 29 | #include "qapi/error.h" |
83c9f4ca PB |
30 | #include "hw/pci/pci.h" |
31 | #include "hw/pci/pci_bus.h" | |
32 | #include "hw/pci/pci_host.h" | |
d6454270 | 33 | #include "migration/vmstate.h" |
0d09e41a | 34 | #include "hw/i386/pc.h" |
64552b6b | 35 | #include "hw/irq.h" |
d0b25425 | 36 | #include "hw/loader.h" |
f40b83a4 | 37 | #include "hw/or-irq.h" |
022c62cb | 38 | #include "exec/address-spaces.h" |
d0b25425 | 39 | #include "elf.h" |
502a5395 | 40 | |
98aca3c8 | 41 | #define TYPE_RAVEN_PCI_DEVICE "raven" |
03a6b667 AF |
42 | #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" |
43 | ||
98aca3c8 AF |
44 | #define RAVEN_PCI_DEVICE(obj) \ |
45 | OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE) | |
46 | ||
47 | typedef struct RavenPCIState { | |
48 | PCIDevice dev; | |
d0b25425 HP |
49 | |
50 | uint32_t elf_machine; | |
51 | char *bios_name; | |
52 | MemoryRegion bios; | |
98aca3c8 AF |
53 | } RavenPCIState; |
54 | ||
03a6b667 AF |
55 | #define RAVEN_PCI_HOST_BRIDGE(obj) \ |
56 | OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) | |
57 | ||
8ca8c7bc | 58 | typedef struct PRePPCIState { |
67c332fd | 59 | PCIHostState parent_obj; |
03a6b667 | 60 | |
f40b83a4 | 61 | qemu_or_irq *or_irq; |
55a22902 | 62 | qemu_irq pci_irqs[PCI_NUM_PINS]; |
98aca3c8 | 63 | PCIBus pci_bus; |
9a183916 | 64 | AddressSpace pci_io_as; |
1ae1dc5b | 65 | MemoryRegion pci_io; |
9a183916 | 66 | MemoryRegion pci_io_non_contiguous; |
1fe9e262 | 67 | MemoryRegion pci_memory; |
49a4e212 | 68 | MemoryRegion pci_intack; |
d16644ec HP |
69 | MemoryRegion bm; |
70 | MemoryRegion bm_ram_alias; | |
71 | MemoryRegion bm_pci_memory_alias; | |
72 | AddressSpace bm_as; | |
98aca3c8 | 73 | RavenPCIState pci_dev; |
9a183916 HP |
74 | |
75 | int contiguous_map; | |
f40b83a4 | 76 | bool is_legacy_prep; |
8ca8c7bc | 77 | } PREPPCIState; |
502a5395 | 78 | |
ab3dd749 | 79 | #define BIOS_SIZE (1 * MiB) |
d0b25425 | 80 | |
f205da68 | 81 | static inline uint32_t raven_pci_io_config(hwaddr addr) |
502a5395 PB |
82 | { |
83 | int i; | |
84 | ||
03a6b667 AF |
85 | for (i = 0; i < 11; i++) { |
86 | if ((addr & (1 << (11 + i))) != 0) { | |
502a5395 | 87 | break; |
03a6b667 | 88 | } |
502a5395 PB |
89 | } |
90 | return (addr & 0x7ff) | (i << 11); | |
91 | } | |
92 | ||
f205da68 HP |
93 | static void raven_pci_io_write(void *opaque, hwaddr addr, |
94 | uint64_t val, unsigned int size) | |
502a5395 PB |
95 | { |
96 | PREPPCIState *s = opaque; | |
67c332fd | 97 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
f205da68 | 98 | pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); |
502a5395 PB |
99 | } |
100 | ||
f205da68 HP |
101 | static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, |
102 | unsigned int size) | |
502a5395 PB |
103 | { |
104 | PREPPCIState *s = opaque; | |
67c332fd | 105 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
f205da68 | 106 | return pci_data_read(phb->bus, raven_pci_io_config(addr), size); |
502a5395 PB |
107 | } |
108 | ||
f205da68 HP |
109 | static const MemoryRegionOps raven_pci_io_ops = { |
110 | .read = raven_pci_io_read, | |
111 | .write = raven_pci_io_write, | |
9c95f183 | 112 | .endianness = DEVICE_LITTLE_ENDIAN, |
502a5395 PB |
113 | }; |
114 | ||
f205da68 HP |
115 | static uint64_t raven_intack_read(void *opaque, hwaddr addr, |
116 | unsigned int size) | |
6c84ce0d HP |
117 | { |
118 | return pic_read_irq(isa_pic); | |
119 | } | |
120 | ||
f205da68 HP |
121 | static const MemoryRegionOps raven_intack_ops = { |
122 | .read = raven_intack_read, | |
6c84ce0d HP |
123 | .valid = { |
124 | .max_access_size = 1, | |
125 | }, | |
126 | }; | |
127 | ||
9a183916 HP |
128 | static inline hwaddr raven_io_address(PREPPCIState *s, |
129 | hwaddr addr) | |
130 | { | |
131 | if (s->contiguous_map == 0) { | |
132 | /* 64 KB contiguous space for IOs */ | |
133 | addr &= 0xFFFF; | |
134 | } else { | |
135 | /* 8 MB non-contiguous space for IOs */ | |
136 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
137 | } | |
138 | ||
139 | /* FIXME: handle endianness switch */ | |
140 | ||
141 | return addr; | |
142 | } | |
143 | ||
144 | static uint64_t raven_io_read(void *opaque, hwaddr addr, | |
145 | unsigned int size) | |
146 | { | |
147 | PREPPCIState *s = opaque; | |
148 | uint8_t buf[4]; | |
149 | ||
150 | addr = raven_io_address(s, addr); | |
5c9eb028 PM |
151 | address_space_read(&s->pci_io_as, addr + 0x80000000, |
152 | MEMTXATTRS_UNSPECIFIED, buf, size); | |
9a183916 HP |
153 | |
154 | if (size == 1) { | |
155 | return buf[0]; | |
156 | } else if (size == 2) { | |
7dc176bc | 157 | return lduw_le_p(buf); |
9a183916 | 158 | } else if (size == 4) { |
7dc176bc | 159 | return ldl_le_p(buf); |
9a183916 HP |
160 | } else { |
161 | g_assert_not_reached(); | |
162 | } | |
163 | } | |
164 | ||
165 | static void raven_io_write(void *opaque, hwaddr addr, | |
166 | uint64_t val, unsigned int size) | |
167 | { | |
168 | PREPPCIState *s = opaque; | |
169 | uint8_t buf[4]; | |
170 | ||
171 | addr = raven_io_address(s, addr); | |
172 | ||
173 | if (size == 1) { | |
174 | buf[0] = val; | |
175 | } else if (size == 2) { | |
7dc176bc | 176 | stw_le_p(buf, val); |
9a183916 | 177 | } else if (size == 4) { |
7dc176bc | 178 | stl_le_p(buf, val); |
9a183916 HP |
179 | } else { |
180 | g_assert_not_reached(); | |
181 | } | |
182 | ||
5c9eb028 PM |
183 | address_space_write(&s->pci_io_as, addr + 0x80000000, |
184 | MEMTXATTRS_UNSPECIFIED, buf, size); | |
9a183916 HP |
185 | } |
186 | ||
187 | static const MemoryRegionOps raven_io_ops = { | |
188 | .read = raven_io_read, | |
189 | .write = raven_io_write, | |
190 | .endianness = DEVICE_LITTLE_ENDIAN, | |
191 | .impl.max_access_size = 4, | |
192 | .valid.unaligned = true, | |
193 | }; | |
194 | ||
f205da68 | 195 | static int raven_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 196 | { |
80b3ada7 | 197 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
d2b59317 PB |
198 | } |
199 | ||
f205da68 | 200 | static void raven_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 201 | { |
55a22902 | 202 | PREPPCIState *s = opaque; |
5d4e84c8 | 203 | |
55a22902 | 204 | qemu_set_irq(s->pci_irqs[irq_num], level); |
502a5395 PB |
205 | } |
206 | ||
d16644ec HP |
207 | static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, |
208 | int devfn) | |
209 | { | |
210 | PREPPCIState *s = opaque; | |
211 | ||
212 | return &s->bm_as; | |
213 | } | |
214 | ||
9a183916 HP |
215 | static void raven_change_gpio(void *opaque, int n, int level) |
216 | { | |
217 | PREPPCIState *s = opaque; | |
218 | ||
219 | s->contiguous_map = level; | |
220 | } | |
221 | ||
8d5ce2e5 | 222 | static void raven_pcihost_realizefn(DeviceState *d, Error **errp) |
502a5395 | 223 | { |
8d5ce2e5 | 224 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
8558d942 | 225 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
03a6b667 | 226 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); |
8ca8c7bc | 227 | MemoryRegion *address_space_mem = get_system_memory(); |
8ca8c7bc AF |
228 | int i; |
229 | ||
f40b83a4 MCA |
230 | if (s->is_legacy_prep) { |
231 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
232 | sysbus_init_irq(dev, &s->pci_irqs[i]); | |
233 | } | |
234 | } else { | |
235 | /* According to PReP specification section 6.1.6 "System Interrupt | |
236 | * Assignments", all PCI interrupts are routed via IRQ 15 */ | |
237 | s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); | |
238 | object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines", | |
239 | &error_fatal); | |
240 | object_property_set_bool(OBJECT(s->or_irq), true, "realized", | |
241 | &error_fatal); | |
242 | sysbus_init_irq(dev, &s->or_irq->out_irq); | |
243 | ||
244 | for (i = 0; i < PCI_NUM_PINS; i++) { | |
245 | s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); | |
246 | } | |
8ca8c7bc | 247 | } |
502a5395 | 248 | |
9a183916 HP |
249 | qdev_init_gpio_in(d, raven_change_gpio, 1); |
250 | ||
55a22902 | 251 | pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS); |
502a5395 | 252 | |
2403837e HP |
253 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, |
254 | "pci-conf-idx", 4); | |
1ae1dc5b | 255 | memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); |
d0ed8076 | 256 | |
2403837e HP |
257 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, |
258 | "pci-conf-data", 4); | |
1ae1dc5b | 259 | memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); |
502a5395 | 260 | |
f205da68 HP |
261 | memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, |
262 | "pciio", 0x00400000); | |
8ca8c7bc | 263 | memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); |
502a5395 | 264 | |
f205da68 | 265 | memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, |
49a4e212 HP |
266 | "pci-intack", 1); |
267 | memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); | |
55526054 | 268 | |
98aca3c8 | 269 | /* TODO Remove once realize propagates to child devices. */ |
685f9a34 | 270 | object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp); |
8d5ce2e5 | 271 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); |
98aca3c8 AF |
272 | } |
273 | ||
274 | static void raven_pcihost_initfn(Object *obj) | |
275 | { | |
276 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
277 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); | |
278 | MemoryRegion *address_space_mem = get_system_memory(); | |
98aca3c8 AF |
279 | DeviceState *pci_dev; |
280 | ||
1ae1dc5b | 281 | memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); |
9a183916 HP |
282 | memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, |
283 | "pci-io-non-contiguous", 0x00800000); | |
97db0466 | 284 | memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); |
1ae1dc5b | 285 | address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); |
9a183916 HP |
286 | |
287 | /* CPU address space */ | |
1ae1dc5b | 288 | memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); |
9a183916 HP |
289 | memory_region_add_subregion_overlap(address_space_mem, 0x80000000, |
290 | &s->pci_io_non_contiguous, 1); | |
1fe9e262 | 291 | memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); |
1115ff6d DG |
292 | pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, |
293 | &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); | |
1ae1dc5b | 294 | |
d16644ec HP |
295 | /* Bus master address space */ |
296 | memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX); | |
297 | memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", | |
298 | &s->pci_memory, 0, | |
299 | memory_region_size(&s->pci_memory)); | |
300 | memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", | |
301 | get_system_memory(), 0, 0x80000000); | |
302 | memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); | |
303 | memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); | |
304 | address_space_init(&s->bm_as, &s->bm, "raven-bm"); | |
305 | pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); | |
306 | ||
98aca3c8 AF |
307 | h->bus = &s->pci_bus; |
308 | ||
213f0c4f | 309 | object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); |
98aca3c8 AF |
310 | pci_dev = DEVICE(&s->pci_dev); |
311 | qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus)); | |
312 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr", | |
313 | NULL); | |
314 | qdev_prop_set_bit(pci_dev, "multifunction", false); | |
55526054 AF |
315 | } |
316 | ||
9af21dbe | 317 | static void raven_realize(PCIDevice *d, Error **errp) |
55526054 | 318 | { |
d0b25425 HP |
319 | RavenPCIState *s = RAVEN_PCI_DEVICE(d); |
320 | char *filename; | |
321 | int bios_size = -1; | |
322 | ||
502a5395 PB |
323 | d->config[0x0C] = 0x08; // cache_line_size |
324 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 PB |
325 | d->config[0x34] = 0x00; // capabilities_pointer |
326 | ||
1cfe48c1 | 327 | memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE, |
f8ed85ac | 328 | &error_fatal); |
d0b25425 HP |
329 | memory_region_set_readonly(&s->bios, true); |
330 | memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), | |
331 | &s->bios); | |
d0b25425 HP |
332 | if (s->bios_name) { |
333 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); | |
334 | if (filename) { | |
335 | if (s->elf_machine != EM_NONE) { | |
4366e1db | 336 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, |
7ef295ea | 337 | NULL, NULL, 1, s->elf_machine, 0, 0); |
d0b25425 HP |
338 | } |
339 | if (bios_size < 0) { | |
340 | bios_size = get_image_size(filename); | |
341 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { | |
342 | hwaddr bios_addr; | |
343 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
344 | bios_addr = (uint32_t)(-BIOS_SIZE); | |
345 | bios_size = load_image_targphys(filename, bios_addr, | |
346 | bios_size); | |
347 | } | |
348 | } | |
349 | } | |
fb38ebfb | 350 | g_free(filename); |
d0b25425 | 351 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
fb38ebfb TH |
352 | memory_region_del_subregion(get_system_memory(), &s->bios); |
353 | error_setg(errp, "Could not load bios image '%s'", s->bios_name); | |
354 | return; | |
d0b25425 | 355 | } |
d0b25425 | 356 | } |
fb38ebfb TH |
357 | |
358 | vmstate_register_ram_global(&s->bios); | |
502a5395 | 359 | } |
55526054 AF |
360 | |
361 | static const VMStateDescription vmstate_raven = { | |
362 | .name = "raven", | |
363 | .version_id = 0, | |
364 | .minimum_version_id = 0, | |
365 | .fields = (VMStateField[]) { | |
366 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), | |
367 | VMSTATE_END_OF_LIST() | |
368 | }, | |
369 | }; | |
370 | ||
40021f08 AL |
371 | static void raven_class_init(ObjectClass *klass, void *data) |
372 | { | |
373 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 374 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 375 | |
9af21dbe | 376 | k->realize = raven_realize; |
40021f08 AL |
377 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; |
378 | k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; | |
379 | k->revision = 0x00; | |
380 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 AL |
381 | dc->desc = "PReP Host Bridge - Motorola Raven"; |
382 | dc->vmsd = &vmstate_raven; | |
08c58f92 | 383 | /* |
9280eb34 MA |
384 | * Reason: PCI-facing part of the host bridge, not usable without |
385 | * the host-facing part, which can't be device_add'ed, yet. | |
08c58f92 | 386 | */ |
e90f2a8c | 387 | dc->user_creatable = false; |
40021f08 AL |
388 | } |
389 | ||
4240abff | 390 | static const TypeInfo raven_info = { |
98aca3c8 | 391 | .name = TYPE_RAVEN_PCI_DEVICE, |
39bffca2 AL |
392 | .parent = TYPE_PCI_DEVICE, |
393 | .instance_size = sizeof(RavenPCIState), | |
40021f08 | 394 | .class_init = raven_class_init, |
fd3b02c8 EH |
395 | .interfaces = (InterfaceInfo[]) { |
396 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
397 | { }, | |
398 | }, | |
55526054 AF |
399 | }; |
400 | ||
d0b25425 HP |
401 | static Property raven_pcihost_properties[] = { |
402 | DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, | |
403 | EM_NONE), | |
404 | DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), | |
f40b83a4 MCA |
405 | /* Temporary workaround until legacy prep machine is removed */ |
406 | DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, | |
407 | false), | |
d0b25425 HP |
408 | DEFINE_PROP_END_OF_LIST() |
409 | }; | |
410 | ||
999e12bb AL |
411 | static void raven_pcihost_class_init(ObjectClass *klass, void *data) |
412 | { | |
39bffca2 | 413 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 414 | |
125ee0ed | 415 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
8d5ce2e5 | 416 | dc->realize = raven_pcihost_realizefn; |
d0b25425 | 417 | dc->props = raven_pcihost_properties; |
39bffca2 | 418 | dc->fw_name = "pci"; |
999e12bb AL |
419 | } |
420 | ||
4240abff | 421 | static const TypeInfo raven_pcihost_info = { |
03a6b667 | 422 | .name = TYPE_RAVEN_PCI_HOST_BRIDGE, |
8558d942 | 423 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 424 | .instance_size = sizeof(PREPPCIState), |
98aca3c8 | 425 | .instance_init = raven_pcihost_initfn, |
999e12bb | 426 | .class_init = raven_pcihost_class_init, |
8ca8c7bc AF |
427 | }; |
428 | ||
83f7d43a | 429 | static void raven_register_types(void) |
55526054 | 430 | { |
39bffca2 AL |
431 | type_register_static(&raven_pcihost_info); |
432 | type_register_static(&raven_info); | |
55526054 AF |
433 | } |
434 | ||
83f7d43a | 435 | type_init(raven_register_types) |