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df2d8b3e IY |
1 | /* |
2 | * QEMU MCH/ICH9 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * Copyright (c) 2009, 2010, 2011 | |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
ef9f7b58 | 10 | * This is based on piix.c, but heavily modified. |
df2d8b3e IY |
11 | * |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
b6a0aa05 | 30 | #include "qemu/osdep.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
0d09e41a | 32 | #include "hw/pci-host/q35.h" |
da34e65c | 33 | #include "qapi/error.h" |
39848901 | 34 | #include "qapi/visitor.h" |
df2d8b3e IY |
35 | |
36 | /**************************************************************************** | |
37 | * Q35 host | |
38 | */ | |
39 | ||
62d92e43 | 40 | static void q35_host_realize(DeviceState *dev, Error **errp) |
df2d8b3e | 41 | { |
ce88812f HT |
42 | PCIHostState *pci = PCI_HOST_BRIDGE(dev); |
43 | Q35PCIHost *s = Q35_HOST_DEVICE(dev); | |
62d92e43 | 44 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
df2d8b3e | 45 | |
62d92e43 HT |
46 | sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); |
47 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); | |
df2d8b3e | 48 | |
62d92e43 HT |
49 | sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); |
50 | sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); | |
df2d8b3e | 51 | |
ce88812f HT |
52 | pci->bus = pci_bus_new(DEVICE(s), "pcie.0", |
53 | s->mch.pci_address_space, s->mch.address_space_io, | |
54 | 0, TYPE_PCIE_BUS); | |
621d983a | 55 | PC_MACHINE(qdev_get_machine())->bus = pci->bus; |
ce88812f | 56 | qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); |
df2d8b3e | 57 | qdev_init_nofail(DEVICE(&s->mch)); |
df2d8b3e IY |
58 | } |
59 | ||
568f0690 DG |
60 | static const char *q35_host_root_bus_path(PCIHostState *host_bridge, |
61 | PCIBus *rootbus) | |
62 | { | |
04c7d8b8 CR |
63 | Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); |
64 | ||
65 | /* For backwards compat with old device paths */ | |
66 | if (s->mch.short_root_bus) { | |
67 | return "0000"; | |
68 | } | |
69 | return "0000:00"; | |
568f0690 DG |
70 | } |
71 | ||
39848901 | 72 | static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, |
d7bce999 | 73 | const char *name, void *opaque, |
39848901 IM |
74 | Error **errp) |
75 | { | |
76 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
a0efbf16 MA |
77 | uint64_t val64; |
78 | uint32_t value; | |
39848901 | 79 | |
a0efbf16 MA |
80 | val64 = range_is_empty(&s->mch.pci_hole) |
81 | ? 0 : range_lob(&s->mch.pci_hole); | |
82 | value = val64; | |
83 | assert(value == val64); | |
51e72bc1 | 84 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
85 | } |
86 | ||
87 | static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, | |
d7bce999 | 88 | const char *name, void *opaque, |
39848901 IM |
89 | Error **errp) |
90 | { | |
91 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
a0efbf16 MA |
92 | uint64_t val64; |
93 | uint32_t value; | |
39848901 | 94 | |
a0efbf16 MA |
95 | val64 = range_is_empty(&s->mch.pci_hole) |
96 | ? 0 : range_upb(&s->mch.pci_hole) + 1; | |
97 | value = val64; | |
98 | assert(value == val64); | |
51e72bc1 | 99 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
100 | } |
101 | ||
102 | static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, | |
d7bce999 | 103 | const char *name, void *opaque, |
39848901 IM |
104 | Error **errp) |
105 | { | |
8b42d730 MT |
106 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
107 | Range w64; | |
a0efbf16 | 108 | uint64_t value; |
8b42d730 MT |
109 | |
110 | pci_bus_get_w64_range(h->bus, &w64); | |
a0efbf16 MA |
111 | value = range_is_empty(&w64) ? 0 : range_lob(&w64); |
112 | visit_type_uint64(v, name, &value, errp); | |
39848901 IM |
113 | } |
114 | ||
115 | static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, | |
d7bce999 | 116 | const char *name, void *opaque, |
39848901 IM |
117 | Error **errp) |
118 | { | |
8b42d730 MT |
119 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
120 | Range w64; | |
a0efbf16 | 121 | uint64_t value; |
39848901 | 122 | |
8b42d730 | 123 | pci_bus_get_w64_range(h->bus, &w64); |
a0efbf16 MA |
124 | value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; |
125 | visit_type_uint64(v, name, &value, errp); | |
39848901 IM |
126 | } |
127 | ||
d7bce999 EB |
128 | static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, |
129 | void *opaque, Error **errp) | |
cbcaf79e MT |
130 | { |
131 | PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); | |
cbcaf79e | 132 | |
d015c4ea | 133 | visit_type_uint64(v, name, &e->size, errp); |
cbcaf79e MT |
134 | } |
135 | ||
df2d8b3e | 136 | static Property mch_props[] = { |
87f65245 | 137 | DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, |
df2d8b3e | 138 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), |
39848901 IM |
139 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, |
140 | mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), | |
04c7d8b8 | 141 | DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), |
401f2f3e EV |
142 | DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, |
143 | mch.below_4g_mem_size, 0), | |
144 | DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, | |
145 | mch.above_4g_mem_size, 0), | |
df2d8b3e IY |
146 | DEFINE_PROP_END_OF_LIST(), |
147 | }; | |
148 | ||
149 | static void q35_host_class_init(ObjectClass *klass, void *data) | |
150 | { | |
151 | DeviceClass *dc = DEVICE_CLASS(klass); | |
568f0690 | 152 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
df2d8b3e | 153 | |
568f0690 | 154 | hc->root_bus_path = q35_host_root_bus_path; |
62d92e43 | 155 | dc->realize = q35_host_realize; |
df2d8b3e | 156 | dc->props = mch_props; |
bf8d4924 | 157 | /* Reason: needs to be wired up by pc_q35_init */ |
e90f2a8c | 158 | dc->user_creatable = false; |
125ee0ed | 159 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
68c0e134 | 160 | dc->fw_name = "pci"; |
df2d8b3e IY |
161 | } |
162 | ||
163 | static void q35_host_initfn(Object *obj) | |
164 | { | |
165 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
62d92e43 HT |
166 | PCIHostState *phb = PCI_HOST_BRIDGE(obj); |
167 | ||
168 | memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, | |
169 | "pci-conf-idx", 4); | |
170 | memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, | |
171 | "pci-conf-data", 4); | |
df2d8b3e | 172 | |
213f0c4f | 173 | object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); |
df2d8b3e IY |
174 | object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); |
175 | qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); | |
176 | qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); | |
39848901 IM |
177 | |
178 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", | |
179 | q35_host_get_pci_hole_start, | |
180 | NULL, NULL, NULL, NULL); | |
181 | ||
182 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", | |
183 | q35_host_get_pci_hole_end, | |
184 | NULL, NULL, NULL, NULL); | |
185 | ||
186 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", | |
187 | q35_host_get_pci_hole64_start, | |
188 | NULL, NULL, NULL, NULL); | |
189 | ||
190 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", | |
191 | q35_host_get_pci_hole64_end, | |
192 | NULL, NULL, NULL, NULL); | |
193 | ||
cbcaf79e MT |
194 | object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", |
195 | q35_host_get_mmcfg_size, | |
196 | NULL, NULL, NULL, NULL); | |
197 | ||
401f2f3e EV |
198 | object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, |
199 | (Object **) &s->mch.ram_memory, | |
200 | qdev_prop_allow_set_link_before_realize, 0, NULL); | |
201 | ||
202 | object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, | |
203 | (Object **) &s->mch.pci_address_space, | |
204 | qdev_prop_allow_set_link_before_realize, 0, NULL); | |
205 | ||
206 | object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, | |
207 | (Object **) &s->mch.system_memory, | |
208 | qdev_prop_allow_set_link_before_realize, 0, NULL); | |
209 | ||
210 | object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, | |
211 | (Object **) &s->mch.address_space_io, | |
212 | qdev_prop_allow_set_link_before_realize, 0, NULL); | |
213 | ||
39848901 IM |
214 | /* Leave enough space for the biggest MCFG BAR */ |
215 | /* TODO: this matches current bios behaviour, but | |
216 | * it's not a power of two, which means an MTRR | |
217 | * can't cover it exactly. | |
218 | */ | |
a0efbf16 MA |
219 | range_set_bounds(&s->mch.pci_hole, |
220 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, | |
221 | IO_APIC_DEFAULT_ADDRESS - 1); | |
df2d8b3e IY |
222 | } |
223 | ||
224 | static const TypeInfo q35_host_info = { | |
225 | .name = TYPE_Q35_HOST_DEVICE, | |
226 | .parent = TYPE_PCIE_HOST_BRIDGE, | |
227 | .instance_size = sizeof(Q35PCIHost), | |
228 | .instance_init = q35_host_initfn, | |
229 | .class_init = q35_host_class_init, | |
230 | }; | |
231 | ||
232 | /**************************************************************************** | |
233 | * MCH D0:F0 | |
234 | */ | |
235 | ||
bafc90bd GH |
236 | static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) |
237 | { | |
238 | return 0xffffffff; | |
239 | } | |
240 | ||
241 | static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, | |
242 | unsigned width) | |
243 | { | |
244 | /* nothing */ | |
245 | } | |
246 | ||
247 | static const MemoryRegionOps tseg_blackhole_ops = { | |
248 | .read = tseg_blackhole_read, | |
249 | .write = tseg_blackhole_write, | |
250 | .endianness = DEVICE_NATIVE_ENDIAN, | |
251 | .valid.min_access_size = 1, | |
252 | .valid.max_access_size = 4, | |
253 | .impl.min_access_size = 4, | |
254 | .impl.max_access_size = 4, | |
255 | .endianness = DEVICE_LITTLE_ENDIAN, | |
256 | }; | |
257 | ||
df2d8b3e IY |
258 | /* PCIe MMCFG */ |
259 | static void mch_update_pciexbar(MCHPCIState *mch) | |
260 | { | |
ce88812f HT |
261 | PCIDevice *pci_dev = PCI_DEVICE(mch); |
262 | BusState *bus = qdev_get_parent_bus(DEVICE(mch)); | |
263 | PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); | |
df2d8b3e IY |
264 | |
265 | uint64_t pciexbar; | |
266 | int enable; | |
267 | uint64_t addr; | |
268 | uint64_t addr_mask; | |
269 | uint32_t length; | |
270 | ||
271 | pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); | |
272 | enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; | |
273 | addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; | |
274 | switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { | |
275 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: | |
276 | length = 256 * 1024 * 1024; | |
277 | break; | |
278 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: | |
279 | length = 128 * 1024 * 1024; | |
280 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | | |
281 | MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
282 | break; | |
283 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: | |
284 | length = 64 * 1024 * 1024; | |
285 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
286 | break; | |
287 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: | |
288 | default: | |
df2d8b3e | 289 | abort(); |
df2d8b3e IY |
290 | } |
291 | addr = pciexbar & addr_mask; | |
ce88812f | 292 | pcie_host_mmcfg_update(pehb, enable, addr, length); |
636228a8 MT |
293 | /* Leave enough space for the MCFG BAR */ |
294 | /* | |
295 | * TODO: this matches current bios behaviour, but it's not a power of two, | |
296 | * which means an MTRR can't cover it exactly. | |
297 | */ | |
298 | if (enable) { | |
a0efbf16 MA |
299 | range_set_bounds(&mch->pci_hole, |
300 | addr + length, | |
301 | IO_APIC_DEFAULT_ADDRESS - 1); | |
636228a8 | 302 | } else { |
a0efbf16 MA |
303 | range_set_bounds(&mch->pci_hole, |
304 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, | |
305 | IO_APIC_DEFAULT_ADDRESS - 1); | |
636228a8 | 306 | } |
df2d8b3e IY |
307 | } |
308 | ||
309 | /* PAM */ | |
310 | static void mch_update_pam(MCHPCIState *mch) | |
311 | { | |
ce88812f | 312 | PCIDevice *pd = PCI_DEVICE(mch); |
df2d8b3e IY |
313 | int i; |
314 | ||
315 | memory_region_transaction_begin(); | |
316 | for (i = 0; i < 13; i++) { | |
317 | pam_update(&mch->pam_regions[i], i, | |
ce88812f | 318 | pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); |
df2d8b3e IY |
319 | } |
320 | memory_region_transaction_commit(); | |
321 | } | |
322 | ||
323 | /* SMRAM */ | |
324 | static void mch_update_smram(MCHPCIState *mch) | |
325 | { | |
ce88812f | 326 | PCIDevice *pd = PCI_DEVICE(mch); |
64130fa4 | 327 | bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); |
bafc90bd | 328 | uint32_t tseg_size; |
ce88812f | 329 | |
68c77acf GH |
330 | /* implement SMRAM.D_LCK */ |
331 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { | |
332 | pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; | |
333 | pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; | |
334 | pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; | |
335 | } | |
336 | ||
df2d8b3e | 337 | memory_region_transaction_begin(); |
64130fa4 PB |
338 | |
339 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { | |
340 | /* Hide (!) low SMRAM if H_SMRAME = 1 */ | |
341 | memory_region_set_enabled(&mch->smram_region, h_smrame); | |
342 | /* Show high SMRAM if H_SMRAME = 1 */ | |
343 | memory_region_set_enabled(&mch->open_high_smram, h_smrame); | |
344 | } else { | |
345 | /* Hide high SMRAM and low SMRAM */ | |
346 | memory_region_set_enabled(&mch->smram_region, true); | |
347 | memory_region_set_enabled(&mch->open_high_smram, false); | |
348 | } | |
349 | ||
350 | if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { | |
351 | memory_region_set_enabled(&mch->low_smram, !h_smrame); | |
352 | memory_region_set_enabled(&mch->high_smram, h_smrame); | |
353 | } else { | |
354 | memory_region_set_enabled(&mch->low_smram, false); | |
355 | memory_region_set_enabled(&mch->high_smram, false); | |
356 | } | |
357 | ||
bafc90bd GH |
358 | if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { |
359 | switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & | |
360 | MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { | |
361 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: | |
362 | tseg_size = 1024 * 1024; | |
363 | break; | |
364 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: | |
365 | tseg_size = 1024 * 1024 * 2; | |
366 | break; | |
367 | case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: | |
368 | tseg_size = 1024 * 1024 * 8; | |
369 | break; | |
370 | default: | |
371 | tseg_size = 0; | |
372 | break; | |
373 | } | |
374 | } else { | |
375 | tseg_size = 0; | |
376 | } | |
377 | memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); | |
378 | memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); | |
379 | memory_region_set_size(&mch->tseg_blackhole, tseg_size); | |
380 | memory_region_add_subregion_overlap(mch->system_memory, | |
381 | mch->below_4g_mem_size - tseg_size, | |
382 | &mch->tseg_blackhole, 1); | |
383 | ||
384 | memory_region_set_enabled(&mch->tseg_window, tseg_size); | |
385 | memory_region_set_size(&mch->tseg_window, tseg_size); | |
386 | memory_region_set_address(&mch->tseg_window, | |
387 | mch->below_4g_mem_size - tseg_size); | |
388 | memory_region_set_alias_offset(&mch->tseg_window, | |
389 | mch->below_4g_mem_size - tseg_size); | |
390 | ||
df2d8b3e IY |
391 | memory_region_transaction_commit(); |
392 | } | |
393 | ||
df2d8b3e IY |
394 | static void mch_write_config(PCIDevice *d, |
395 | uint32_t address, uint32_t val, int len) | |
396 | { | |
397 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
398 | ||
df2d8b3e IY |
399 | pci_default_write_config(d, address, val, len); |
400 | ||
401 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, | |
402 | MCH_HOST_BRIDGE_PAM_SIZE)) { | |
403 | mch_update_pam(mch); | |
404 | } | |
405 | ||
406 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, | |
407 | MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { | |
408 | mch_update_pciexbar(mch); | |
409 | } | |
410 | ||
263cf436 BZ |
411 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, |
412 | MCH_HOST_BRIDGE_SMRAM_SIZE)) { | |
df2d8b3e IY |
413 | mch_update_smram(mch); |
414 | } | |
415 | } | |
416 | ||
417 | static void mch_update(MCHPCIState *mch) | |
418 | { | |
419 | mch_update_pciexbar(mch); | |
420 | mch_update_pam(mch); | |
421 | mch_update_smram(mch); | |
422 | } | |
423 | ||
424 | static int mch_post_load(void *opaque, int version_id) | |
425 | { | |
426 | MCHPCIState *mch = opaque; | |
427 | mch_update(mch); | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static const VMStateDescription vmstate_mch = { | |
432 | .name = "mch", | |
433 | .version_id = 1, | |
434 | .minimum_version_id = 1, | |
df2d8b3e | 435 | .post_load = mch_post_load, |
d49805ae | 436 | .fields = (VMStateField[]) { |
ce88812f | 437 | VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), |
f809c605 PB |
438 | /* Used to be smm_enabled, which was basically always zero because |
439 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. | |
440 | */ | |
441 | VMSTATE_UNUSED(1), | |
df2d8b3e IY |
442 | VMSTATE_END_OF_LIST() |
443 | } | |
444 | }; | |
445 | ||
446 | static void mch_reset(DeviceState *qdev) | |
447 | { | |
448 | PCIDevice *d = PCI_DEVICE(qdev); | |
449 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
450 | ||
451 | pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, | |
452 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); | |
453 | ||
263cf436 | 454 | d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; |
77447524 | 455 | d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; |
b66a67d7 GH |
456 | d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; |
457 | d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; | |
df2d8b3e IY |
458 | |
459 | mch_update(mch); | |
460 | } | |
461 | ||
9af21dbe | 462 | static void mch_realize(PCIDevice *d, Error **errp) |
df2d8b3e IY |
463 | { |
464 | int i; | |
df2d8b3e | 465 | MCHPCIState *mch = MCH_PCI_DEVICE(d); |
83d08f26 MT |
466 | |
467 | /* setup pci memory mapping */ | |
468 | pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, | |
469 | mch->pci_address_space); | |
470 | ||
fe6567d5 | 471 | /* if *disabled* show SMRAM to all CPUs */ |
40c5dce9 | 472 | memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", |
df2d8b3e IY |
473 | mch->pci_address_space, 0xa0000, 0x20000); |
474 | memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, | |
475 | &mch->smram_region, 1); | |
fe6567d5 PB |
476 | memory_region_set_enabled(&mch->smram_region, true); |
477 | ||
64130fa4 PB |
478 | memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", |
479 | mch->ram_memory, 0xa0000, 0x20000); | |
480 | memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, | |
481 | &mch->open_high_smram, 1); | |
482 | memory_region_set_enabled(&mch->open_high_smram, false); | |
483 | ||
fe6567d5 PB |
484 | /* smram, as seen by SMM CPUs */ |
485 | memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); | |
486 | memory_region_set_enabled(&mch->smram, true); | |
487 | memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", | |
f809c605 | 488 | mch->ram_memory, 0xa0000, 0x20000); |
fe6567d5 PB |
489 | memory_region_set_enabled(&mch->low_smram, true); |
490 | memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); | |
64130fa4 PB |
491 | memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", |
492 | mch->ram_memory, 0xa0000, 0x20000); | |
493 | memory_region_set_enabled(&mch->high_smram, true); | |
494 | memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); | |
bafc90bd GH |
495 | |
496 | memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), | |
497 | &tseg_blackhole_ops, NULL, | |
498 | "tseg-blackhole", 0); | |
499 | memory_region_set_enabled(&mch->tseg_blackhole, false); | |
500 | memory_region_add_subregion_overlap(mch->system_memory, | |
501 | mch->below_4g_mem_size, | |
502 | &mch->tseg_blackhole, 1); | |
503 | ||
504 | memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", | |
505 | mch->ram_memory, mch->below_4g_mem_size, 0); | |
506 | memory_region_set_enabled(&mch->tseg_window, false); | |
507 | memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, | |
508 | &mch->tseg_window); | |
fe6567d5 PB |
509 | object_property_add_const_link(qdev_get_machine(), "smram", |
510 | OBJECT(&mch->smram), &error_abort); | |
511 | ||
ac40aa15 LT |
512 | init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, |
513 | mch->pci_address_space, &mch->pam_regions[0], | |
514 | PAM_BIOS_BASE, PAM_BIOS_SIZE); | |
df2d8b3e | 515 | for (i = 0; i < 12; ++i) { |
ac40aa15 LT |
516 | init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, |
517 | mch->pci_address_space, &mch->pam_regions[i+1], | |
518 | PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); | |
df2d8b3e | 519 | } |
df2d8b3e IY |
520 | } |
521 | ||
6f1426ab MT |
522 | uint64_t mch_mcfg_base(void) |
523 | { | |
524 | bool ambiguous; | |
525 | Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); | |
526 | if (!o) { | |
527 | return 0; | |
528 | } | |
529 | return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; | |
530 | } | |
531 | ||
df2d8b3e IY |
532 | static void mch_class_init(ObjectClass *klass, void *data) |
533 | { | |
534 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
535 | DeviceClass *dc = DEVICE_CLASS(klass); | |
536 | ||
9af21dbe | 537 | k->realize = mch_realize; |
df2d8b3e IY |
538 | k->config_write = mch_write_config; |
539 | dc->reset = mch_reset; | |
125ee0ed | 540 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
df2d8b3e IY |
541 | dc->desc = "Host bridge"; |
542 | dc->vmsd = &vmstate_mch; | |
543 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
544 | k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; | |
451f7846 | 545 | k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; |
df2d8b3e | 546 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
08c58f92 MA |
547 | /* |
548 | * PCI-facing part of the host bridge, not usable without the | |
549 | * host-facing part, which can't be device_add'ed, yet. | |
550 | */ | |
e90f2a8c | 551 | dc->user_creatable = false; |
df2d8b3e IY |
552 | } |
553 | ||
554 | static const TypeInfo mch_info = { | |
555 | .name = TYPE_MCH_PCI_DEVICE, | |
556 | .parent = TYPE_PCI_DEVICE, | |
557 | .instance_size = sizeof(MCHPCIState), | |
558 | .class_init = mch_class_init, | |
559 | }; | |
560 | ||
561 | static void q35_register(void) | |
562 | { | |
563 | type_register_static(&mch_info); | |
564 | type_register_static(&q35_host_info); | |
565 | } | |
566 | ||
567 | type_init(q35_register); |