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df2d8b3e IY |
1 | /* |
2 | * QEMU MCH/ICH9 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * Copyright (c) 2009, 2010, 2011 | |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
10 | * This is based on piix_pci.c, but heavily modified. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
83c9f4ca | 30 | #include "hw/hw.h" |
0d09e41a | 31 | #include "hw/pci-host/q35.h" |
df2d8b3e IY |
32 | |
33 | /**************************************************************************** | |
34 | * Q35 host | |
35 | */ | |
36 | ||
37 | static int q35_host_init(SysBusDevice *dev) | |
38 | { | |
39 | PCIBus *b; | |
40 | PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); | |
41 | Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); | |
42 | ||
43 | memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci, | |
44 | "pci-conf-idx", 4); | |
45 | sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); | |
46 | sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); | |
47 | ||
48 | memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci, | |
49 | "pci-conf-data", 4); | |
50 | sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); | |
51 | sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); | |
52 | ||
53 | if (pcie_host_init(&s->host) < 0) { | |
54 | return -1; | |
55 | } | |
56 | b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", | |
60a0e443 | 57 | s->mch.pci_address_space, s->mch.address_space_io, |
afb661eb | 58 | 0, TYPE_PCIE_BUS); |
df2d8b3e IY |
59 | s->host.pci.bus = b; |
60 | qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); | |
61 | qdev_init_nofail(DEVICE(&s->mch)); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
66 | static Property mch_props[] = { | |
67 | DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, | |
68 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), | |
69 | DEFINE_PROP_END_OF_LIST(), | |
70 | }; | |
71 | ||
72 | static void q35_host_class_init(ObjectClass *klass, void *data) | |
73 | { | |
74 | DeviceClass *dc = DEVICE_CLASS(klass); | |
75 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
76 | ||
77 | k->init = q35_host_init; | |
78 | dc->props = mch_props; | |
68c0e134 | 79 | dc->fw_name = "pci"; |
df2d8b3e IY |
80 | } |
81 | ||
82 | static void q35_host_initfn(Object *obj) | |
83 | { | |
84 | Q35PCIHost *s = Q35_HOST_DEVICE(obj); | |
85 | ||
86 | object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); | |
87 | object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); | |
88 | qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); | |
89 | qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); | |
90 | } | |
91 | ||
92 | static const TypeInfo q35_host_info = { | |
93 | .name = TYPE_Q35_HOST_DEVICE, | |
94 | .parent = TYPE_PCIE_HOST_BRIDGE, | |
95 | .instance_size = sizeof(Q35PCIHost), | |
96 | .instance_init = q35_host_initfn, | |
97 | .class_init = q35_host_class_init, | |
98 | }; | |
99 | ||
100 | /**************************************************************************** | |
101 | * MCH D0:F0 | |
102 | */ | |
103 | ||
104 | /* PCIe MMCFG */ | |
105 | static void mch_update_pciexbar(MCHPCIState *mch) | |
106 | { | |
107 | PCIDevice *pci_dev = &mch->d; | |
108 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); | |
109 | DeviceState *qdev = bus->parent; | |
110 | Q35PCIHost *s = Q35_HOST_DEVICE(qdev); | |
111 | ||
112 | uint64_t pciexbar; | |
113 | int enable; | |
114 | uint64_t addr; | |
115 | uint64_t addr_mask; | |
116 | uint32_t length; | |
117 | ||
118 | pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); | |
119 | enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; | |
120 | addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; | |
121 | switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { | |
122 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: | |
123 | length = 256 * 1024 * 1024; | |
124 | break; | |
125 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: | |
126 | length = 128 * 1024 * 1024; | |
127 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | | |
128 | MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
129 | break; | |
130 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: | |
131 | length = 64 * 1024 * 1024; | |
132 | addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; | |
133 | break; | |
134 | case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: | |
135 | default: | |
136 | enable = 0; | |
137 | length = 0; | |
138 | abort(); | |
139 | break; | |
140 | } | |
141 | addr = pciexbar & addr_mask; | |
142 | pcie_host_mmcfg_update(&s->host, enable, addr, length); | |
143 | } | |
144 | ||
145 | /* PAM */ | |
146 | static void mch_update_pam(MCHPCIState *mch) | |
147 | { | |
148 | int i; | |
149 | ||
150 | memory_region_transaction_begin(); | |
151 | for (i = 0; i < 13; i++) { | |
152 | pam_update(&mch->pam_regions[i], i, | |
153 | mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); | |
154 | } | |
155 | memory_region_transaction_commit(); | |
156 | } | |
157 | ||
158 | /* SMRAM */ | |
159 | static void mch_update_smram(MCHPCIState *mch) | |
160 | { | |
161 | memory_region_transaction_begin(); | |
162 | smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM], | |
163 | mch->smm_enabled); | |
164 | memory_region_transaction_commit(); | |
165 | } | |
166 | ||
167 | static void mch_set_smm(int smm, void *arg) | |
168 | { | |
169 | MCHPCIState *mch = arg; | |
170 | ||
171 | memory_region_transaction_begin(); | |
172 | smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM], | |
173 | &mch->smram_region); | |
174 | memory_region_transaction_commit(); | |
175 | } | |
176 | ||
177 | static void mch_write_config(PCIDevice *d, | |
178 | uint32_t address, uint32_t val, int len) | |
179 | { | |
180 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
181 | ||
182 | /* XXX: implement SMRAM.D_LOCK */ | |
183 | pci_default_write_config(d, address, val, len); | |
184 | ||
185 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, | |
186 | MCH_HOST_BRIDGE_PAM_SIZE)) { | |
187 | mch_update_pam(mch); | |
188 | } | |
189 | ||
190 | if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, | |
191 | MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { | |
192 | mch_update_pciexbar(mch); | |
193 | } | |
194 | ||
195 | if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, | |
196 | MCH_HOST_BRDIGE_SMRAM_SIZE)) { | |
197 | mch_update_smram(mch); | |
198 | } | |
199 | } | |
200 | ||
201 | static void mch_update(MCHPCIState *mch) | |
202 | { | |
203 | mch_update_pciexbar(mch); | |
204 | mch_update_pam(mch); | |
205 | mch_update_smram(mch); | |
206 | } | |
207 | ||
208 | static int mch_post_load(void *opaque, int version_id) | |
209 | { | |
210 | MCHPCIState *mch = opaque; | |
211 | mch_update(mch); | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static const VMStateDescription vmstate_mch = { | |
216 | .name = "mch", | |
217 | .version_id = 1, | |
218 | .minimum_version_id = 1, | |
219 | .minimum_version_id_old = 1, | |
220 | .post_load = mch_post_load, | |
221 | .fields = (VMStateField []) { | |
222 | VMSTATE_PCI_DEVICE(d, MCHPCIState), | |
223 | VMSTATE_UINT8(smm_enabled, MCHPCIState), | |
224 | VMSTATE_END_OF_LIST() | |
225 | } | |
226 | }; | |
227 | ||
228 | static void mch_reset(DeviceState *qdev) | |
229 | { | |
230 | PCIDevice *d = PCI_DEVICE(qdev); | |
231 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
232 | ||
233 | pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, | |
234 | MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); | |
235 | ||
236 | d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; | |
237 | ||
238 | mch_update(mch); | |
239 | } | |
240 | ||
241 | static int mch_init(PCIDevice *d) | |
242 | { | |
243 | int i; | |
244 | hwaddr pci_hole64_size; | |
245 | MCHPCIState *mch = MCH_PCI_DEVICE(d); | |
246 | ||
3459a625 MT |
247 | /* Leave enough space for the biggest MCFG BAR */ |
248 | /* TODO: this matches current bios behaviour, but | |
249 | * it's not a power of two, which means an MTRR | |
250 | * can't cover it exactly. | |
251 | */ | |
252 | mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + | |
253 | MCH_HOST_BRIDGE_PCIEXBAR_MAX; | |
254 | ||
df2d8b3e IY |
255 | /* setup pci memory regions */ |
256 | memory_region_init_alias(&mch->pci_hole, "pci-hole", | |
257 | mch->pci_address_space, | |
258 | mch->below_4g_mem_size, | |
259 | 0x100000000ULL - mch->below_4g_mem_size); | |
260 | memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, | |
261 | &mch->pci_hole); | |
262 | pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : | |
263 | ((uint64_t)1 << 62)); | |
264 | memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64", | |
265 | mch->pci_address_space, | |
266 | 0x100000000ULL + mch->above_4g_mem_size, | |
267 | pci_hole64_size); | |
268 | if (pci_hole64_size) { | |
269 | memory_region_add_subregion(mch->system_memory, | |
270 | 0x100000000ULL + mch->above_4g_mem_size, | |
271 | &mch->pci_hole_64bit); | |
272 | } | |
273 | /* smram */ | |
274 | cpu_smm_register(&mch_set_smm, mch); | |
275 | memory_region_init_alias(&mch->smram_region, "smram-region", | |
276 | mch->pci_address_space, 0xa0000, 0x20000); | |
277 | memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, | |
278 | &mch->smram_region, 1); | |
279 | memory_region_set_enabled(&mch->smram_region, false); | |
280 | init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, | |
281 | &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); | |
282 | for (i = 0; i < 12; ++i) { | |
283 | init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space, | |
284 | &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, | |
285 | PAM_EXPAN_SIZE); | |
286 | } | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static void mch_class_init(ObjectClass *klass, void *data) | |
291 | { | |
292 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
293 | DeviceClass *dc = DEVICE_CLASS(klass); | |
294 | ||
295 | k->init = mch_init; | |
296 | k->config_write = mch_write_config; | |
297 | dc->reset = mch_reset; | |
298 | dc->desc = "Host bridge"; | |
299 | dc->vmsd = &vmstate_mch; | |
300 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
301 | k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; | |
302 | k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; | |
303 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
304 | } | |
305 | ||
306 | static const TypeInfo mch_info = { | |
307 | .name = TYPE_MCH_PCI_DEVICE, | |
308 | .parent = TYPE_PCI_DEVICE, | |
309 | .instance_size = sizeof(MCHPCIState), | |
310 | .class_init = mch_class_init, | |
311 | }; | |
312 | ||
313 | static void q35_register(void) | |
314 | { | |
315 | type_register_static(&mch_info); | |
316 | type_register_static(&q35_host_info); | |
317 | } | |
318 | ||
319 | type_init(q35_register); |