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Commit | Line | Data |
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502a5395 | 1 | /* |
9b301794 | 2 | * QEMU Ultrasparc Sabre PCI host (PBM) |
502a5395 PB |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard | |
9625036d | 5 | * Copyright (c) 2012,2013 Artyom Tarasenko |
9b301794 | 6 | * Copyright (c) 2018 Mark Cave-Ayland |
5fafdf24 | 7 | * |
502a5395 PB |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | */ | |
80b3ada7 | 26 | |
97d5408f | 27 | #include "qemu/osdep.h" |
83c9f4ca PB |
28 | #include "hw/sysbus.h" |
29 | #include "hw/pci/pci.h" | |
30 | #include "hw/pci/pci_host.h" | |
31 | #include "hw/pci/pci_bridge.h" | |
32 | #include "hw/pci/pci_bus.h" | |
ffd9589e | 33 | #include "hw/pci-bridge/simba.h" |
9b301794 | 34 | #include "hw/pci-host/sabre.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
022c62cb | 36 | #include "exec/address-spaces.h" |
03dd024f | 37 | #include "qemu/log.h" |
0b8fa32f | 38 | #include "qemu/module.h" |
bfec08b5 | 39 | #include "trace.h" |
a94fd955 | 40 | |
930f3fe1 BS |
41 | /* |
42 | * Chipset docs: | |
43 | * PBM: "UltraSPARC IIi User's Manual", | |
44 | * http://www.sun.com/processors/manuals/805-0087.pdf | |
930f3fe1 BS |
45 | */ |
46 | ||
95819af0 BS |
47 | #define PBM_PCI_IMR_MASK 0x7fffffff |
48 | #define PBM_PCI_IMR_ENABLED 0x80000000 | |
49 | ||
af23906d PM |
50 | #define POR (1U << 31) |
51 | #define SOFT_POR (1U << 30) | |
52 | #define SOFT_XIR (1U << 29) | |
53 | #define BTN_POR (1U << 28) | |
54 | #define BTN_XIR (1U << 27) | |
95819af0 BS |
55 | #define RESET_MASK 0xf8000000 |
56 | #define RESET_WCMASK 0x98000000 | |
57 | #define RESET_WMASK 0x60000000 | |
58 | ||
9625036d | 59 | #define NO_IRQ_REQUEST (MAX_IVEC + 1) |
361dea40 | 60 | |
b14dcaf4 | 61 | static inline void sabre_set_request(SabreState *s, unsigned int irq_num) |
9625036d | 62 | { |
bfec08b5 | 63 | trace_sabre_set_request(irq_num); |
9625036d AT |
64 | s->irq_request = irq_num; |
65 | qemu_set_irq(s->ivec_irqs[irq_num], 1); | |
66 | } | |
67 | ||
b14dcaf4 | 68 | static inline void sabre_check_irqs(SabreState *s) |
9625036d | 69 | { |
9625036d AT |
70 | unsigned int i; |
71 | ||
72 | /* Previous request is not acknowledged, resubmit */ | |
73 | if (s->irq_request != NO_IRQ_REQUEST) { | |
fe984c7d | 74 | sabre_set_request(s, s->irq_request); |
9625036d AT |
75 | return; |
76 | } | |
77 | /* no request pending */ | |
78 | if (s->pci_irq_in == 0ULL) { | |
79 | return; | |
80 | } | |
81 | for (i = 0; i < 32; i++) { | |
82 | if (s->pci_irq_in & (1ULL << i)) { | |
83 | if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 84 | sabre_set_request(s, i); |
9625036d AT |
85 | return; |
86 | } | |
87 | } | |
88 | } | |
89 | for (i = 32; i < 64; i++) { | |
90 | if (s->pci_irq_in & (1ULL << i)) { | |
91 | if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 92 | sabre_set_request(s, i); |
9625036d AT |
93 | break; |
94 | } | |
95 | } | |
96 | } | |
97 | } | |
98 | ||
b14dcaf4 | 99 | static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) |
9625036d | 100 | { |
bfec08b5 | 101 | trace_sabre_clear_request(irq_num); |
9625036d AT |
102 | qemu_set_irq(s->ivec_irqs[irq_num], 0); |
103 | s->irq_request = NO_IRQ_REQUEST; | |
104 | } | |
94d19914 | 105 | |
fe984c7d | 106 | static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
ae74bbe7 MCA |
107 | { |
108 | IOMMUState *is = opaque; | |
109 | ||
110 | return &is->iommu_as; | |
111 | } | |
112 | ||
fe984c7d | 113 | static void sabre_config_write(void *opaque, hwaddr addr, |
3812ed0b | 114 | uint64_t val, unsigned size) |
502a5395 | 115 | { |
b14dcaf4 | 116 | SabreState *s = opaque; |
95819af0 | 117 | |
bfec08b5 | 118 | trace_sabre_config_write(addr, val); |
95819af0 BS |
119 | |
120 | switch (addr & 0xffff) { | |
121 | case 0x30 ... 0x4f: /* DMA error registers */ | |
122 | /* XXX: not implemented yet */ | |
123 | break; | |
95819af0 BS |
124 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
125 | if (addr & 4) { | |
9625036d AT |
126 | unsigned int ino = (addr & 0x3f) >> 3; |
127 | s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; | |
128 | s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; | |
129 | if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { | |
fe984c7d | 130 | sabre_clear_request(s, ino); |
9625036d | 131 | } |
fe984c7d | 132 | sabre_check_irqs(s); |
95819af0 BS |
133 | } |
134 | break; | |
de739df8 | 135 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
361dea40 | 136 | if (addr & 4) { |
9625036d AT |
137 | unsigned int ino = ((addr & 0xff) >> 3); |
138 | s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; | |
139 | s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; | |
140 | if ((s->irq_request == (ino | 0x20)) | |
141 | && !(val & ~PBM_PCI_IMR_MASK)) { | |
fe984c7d | 142 | sabre_clear_request(s, ino | 0x20); |
9625036d | 143 | } |
fe984c7d | 144 | sabre_check_irqs(s); |
361dea40 BS |
145 | } |
146 | break; | |
9625036d | 147 | case 0x1400 ... 0x14ff: /* PCI interrupt clear */ |
94d19914 | 148 | if (addr & 4) { |
9625036d AT |
149 | unsigned int ino = (addr & 0xff) >> 5; |
150 | if ((s->irq_request / 4) == ino) { | |
fe984c7d MCA |
151 | sabre_clear_request(s, s->irq_request); |
152 | sabre_check_irqs(s); | |
9625036d | 153 | } |
94d19914 AT |
154 | } |
155 | break; | |
156 | case 0x1800 ... 0x1860: /* OBIO interrupt clear */ | |
157 | if (addr & 4) { | |
9625036d AT |
158 | unsigned int ino = ((addr & 0xff) >> 3) | 0x20; |
159 | if (s->irq_request == ino) { | |
fe984c7d MCA |
160 | sabre_clear_request(s, ino); |
161 | sabre_check_irqs(s); | |
9625036d | 162 | } |
94d19914 AT |
163 | } |
164 | break; | |
95819af0 BS |
165 | case 0x2000 ... 0x202f: /* PCI control */ |
166 | s->pci_control[(addr & 0x3f) >> 2] = val; | |
167 | break; | |
168 | case 0xf020 ... 0xf027: /* Reset control */ | |
169 | if (addr & 4) { | |
170 | val &= RESET_MASK; | |
171 | s->reset_control &= ~(val & RESET_WCMASK); | |
172 | s->reset_control |= val & RESET_WMASK; | |
173 | if (val & SOFT_POR) { | |
9c0afd0e | 174 | s->nr_resets = 0; |
cf83f140 | 175 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
95819af0 | 176 | } else if (val & SOFT_XIR) { |
cf83f140 | 177 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
95819af0 BS |
178 | } |
179 | } | |
180 | break; | |
181 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ | |
182 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ | |
183 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ | |
184 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ | |
185 | /* we don't care */ | |
502a5395 | 186 | default: |
f930d07e | 187 | break; |
502a5395 PB |
188 | } |
189 | } | |
190 | ||
fe984c7d | 191 | static uint64_t sabre_config_read(void *opaque, |
a8170e5e | 192 | hwaddr addr, unsigned size) |
502a5395 | 193 | { |
b14dcaf4 | 194 | SabreState *s = opaque; |
502a5395 PB |
195 | uint32_t val; |
196 | ||
95819af0 BS |
197 | switch (addr & 0xffff) { |
198 | case 0x30 ... 0x4f: /* DMA error registers */ | |
199 | val = 0; | |
200 | /* XXX: not implemented yet */ | |
201 | break; | |
95819af0 BS |
202 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
203 | if (addr & 4) { | |
204 | val = s->pci_irq_map[(addr & 0x3f) >> 3]; | |
205 | } else { | |
206 | val = 0; | |
207 | } | |
208 | break; | |
de739df8 | 209 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
361dea40 BS |
210 | if (addr & 4) { |
211 | val = s->obio_irq_map[(addr & 0xff) >> 3]; | |
212 | } else { | |
213 | val = 0; | |
214 | } | |
215 | break; | |
de739df8 MCA |
216 | case 0x1080 ... 0x108f: /* PCI bus error */ |
217 | if (addr & 4) { | |
218 | val = s->pci_err_irq_map[(addr & 0xf) >> 3]; | |
219 | } else { | |
220 | val = 0; | |
221 | } | |
222 | break; | |
95819af0 BS |
223 | case 0x2000 ... 0x202f: /* PCI control */ |
224 | val = s->pci_control[(addr & 0x3f) >> 2]; | |
225 | break; | |
226 | case 0xf020 ... 0xf027: /* Reset control */ | |
227 | if (addr & 4) { | |
228 | val = s->reset_control; | |
229 | } else { | |
230 | val = 0; | |
231 | } | |
232 | break; | |
233 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ | |
234 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ | |
235 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ | |
236 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ | |
237 | /* we don't care */ | |
502a5395 | 238 | default: |
f930d07e BS |
239 | val = 0; |
240 | break; | |
502a5395 | 241 | } |
bfec08b5 | 242 | trace_sabre_config_read(addr, val); |
95819af0 | 243 | |
502a5395 PB |
244 | return val; |
245 | } | |
246 | ||
fe984c7d MCA |
247 | static const MemoryRegionOps sabre_config_ops = { |
248 | .read = sabre_config_read, | |
249 | .write = sabre_config_write, | |
b2f9005a | 250 | .endianness = DEVICE_BIG_ENDIAN, |
502a5395 PB |
251 | }; |
252 | ||
fe984c7d MCA |
253 | static void sabre_pci_config_write(void *opaque, hwaddr addr, |
254 | uint64_t val, unsigned size) | |
5a5d4a76 | 255 | { |
b14dcaf4 | 256 | SabreState *s = opaque; |
2b8fbcd8 | 257 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
63e6f31d | 258 | |
bfec08b5 | 259 | trace_sabre_pci_config_write(addr, val); |
2b8fbcd8 | 260 | pci_data_write(phb->bus, addr, val, size); |
5a5d4a76 BS |
261 | } |
262 | ||
fe984c7d MCA |
263 | static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, |
264 | unsigned size) | |
5a5d4a76 BS |
265 | { |
266 | uint32_t ret; | |
b14dcaf4 | 267 | SabreState *s = opaque; |
2b8fbcd8 | 268 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
5a5d4a76 | 269 | |
2b8fbcd8 | 270 | ret = pci_data_read(phb->bus, addr, size); |
bfec08b5 | 271 | trace_sabre_pci_config_read(addr, ret); |
5a5d4a76 BS |
272 | return ret; |
273 | } | |
274 | ||
fe984c7d MCA |
275 | /* The sabre host has an IRQ line for each IRQ line of each slot. */ |
276 | static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) | |
502a5395 | 277 | { |
6864fa38 MCA |
278 | /* Return the irq as swizzled by the PBM */ |
279 | return irq_num; | |
80b3ada7 PB |
280 | } |
281 | ||
90302ada | 282 | static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) |
80b3ada7 | 283 | { |
d9e4d682 MCA |
284 | /* The on-board devices have fixed (legacy) OBIO intnos */ |
285 | switch (PCI_SLOT(pci_dev->devfn)) { | |
286 | case 1: | |
287 | /* Onboard NIC */ | |
a5546222 | 288 | return OBIO_NIC_IRQ; |
d9e4d682 MCA |
289 | case 3: |
290 | /* Onboard IDE */ | |
a5546222 | 291 | return OBIO_HDD_IRQ; |
d9e4d682 MCA |
292 | default: |
293 | /* Normal intno, fall through */ | |
294 | break; | |
6864fa38 | 295 | } |
6864fa38 | 296 | |
d9e4d682 MCA |
297 | return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; |
298 | } | |
6864fa38 | 299 | |
90302ada | 300 | static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) |
d9e4d682 MCA |
301 | { |
302 | return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; | |
d2b59317 PB |
303 | } |
304 | ||
fe984c7d | 305 | static void pci_sabre_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 306 | { |
b14dcaf4 | 307 | SabreState *s = opaque; |
5d4e84c8 | 308 | |
bfec08b5 MCA |
309 | trace_sabre_pci_set_irq(irq_num, level); |
310 | ||
80b3ada7 | 311 | /* PCI IRQ map onto the first 32 INO. */ |
95819af0 | 312 | if (irq_num < 32) { |
9625036d AT |
313 | if (level) { |
314 | s->pci_irq_in |= 1ULL << irq_num; | |
315 | if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { | |
fe984c7d | 316 | sabre_set_request(s, irq_num); |
9625036d | 317 | } |
361dea40 | 318 | } else { |
9625036d | 319 | s->pci_irq_in &= ~(1ULL << irq_num); |
361dea40 BS |
320 | } |
321 | } else { | |
9625036d AT |
322 | /* OBIO IRQ map onto the next 32 INO. */ |
323 | if (level) { | |
bfec08b5 | 324 | trace_sabre_pci_set_obio_irq(irq_num, level); |
9625036d AT |
325 | s->pci_irq_in |= 1ULL << irq_num; |
326 | if ((s->irq_request == NO_IRQ_REQUEST) | |
327 | && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { | |
fe984c7d | 328 | sabre_set_request(s, irq_num); |
9625036d | 329 | } |
95819af0 | 330 | } else { |
9625036d | 331 | s->pci_irq_in &= ~(1ULL << irq_num); |
95819af0 BS |
332 | } |
333 | } | |
502a5395 PB |
334 | } |
335 | ||
fe984c7d | 336 | static void sabre_reset(DeviceState *d) |
72f44c8c | 337 | { |
b14dcaf4 | 338 | SabreState *s = SABRE_DEVICE(d); |
33c5eb02 MCA |
339 | PCIDevice *pci_dev; |
340 | unsigned int i; | |
341 | uint16_t cmd; | |
72f44c8c | 342 | |
95819af0 BS |
343 | for (i = 0; i < 8; i++) { |
344 | s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; | |
345 | } | |
d1d80055 AT |
346 | for (i = 0; i < 32; i++) { |
347 | s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; | |
348 | } | |
95819af0 | 349 | |
9625036d AT |
350 | s->irq_request = NO_IRQ_REQUEST; |
351 | s->pci_irq_in = 0ULL; | |
352 | ||
9c0afd0e | 353 | if (s->nr_resets++ == 0) { |
95819af0 BS |
354 | /* Power on reset */ |
355 | s->reset_control = POR; | |
356 | } | |
33c5eb02 MCA |
357 | |
358 | /* As this is the busA PCI bridge which contains the on-board devices | |
359 | * attached to the ebus, ensure that we initially allow IO transactions | |
360 | * so that we get the early serial console until OpenBIOS can properly | |
361 | * configure the PCI bridge itself */ | |
362 | pci_dev = PCI_DEVICE(s->bridgeA); | |
363 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); | |
364 | pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); | |
365 | pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); | |
95819af0 BS |
366 | } |
367 | ||
3812ed0b | 368 | static const MemoryRegionOps pci_config_ops = { |
fe984c7d MCA |
369 | .read = sabre_pci_config_read, |
370 | .write = sabre_pci_config_write, | |
b2f9005a | 371 | .endianness = DEVICE_LITTLE_ENDIAN, |
3812ed0b AK |
372 | }; |
373 | ||
fe984c7d | 374 | static void sabre_realize(DeviceState *dev, Error **errp) |
95819af0 | 375 | { |
b14dcaf4 | 376 | SabreState *s = SABRE_DEVICE(dev); |
cacd0580 MCA |
377 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
378 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); | |
68f79994 | 379 | PCIDevice *pci_dev; |
502a5395 | 380 | |
9b301794 | 381 | /* sabre_config */ |
cacd0580 | 382 | sysbus_mmio_map(sbd, 0, s->special_base); |
d63baf92 | 383 | /* PCI configuration space */ |
cacd0580 | 384 | sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); |
72f44c8c | 385 | /* pci_ioport */ |
cacd0580 | 386 | sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); |
d63baf92 | 387 | |
cacd0580 MCA |
388 | memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); |
389 | memory_region_add_subregion(get_system_memory(), s->mem_base, | |
390 | &s->pci_mmio); | |
391 | ||
acc95bc8 | 392 | phb->bus = pci_register_root_bus(dev, "pci", |
fe984c7d | 393 | pci_sabre_set_irq, pci_sabre_map_irq, s, |
acc95bc8 MT |
394 | &s->pci_mmio, |
395 | &s->pci_ioport, | |
396 | 0, 32, TYPE_PCI_BUS); | |
f69539b1 | 397 | |
8fb28035 | 398 | pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); |
d63baf92 | 399 | |
fe984c7d | 400 | /* IOMMU */ |
9b301794 | 401 | memory_region_add_subregion_overlap(&s->sabre_config, 0x200, |
aea5b071 | 402 | sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); |
fe984c7d | 403 | pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); |
ae74bbe7 | 404 | |
72f44c8c | 405 | /* APB secondary busses */ |
2b8fbcd8 | 406 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, |
90302ada | 407 | TYPE_SIMBA_PCI_BRIDGE); |
cacd0580 | 408 | s->bridgeB = PCI_BRIDGE(pci_dev); |
90302ada | 409 | pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); |
68f79994 | 410 | qdev_init_nofail(&pci_dev->qdev); |
68f79994 | 411 | |
2b8fbcd8 | 412 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, |
90302ada | 413 | TYPE_SIMBA_PCI_BRIDGE); |
cacd0580 | 414 | s->bridgeA = PCI_BRIDGE(pci_dev); |
90302ada | 415 | pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); |
68f79994 | 416 | qdev_init_nofail(&pci_dev->qdev); |
95819af0 BS |
417 | } |
418 | ||
fe984c7d | 419 | static void sabre_init(Object *obj) |
95819af0 | 420 | { |
b14dcaf4 | 421 | SabreState *s = SABRE_DEVICE(obj); |
cacd0580 | 422 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
95819af0 | 423 | unsigned int i; |
72f44c8c | 424 | |
95819af0 BS |
425 | for (i = 0; i < 8; i++) { |
426 | s->pci_irq_map[i] = (0x1f << 6) | (i << 2); | |
427 | } | |
de739df8 MCA |
428 | for (i = 0; i < 2; i++) { |
429 | s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; | |
430 | } | |
d1d80055 AT |
431 | for (i = 0; i < 32; i++) { |
432 | s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; | |
433 | } | |
fe984c7d | 434 | qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); |
2a4d6af5 | 435 | qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); |
9625036d AT |
436 | s->irq_request = NO_IRQ_REQUEST; |
437 | s->pci_irq_in = 0ULL; | |
95819af0 | 438 | |
aea5b071 MCA |
439 | /* IOMMU */ |
440 | object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, | |
441 | (Object **) &s->iommu, | |
442 | qdev_prop_allow_set_link_before_realize, | |
443 | 0, NULL); | |
444 | ||
9b301794 MCA |
445 | /* sabre_config */ |
446 | memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, | |
447 | "sabre-config", 0x10000); | |
d63baf92 | 448 | /* at region 0 */ |
9b301794 | 449 | sysbus_init_mmio(sbd, &s->sabre_config); |
d63baf92 | 450 | |
40c5dce9 | 451 | memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, |
9b301794 | 452 | "sabre-pci-config", 0x1000000); |
d63baf92 | 453 | /* at region 1 */ |
b26f4419 | 454 | sysbus_init_mmio(sbd, &s->pci_config); |
d63baf92 IK |
455 | |
456 | /* pci_ioport */ | |
9b301794 MCA |
457 | memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", |
458 | 0x1000000); | |
6864fa38 | 459 | |
d63baf92 | 460 | /* at region 2 */ |
b26f4419 | 461 | sysbus_init_mmio(sbd, &s->pci_ioport); |
72f44c8c | 462 | } |
502a5395 | 463 | |
5560c58a | 464 | static void sabre_pci_realize(PCIDevice *d, Error **errp) |
72f44c8c | 465 | { |
9fe52c7f BS |
466 | pci_set_word(d->config + PCI_COMMAND, |
467 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
468 | pci_set_word(d->config + PCI_STATUS, | |
469 | PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | | |
470 | PCI_STATUS_DEVSEL_MEDIUM); | |
72f44c8c | 471 | } |
80b3ada7 | 472 | |
5560c58a | 473 | static void sabre_pci_class_init(ObjectClass *klass, void *data) |
40021f08 AL |
474 | { |
475 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 476 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 477 | |
5560c58a | 478 | k->realize = sabre_pci_realize; |
40021f08 AL |
479 | k->vendor_id = PCI_VENDOR_ID_SUN; |
480 | k->device_id = PCI_DEVICE_ID_SUN_SABRE; | |
481 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
482 | /* |
483 | * PCI-facing part of the host bridge, not usable without the | |
484 | * host-facing part, which can't be device_add'ed, yet. | |
485 | */ | |
e90f2a8c | 486 | dc->user_creatable = false; |
40021f08 AL |
487 | } |
488 | ||
5560c58a | 489 | static const TypeInfo sabre_pci_info = { |
8fb28035 | 490 | .name = TYPE_SABRE_PCI_DEVICE, |
39bffca2 | 491 | .parent = TYPE_PCI_DEVICE, |
8fb28035 | 492 | .instance_size = sizeof(SabrePCIState), |
5560c58a | 493 | .class_init = sabre_pci_class_init, |
fd3b02c8 EH |
494 | .interfaces = (InterfaceInfo[]) { |
495 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
496 | { }, | |
497 | }, | |
72f44c8c BS |
498 | }; |
499 | ||
09af820e MCA |
500 | static char *sabre_ofw_unit_address(const SysBusDevice *dev) |
501 | { | |
502 | SabreState *s = SABRE_DEVICE(dev); | |
503 | ||
504 | return g_strdup_printf("%x,%x", | |
505 | (uint32_t)((s->special_base >> 32) & 0xffffffff), | |
506 | (uint32_t)(s->special_base & 0xffffffff)); | |
507 | } | |
508 | ||
fe984c7d | 509 | static Property sabre_properties[] = { |
b14dcaf4 MCA |
510 | DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), |
511 | DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), | |
cacd0580 MCA |
512 | DEFINE_PROP_END_OF_LIST(), |
513 | }; | |
514 | ||
fe984c7d | 515 | static void sabre_class_init(ObjectClass *klass, void *data) |
999e12bb | 516 | { |
39bffca2 | 517 | DeviceClass *dc = DEVICE_CLASS(klass); |
09af820e | 518 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 519 | |
fe984c7d MCA |
520 | dc->realize = sabre_realize; |
521 | dc->reset = sabre_reset; | |
522 | dc->props = sabre_properties; | |
b26f4419 | 523 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
09af820e MCA |
524 | dc->fw_name = "pci"; |
525 | sbc->explicit_ofw_unit_address = sabre_ofw_unit_address; | |
999e12bb AL |
526 | } |
527 | ||
fe984c7d | 528 | static const TypeInfo sabre_info = { |
b14dcaf4 | 529 | .name = TYPE_SABRE, |
2b8fbcd8 | 530 | .parent = TYPE_PCI_HOST_BRIDGE, |
b14dcaf4 | 531 | .instance_size = sizeof(SabreState), |
fe984c7d MCA |
532 | .instance_init = sabre_init, |
533 | .class_init = sabre_class_init, | |
95819af0 | 534 | }; |
68f79994 | 535 | |
fe984c7d | 536 | static void sabre_register_types(void) |
72f44c8c | 537 | { |
fe984c7d | 538 | type_register_static(&sabre_info); |
5560c58a | 539 | type_register_static(&sabre_pci_info); |
502a5395 | 540 | } |
72f44c8c | 541 | |
fe984c7d | 542 | type_init(sabre_register_types) |