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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU Uninorth PCI host (for all Mac99 and newer machines) | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0b8fa32f | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/ppc/mac.h" | |
0b8fa32f | 28 | #include "qemu/module.h" |
83c9f4ca PB |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_host.h" | |
5d2eaa02 | 31 | #include "hw/pci-host/uninorth.h" |
0b0c5e90 | 32 | #include "trace.h" |
f3902383 | 33 | |
fa0be69a AG |
34 | static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
35 | ||
d2b59317 | 36 | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 37 | { |
39d97e14 | 38 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
d2b59317 PB |
39 | } |
40 | ||
5d4e84c8 | 41 | static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 42 | { |
c90c393c | 43 | UNINHostState *s = opaque; |
5d4e84c8 | 44 | |
0b0c5e90 | 45 | trace_unin_set_irq(unin_irq_line[irq_num], level); |
e7755cc1 | 46 | qemu_set_irq(s->irqs[irq_num], level); |
502a5395 PB |
47 | } |
48 | ||
d86f0e32 AG |
49 | static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) |
50 | { | |
51 | uint32_t retval; | |
52 | ||
53 | if (reg & (1u << 31)) { | |
54 | /* XXX OpenBIOS compatibility hack */ | |
55 | retval = reg | (addr & 3); | |
56 | } else if (reg & 1) { | |
57 | /* CFA1 style */ | |
58 | retval = (reg & ~7u) | (addr & 7); | |
59 | } else { | |
60 | uint32_t slot, func; | |
61 | ||
62 | /* Grab CFA0 style values */ | |
5863d374 SH |
63 | slot = ctz32(reg & 0xfffff800); |
64 | if (slot == 32) { | |
65 | slot = -1; /* XXX: should this be 0? */ | |
66 | } | |
d86f0e32 AG |
67 | func = (reg >> 8) & 7; |
68 | ||
69 | /* ... and then convert them to x86 format */ | |
70 | /* config pointer */ | |
71 | retval = (reg & (0xff - 7)) | (addr & 7); | |
72 | /* slot */ | |
73 | retval |= slot << 11; | |
74 | /* fn */ | |
75 | retval |= func << 8; | |
76 | } | |
77 | ||
0b0c5e90 | 78 | trace_unin_get_config_reg(reg, addr, retval); |
d86f0e32 AG |
79 | |
80 | return retval; | |
81 | } | |
82 | ||
a8170e5e | 83 | static void unin_data_write(void *opaque, hwaddr addr, |
d0ed8076 | 84 | uint64_t val, unsigned len) |
d86f0e32 | 85 | { |
c90c393c | 86 | UNINHostState *s = opaque; |
67c332fd | 87 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
0b0c5e90 | 88 | trace_unin_data_write(addr, len, val); |
67c332fd AF |
89 | pci_data_write(phb->bus, |
90 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 AG |
91 | val, len); |
92 | } | |
93 | ||
a8170e5e | 94 | static uint64_t unin_data_read(void *opaque, hwaddr addr, |
d0ed8076 | 95 | unsigned len) |
d86f0e32 | 96 | { |
c90c393c | 97 | UNINHostState *s = opaque; |
67c332fd | 98 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
d86f0e32 AG |
99 | uint32_t val; |
100 | ||
67c332fd AF |
101 | val = pci_data_read(phb->bus, |
102 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 | 103 | len); |
0b0c5e90 | 104 | trace_unin_data_read(addr, len, val); |
d86f0e32 AG |
105 | return val; |
106 | } | |
107 | ||
d0ed8076 AK |
108 | static const MemoryRegionOps unin_data_ops = { |
109 | .read = unin_data_read, | |
110 | .write = unin_data_write, | |
111 | .endianness = DEVICE_LITTLE_ENDIAN, | |
112 | }; | |
113 | ||
c90c393c | 114 | static void pci_unin_init_irqs(UNINHostState *s) |
e7755cc1 MCA |
115 | { |
116 | int i; | |
117 | ||
118 | for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { | |
119 | s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]); | |
120 | } | |
121 | } | |
122 | ||
03756c84 MCA |
123 | static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev) |
124 | { | |
125 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); | |
126 | ||
127 | return g_strdup_printf("%x", s->ofw_addr); | |
128 | } | |
129 | ||
32cde615 MCA |
130 | static void pci_unin_main_realize(DeviceState *dev, Error **errp) |
131 | { | |
c90c393c | 132 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); |
32cde615 MCA |
133 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
134 | ||
135 | h->bus = pci_register_root_bus(dev, NULL, | |
136 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 137 | s, |
32cde615 | 138 | &s->pci_mmio, |
e226efbb | 139 | &s->pci_io, |
32cde615 MCA |
140 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
141 | ||
c1d66d37 | 142 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); |
e7755cc1 | 143 | pci_unin_init_irqs(s); |
32cde615 MCA |
144 | |
145 | /* DEC 21154 bridge */ | |
146 | #if 0 | |
147 | /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */ | |
148 | pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154"); | |
149 | #endif | |
150 | } | |
151 | ||
02034599 | 152 | static void pci_unin_main_init(Object *obj) |
502a5395 | 153 | { |
c90c393c | 154 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); |
02034599 MCA |
155 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
156 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
502a5395 PB |
157 | |
158 | /* Use values found on a real PowerMac */ | |
159 | /* Uninorth main bus */ | |
40c5dce9 | 160 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 161 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 162 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
163 | "unin-pci-conf-data", 0x1000); |
164 | ||
165 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
166 | 0x100000000ULL); | |
e226efbb MCA |
167 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
168 | "unin-pci-isa-mmio", 0x00800000); | |
132e9906 | 169 | |
7b19318b MCA |
170 | memory_region_init_alias(&s->pci_hole, OBJECT(s), |
171 | "unin-pci-hole", &s->pci_mmio, | |
172 | 0x80000000ULL, 0x10000000ULL); | |
173 | ||
e7755cc1 MCA |
174 | object_property_add_link(obj, "pic", TYPE_OPENPIC, |
175 | (Object **) &s->pic, | |
176 | qdev_prop_allow_set_link_before_realize, | |
177 | 0, NULL); | |
178 | ||
02034599 MCA |
179 | sysbus_init_mmio(sbd, &h->conf_mem); |
180 | sysbus_init_mmio(sbd, &h->data_mem); | |
7b19318b | 181 | sysbus_init_mmio(sbd, &s->pci_hole); |
e226efbb | 182 | sysbus_init_mmio(sbd, &s->pci_io); |
2e29bd04 BS |
183 | } |
184 | ||
32cde615 MCA |
185 | static void pci_u3_agp_realize(DeviceState *dev, Error **errp) |
186 | { | |
c90c393c | 187 | UNINHostState *s = U3_AGP_HOST_BRIDGE(dev); |
32cde615 MCA |
188 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
189 | ||
190 | h->bus = pci_register_root_bus(dev, NULL, | |
191 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 192 | s, |
32cde615 | 193 | &s->pci_mmio, |
e226efbb | 194 | &s->pci_io, |
32cde615 MCA |
195 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
196 | ||
197 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); | |
e7755cc1 | 198 | pci_unin_init_irqs(s); |
32cde615 MCA |
199 | } |
200 | ||
02034599 | 201 | static void pci_u3_agp_init(Object *obj) |
0f921197 | 202 | { |
c90c393c | 203 | UNINHostState *s = U3_AGP_HOST_BRIDGE(obj); |
02034599 MCA |
204 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
205 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
0f921197 AG |
206 | |
207 | /* Uninorth U3 AGP bus */ | |
40c5dce9 | 208 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 209 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 210 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
211 | "unin-pci-conf-data", 0x1000); |
212 | ||
213 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
214 | 0x100000000ULL); | |
e226efbb MCA |
215 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
216 | "unin-pci-isa-mmio", 0x00800000); | |
132e9906 | 217 | |
8ce3f743 MCA |
218 | memory_region_init_alias(&s->pci_hole, OBJECT(s), |
219 | "unin-pci-hole", &s->pci_mmio, | |
220 | 0x80000000ULL, 0x70000000ULL); | |
221 | ||
e7755cc1 MCA |
222 | object_property_add_link(obj, "pic", TYPE_OPENPIC, |
223 | (Object **) &s->pic, | |
224 | qdev_prop_allow_set_link_before_realize, | |
225 | 0, NULL); | |
226 | ||
02034599 MCA |
227 | sysbus_init_mmio(sbd, &h->conf_mem); |
228 | sysbus_init_mmio(sbd, &h->data_mem); | |
8ce3f743 | 229 | sysbus_init_mmio(sbd, &s->pci_hole); |
e226efbb | 230 | sysbus_init_mmio(sbd, &s->pci_io); |
0f921197 AG |
231 | } |
232 | ||
32cde615 MCA |
233 | static void pci_unin_agp_realize(DeviceState *dev, Error **errp) |
234 | { | |
c90c393c | 235 | UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); |
32cde615 MCA |
236 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
237 | ||
238 | h->bus = pci_register_root_bus(dev, NULL, | |
239 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 240 | s, |
32cde615 | 241 | &s->pci_mmio, |
e226efbb | 242 | &s->pci_io, |
32cde615 | 243 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
c1d66d37 MCA |
244 | |
245 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); | |
e7755cc1 | 246 | pci_unin_init_irqs(s); |
32cde615 MCA |
247 | } |
248 | ||
02034599 | 249 | static void pci_unin_agp_init(Object *obj) |
2e29bd04 | 250 | { |
c90c393c | 251 | UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); |
02034599 MCA |
252 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
253 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
254 | |
255 | /* Uninorth AGP bus */ | |
40c5dce9 | 256 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 257 | obj, "unin-agp-conf-idx", 0x1000); |
40c5dce9 | 258 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 259 | obj, "unin-agp-conf-data", 0x1000); |
e7755cc1 MCA |
260 | |
261 | object_property_add_link(obj, "pic", TYPE_OPENPIC, | |
262 | (Object **) &s->pic, | |
263 | qdev_prop_allow_set_link_before_realize, | |
264 | 0, NULL); | |
265 | ||
02034599 MCA |
266 | sysbus_init_mmio(sbd, &h->conf_mem); |
267 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
268 | } |
269 | ||
1ff861d2 MCA |
270 | static void pci_unin_internal_realize(DeviceState *dev, Error **errp) |
271 | { | |
c90c393c | 272 | UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); |
1ff861d2 MCA |
273 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
274 | ||
275 | h->bus = pci_register_root_bus(dev, NULL, | |
276 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 277 | s, |
1ff861d2 | 278 | &s->pci_mmio, |
e226efbb | 279 | &s->pci_io, |
1ff861d2 MCA |
280 | PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); |
281 | ||
282 | pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); | |
e7755cc1 | 283 | pci_unin_init_irqs(s); |
1ff861d2 MCA |
284 | } |
285 | ||
02034599 | 286 | static void pci_unin_internal_init(Object *obj) |
2e29bd04 | 287 | { |
c90c393c | 288 | UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); |
02034599 MCA |
289 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
290 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
291 | |
292 | /* Uninorth internal bus */ | |
40c5dce9 | 293 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 294 | obj, "unin-pci-conf-idx", 0x1000); |
40c5dce9 | 295 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 296 | obj, "unin-pci-conf-data", 0x1000); |
e7755cc1 MCA |
297 | |
298 | object_property_add_link(obj, "pic", TYPE_OPENPIC, | |
299 | (Object **) &s->pic, | |
300 | qdev_prop_allow_set_link_before_realize, | |
301 | 0, NULL); | |
302 | ||
02034599 MCA |
303 | sysbus_init_mmio(sbd, &h->conf_mem); |
304 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
305 | } |
306 | ||
9af21dbe | 307 | static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 308 | { |
4d309c96 MCA |
309 | /* cache_line_size */ |
310 | d->config[0x0C] = 0x08; | |
311 | /* latency_timer */ | |
312 | d->config[0x0D] = 0x10; | |
313 | /* capabilities_pointer */ | |
314 | d->config[0x34] = 0x00; | |
4d309c96 | 315 | |
98ae3b27 JA |
316 | /* |
317 | * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI | |
318 | * memory space with base 0x80000000, size 0x10000000 for Apple's | |
319 | * AppleMacRiscPCI driver | |
320 | */ | |
321 | d->config[0x48] = 0x0; | |
322 | d->config[0x49] = 0x0; | |
323 | d->config[0x4a] = 0x0; | |
324 | d->config[0x4b] = 0x1; | |
2e29bd04 | 325 | } |
502a5395 | 326 | |
c1d66d37 MCA |
327 | static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) |
328 | { | |
329 | /* cache_line_size */ | |
330 | d->config[0x0C] = 0x08; | |
331 | /* latency_timer */ | |
332 | d->config[0x0D] = 0x10; | |
333 | /* capabilities_pointer | |
334 | d->config[0x34] = 0x80; */ | |
335 | } | |
336 | ||
9af21dbe | 337 | static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) |
0f921197 | 338 | { |
0f921197 AG |
339 | /* cache line size */ |
340 | d->config[0x0C] = 0x08; | |
341 | /* latency timer */ | |
342 | d->config[0x0D] = 0x10; | |
0f921197 AG |
343 | } |
344 | ||
9af21dbe | 345 | static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 346 | { |
4d309c96 MCA |
347 | /* cache_line_size */ |
348 | d->config[0x0C] = 0x08; | |
349 | /* latency_timer */ | |
350 | d->config[0x0D] = 0x10; | |
351 | /* capabilities_pointer */ | |
352 | d->config[0x34] = 0x00; | |
2e29bd04 BS |
353 | } |
354 | ||
40021f08 AL |
355 | static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) |
356 | { | |
357 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 358 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 359 | |
9af21dbe | 360 | k->realize = unin_main_pci_host_realize; |
40021f08 AL |
361 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
362 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; | |
363 | k->revision = 0x00; | |
364 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
365 | /* |
366 | * PCI-facing part of the host bridge, not usable without the | |
367 | * host-facing part, which can't be device_add'ed, yet. | |
368 | */ | |
e90f2a8c | 369 | dc->user_creatable = false; |
40021f08 AL |
370 | } |
371 | ||
4240abff | 372 | static const TypeInfo unin_main_pci_host_info = { |
40021f08 | 373 | .name = "uni-north-pci", |
39bffca2 AL |
374 | .parent = TYPE_PCI_DEVICE, |
375 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 376 | .class_init = unin_main_pci_host_class_init, |
fd3b02c8 EH |
377 | .interfaces = (InterfaceInfo[]) { |
378 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
379 | { }, | |
380 | }, | |
2e29bd04 BS |
381 | }; |
382 | ||
40021f08 AL |
383 | static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) |
384 | { | |
385 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 386 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 387 | |
9af21dbe | 388 | k->realize = u3_agp_pci_host_realize; |
40021f08 AL |
389 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
390 | k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; | |
391 | k->revision = 0x00; | |
392 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
393 | /* |
394 | * PCI-facing part of the host bridge, not usable without the | |
395 | * host-facing part, which can't be device_add'ed, yet. | |
396 | */ | |
e90f2a8c | 397 | dc->user_creatable = false; |
40021f08 AL |
398 | } |
399 | ||
4240abff | 400 | static const TypeInfo u3_agp_pci_host_info = { |
40021f08 | 401 | .name = "u3-agp", |
39bffca2 AL |
402 | .parent = TYPE_PCI_DEVICE, |
403 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 404 | .class_init = u3_agp_pci_host_class_init, |
fd3b02c8 EH |
405 | .interfaces = (InterfaceInfo[]) { |
406 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
407 | { }, | |
408 | }, | |
0f921197 AG |
409 | }; |
410 | ||
40021f08 AL |
411 | static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) |
412 | { | |
413 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 414 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 415 | |
9af21dbe | 416 | k->realize = unin_agp_pci_host_realize; |
40021f08 AL |
417 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
418 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; | |
419 | k->revision = 0x00; | |
420 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
421 | /* |
422 | * PCI-facing part of the host bridge, not usable without the | |
423 | * host-facing part, which can't be device_add'ed, yet. | |
424 | */ | |
e90f2a8c | 425 | dc->user_creatable = false; |
40021f08 AL |
426 | } |
427 | ||
4240abff | 428 | static const TypeInfo unin_agp_pci_host_info = { |
40021f08 | 429 | .name = "uni-north-agp", |
39bffca2 AL |
430 | .parent = TYPE_PCI_DEVICE, |
431 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 432 | .class_init = unin_agp_pci_host_class_init, |
fd3b02c8 EH |
433 | .interfaces = (InterfaceInfo[]) { |
434 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
435 | { }, | |
436 | }, | |
2e29bd04 BS |
437 | }; |
438 | ||
40021f08 AL |
439 | static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) |
440 | { | |
441 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 442 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 443 | |
9af21dbe | 444 | k->realize = unin_internal_pci_host_realize; |
40021f08 AL |
445 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
446 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; | |
447 | k->revision = 0x00; | |
448 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
449 | /* |
450 | * PCI-facing part of the host bridge, not usable without the | |
451 | * host-facing part, which can't be device_add'ed, yet. | |
452 | */ | |
e90f2a8c | 453 | dc->user_creatable = false; |
40021f08 AL |
454 | } |
455 | ||
4240abff | 456 | static const TypeInfo unin_internal_pci_host_info = { |
40021f08 | 457 | .name = "uni-north-internal-pci", |
39bffca2 AL |
458 | .parent = TYPE_PCI_DEVICE, |
459 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 460 | .class_init = unin_internal_pci_host_class_init, |
fd3b02c8 EH |
461 | .interfaces = (InterfaceInfo[]) { |
462 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
463 | { }, | |
464 | }, | |
2e29bd04 BS |
465 | }; |
466 | ||
03756c84 MCA |
467 | static Property pci_unin_main_pci_host_props[] = { |
468 | DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1), | |
469 | DEFINE_PROP_END_OF_LIST() | |
470 | }; | |
471 | ||
999e12bb AL |
472 | static void pci_unin_main_class_init(ObjectClass *klass, void *data) |
473 | { | |
1d16f86a | 474 | DeviceClass *dc = DEVICE_CLASS(klass); |
03756c84 | 475 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 476 | |
32cde615 | 477 | dc->realize = pci_unin_main_realize; |
03756c84 | 478 | dc->props = pci_unin_main_pci_host_props; |
1d16f86a | 479 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
03756c84 MCA |
480 | dc->fw_name = "pci"; |
481 | sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address; | |
999e12bb AL |
482 | } |
483 | ||
4240abff | 484 | static const TypeInfo pci_unin_main_info = { |
57fd7b7f | 485 | .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, |
8558d942 | 486 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 487 | .instance_size = sizeof(UNINHostState), |
02034599 | 488 | .instance_init = pci_unin_main_init, |
39bffca2 | 489 | .class_init = pci_unin_main_class_init, |
70f9c987 AF |
490 | }; |
491 | ||
999e12bb AL |
492 | static void pci_u3_agp_class_init(ObjectClass *klass, void *data) |
493 | { | |
1d16f86a | 494 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 495 | |
32cde615 | 496 | dc->realize = pci_u3_agp_realize; |
1d16f86a | 497 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
498 | } |
499 | ||
4240abff | 500 | static const TypeInfo pci_u3_agp_info = { |
57fd7b7f | 501 | .name = TYPE_U3_AGP_HOST_BRIDGE, |
8558d942 | 502 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 503 | .instance_size = sizeof(UNINHostState), |
02034599 | 504 | .instance_init = pci_u3_agp_init, |
39bffca2 | 505 | .class_init = pci_u3_agp_class_init, |
70f9c987 AF |
506 | }; |
507 | ||
999e12bb AL |
508 | static void pci_unin_agp_class_init(ObjectClass *klass, void *data) |
509 | { | |
1d16f86a | 510 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 511 | |
32cde615 | 512 | dc->realize = pci_unin_agp_realize; |
1d16f86a | 513 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
514 | } |
515 | ||
4240abff | 516 | static const TypeInfo pci_unin_agp_info = { |
57fd7b7f | 517 | .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, |
8558d942 | 518 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 519 | .instance_size = sizeof(UNINHostState), |
02034599 | 520 | .instance_init = pci_unin_agp_init, |
39bffca2 | 521 | .class_init = pci_unin_agp_class_init, |
70f9c987 AF |
522 | }; |
523 | ||
999e12bb AL |
524 | static void pci_unin_internal_class_init(ObjectClass *klass, void *data) |
525 | { | |
1d16f86a | 526 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 527 | |
1ff861d2 | 528 | dc->realize = pci_unin_internal_realize; |
1d16f86a | 529 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
530 | } |
531 | ||
4240abff | 532 | static const TypeInfo pci_unin_internal_info = { |
57fd7b7f | 533 | .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, |
8558d942 | 534 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 535 | .instance_size = sizeof(UNINHostState), |
02034599 | 536 | .instance_init = pci_unin_internal_init, |
39bffca2 | 537 | .class_init = pci_unin_internal_class_init, |
70f9c987 AF |
538 | }; |
539 | ||
0662946a MCA |
540 | /* UniN device */ |
541 | static void unin_write(void *opaque, hwaddr addr, uint64_t value, | |
542 | unsigned size) | |
543 | { | |
544 | trace_unin_write(addr, value); | |
0662946a MCA |
545 | } |
546 | ||
547 | static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) | |
548 | { | |
549 | uint32_t value; | |
550 | ||
0662946a MCA |
551 | switch (addr) { |
552 | case 0: | |
45fefe7c MCA |
553 | value = UNINORTH_VERSION_10A; |
554 | break; | |
555 | default: | |
556 | value = 0; | |
0662946a MCA |
557 | } |
558 | ||
559 | trace_unin_read(addr, value); | |
560 | ||
561 | return value; | |
562 | } | |
563 | ||
564 | static const MemoryRegionOps unin_ops = { | |
565 | .read = unin_read, | |
566 | .write = unin_write, | |
567 | .endianness = DEVICE_BIG_ENDIAN, | |
568 | }; | |
569 | ||
570 | static void unin_init(Object *obj) | |
571 | { | |
572 | UNINState *s = UNI_NORTH(obj); | |
573 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
574 | ||
45fefe7c | 575 | memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000); |
0662946a MCA |
576 | |
577 | sysbus_init_mmio(sbd, &s->mem); | |
578 | } | |
579 | ||
580 | static void unin_class_init(ObjectClass *klass, void *data) | |
581 | { | |
582 | DeviceClass *dc = DEVICE_CLASS(klass); | |
583 | ||
584 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
585 | } | |
586 | ||
587 | static const TypeInfo unin_info = { | |
588 | .name = TYPE_UNI_NORTH, | |
589 | .parent = TYPE_SYS_BUS_DEVICE, | |
590 | .instance_size = sizeof(UNINState), | |
591 | .instance_init = unin_init, | |
592 | .class_init = unin_class_init, | |
593 | }; | |
594 | ||
83f7d43a | 595 | static void unin_register_types(void) |
2e29bd04 | 596 | { |
39bffca2 AL |
597 | type_register_static(&unin_main_pci_host_info); |
598 | type_register_static(&u3_agp_pci_host_info); | |
599 | type_register_static(&unin_agp_pci_host_info); | |
600 | type_register_static(&unin_internal_pci_host_info); | |
601 | ||
602 | type_register_static(&pci_unin_main_info); | |
603 | type_register_static(&pci_u3_agp_info); | |
604 | type_register_static(&pci_unin_agp_info); | |
605 | type_register_static(&pci_unin_internal_info); | |
0662946a MCA |
606 | |
607 | type_register_static(&unin_info); | |
502a5395 | 608 | } |
2e29bd04 | 609 | |
83f7d43a | 610 | type_init(unin_register_types) |