[mirror_qemu.git] / hw / pci-host / uninorth.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"

#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)

typedef struct UNINState {
    PCIHostState parent_obj;

    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ctz32(reg & 0xfffff800);
        if (slot == 32) {
            slot = -1; /* XXX: should this be 0? */
        }
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth U3 AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth internal bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(s);
    d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x10000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

#if 0
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(h->bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return h->bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(dev);
    d = U3_AGP_HOST_BRIDGE(dev);

    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(h->bus, 11 << 3, "u3-agp");

    return h->bus;
}

static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
}

static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
}

static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_main_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = u3_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_internal_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_main_init_device;
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_u3_agp_init_device;
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_agp_init_device;
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);

    sbc->init = pci_unin_internal_init_device;
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca PB	24	#include "hw/hw.h"
	25	#include "hw/ppc/mac.h"
	26	#include "hw/pci/pci.h"
	27	#include "hw/pci/pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
57fd7b7f AF	41	#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
	42	#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
	43	#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
	44	#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
	45
	46	#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
	47	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
	48	#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
	49	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
	50	#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
	51	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
	52	#define U3_AGP_HOST_BRIDGE(obj) \
	53	OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
	54
2e29bd04	55	typedef struct UNINState {
67c332fd	56	PCIHostState parent_obj;
57fd7b7f	57
46f3069c BS	58	MemoryRegion pci_mmio;
46f3069c BS	59	MemoryRegion pci_hole;
2e29bd04	60	} UNINState;
502a5395	61
d2b59317	62	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	63	{
fa0be69a AG	64	int retval;
	65	int devfn = pci_dev->devfn & 0x00FFFFFF;
	66
	67	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	68
	69	return retval;
d2b59317 PB	70	}
d2b59317 PB	71
5d4e84c8	72	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	73	{
5d4e84c8 JQ	74	qemu_irq *pic = opaque;
5d4e84c8 JQ	75
fa0be69a AG	76	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	77	unin_irq_line[irq_num], level);
	78	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	79	}
502a5395 PB	80
d86f0e32 AG	81	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	82	{
	83	uint32_t retval;
	84
	85	if (reg & (1u << 31)) {
	86	/* XXX OpenBIOS compatibility hack */
	87	retval = reg \| (addr & 3);
	88	} else if (reg & 1) {
	89	/* CFA1 style */
	90	retval = (reg & ~7u) \| (addr & 7);
	91	} else {
	92	uint32_t slot, func;
	93
	94	/* Grab CFA0 style values */
5863d374 SH	95	slot = ctz32(reg & 0xfffff800);
	96	if (slot == 32) {
	97	slot = -1; /* XXX: should this be 0? */
	98	}
d86f0e32 AG	99	func = (reg >> 8) & 7;
	100
	101	/* ... and then convert them to x86 format */
	102	/* config pointer */
	103	retval = (reg & (0xff - 7)) \| (addr & 7);
	104	/* slot */
	105	retval \|= slot << 11;
	106	/* fn */
	107	retval \|= func << 8;
	108	}
	109
	110
	111	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	112	reg, addr, retval);
	113
	114	return retval;
	115	}
	116
a8170e5e	117	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	118	uint64_t val, unsigned len)
d86f0e32	119	{
d0ed8076	120	UNINState *s = opaque;
67c332fd	121	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d0ed8076 AK	122	UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
d0ed8076 AK	123	addr, len, val);
67c332fd AF	124	pci_data_write(phb->bus,
67c332fd AF	125	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	126	val, len);
	127	}
	128
a8170e5e	129	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	130	unsigned len)
d86f0e32	131	{
d0ed8076	132	UNINState *s = opaque;
67c332fd	133	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	134	uint32_t val;
d86f0e32 AG	135
67c332fd AF	136	val = pci_data_read(phb->bus,
67c332fd AF	137	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	138	len);
d0ed8076 AK	139	UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
d0ed8076 AK	140	addr, len, val);
d86f0e32 AG	141	return val;
	142	}
	143
d0ed8076 AK	144	static const MemoryRegionOps unin_data_ops = {
	145	.read = unin_data_read,
	146	.write = unin_data_write,
	147	.endianness = DEVICE_LITTLE_ENDIAN,
	148	};
	149
81a322d4	150	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	151	{
ff452ace	152	PCIHostState *h;
502a5395 PB	153
	154	/* Use values found on a real PowerMac */
	155	/* Uninorth main bus */
8558d942	156	h = PCI_HOST_BRIDGE(dev);
502a5395	157
40c5dce9	158	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	159	dev, "pci-conf-idx", 0x1000);
40c5dce9	160	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	161	"pci-conf-data", 0x1000);
57fd7b7f AF	162	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	163	sysbus_init_mmio(dev, &h->data_mem);
2e29bd04	164
81a322d4	165	return 0;
2e29bd04 BS	166	}
2e29bd04 BS	167
d0ed8076	168
0f921197 AG	169	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	170	{
ff452ace	171	PCIHostState *h;
0f921197 AG	172
0f921197 AG	173	/* Uninorth U3 AGP bus */
8558d942	174	h = PCI_HOST_BRIDGE(dev);
0f921197	175
40c5dce9	176	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	177	dev, "pci-conf-idx", 0x1000);
40c5dce9	178	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	179	"pci-conf-data", 0x1000);
57fd7b7f AF	180	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	181	sysbus_init_mmio(dev, &h->data_mem);
0f921197	182
0f921197 AG	183	return 0;
	184	}
	185
81a322d4	186	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	187	{
ff452ace	188	PCIHostState *h;
2e29bd04 BS	189
2e29bd04 BS	190	/* Uninorth AGP bus */
8558d942	191	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	192
40c5dce9	193	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	194	dev, "pci-conf-idx", 0x1000);
40c5dce9	195	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	196	dev, "pci-conf-data", 0x1000);
	197	sysbus_init_mmio(dev, &h->conf_mem);
	198	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	199	return 0;
2e29bd04 BS	200	}
2e29bd04 BS	201
81a322d4	202	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	203	{
ff452ace	204	PCIHostState *h;
2e29bd04 BS	205
2e29bd04 BS	206	/* Uninorth internal bus */
8558d942	207	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	208
40c5dce9	209	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	210	dev, "pci-conf-idx", 0x1000);
40c5dce9	211	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	212	dev, "pci-conf-data", 0x1000);
	213	sysbus_init_mmio(dev, &h->conf_mem);
	214	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	215	return 0;
2e29bd04 BS	216	}
2e29bd04 BS	217
aee97b84 AK	218	PCIBus pci_pmac_init(qemu_irq pic,
	219	MemoryRegion *address_space_mem,
	220	MemoryRegion *address_space_io)
2e29bd04 BS	221	{
	222	DeviceState *dev;
	223	SysBusDevice *s;
ff452ace	224	PCIHostState *h;
2e29bd04 BS	225	UNINState *d;
	226
	227	/* Use values found on a real PowerMac */
	228	/* Uninorth main bus */
57fd7b7f	229	dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33	230	qdev_init_nofail(dev);
57fd7b7f	231	s = SYS_BUS_DEVICE(dev);
8558d942	232	h = PCI_HOST_BRIDGE(s);
57fd7b7f	233	d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
40c5dce9 PB	234	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	235	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
1be88255	236	0x80000000ULL, 0x10000000ULL);
46f3069c BS	237	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	238	&d->pci_hole);
	239
8a0e1104	240	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	241	pci_unin_set_irq, pci_unin_map_irq,
	242	pic,
	243	&d->pci_mmio,
	244	address_space_io,
60a0e443	245	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
2e29bd04	246
60398748	247	#if 0
57fd7b7f	248	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748	249	#endif
2e29bd04 BS	250
	251	sysbus_mmio_map(s, 0, 0xf2800000);
	252	sysbus_mmio_map(s, 1, 0xf2c00000);
	253
	254	/* DEC 21154 bridge */
	255	#if 0
	256	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f	257	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	258	#endif
	259
	260	/* Uninorth AGP bus */
57fd7b7f AF	261	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
57fd7b7f AF	262	dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2	263	qdev_init_nofail(dev);
57fd7b7f	264	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	265	sysbus_mmio_map(s, 0, 0xf0800000);
d27d06f2 BS	266	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	267
	268	/* Uninorth internal bus */
	269	#if 0
	270	/* XXX: not needed for now */
57fd7b7f	271	pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987	272	"uni-north-internal-pci");
57fd7b7f	273	dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2	274	qdev_init_nofail(dev);
57fd7b7f	275	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	276	sysbus_mmio_map(s, 0, 0xf4800000);
d27d06f2 BS	277	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	278	#endif
2e29bd04 BS	279
57fd7b7f	280	return h->bus;
2e29bd04 BS	281	}
2e29bd04 BS	282
aee97b84 AK	283	PCIBus pci_pmac_u3_init(qemu_irq pic,
	284	MemoryRegion *address_space_mem,
	285	MemoryRegion *address_space_io)
0f921197 AG	286	{
	287	DeviceState *dev;
	288	SysBusDevice *s;
ff452ace	289	PCIHostState *h;
0f921197 AG	290	UNINState *d;
	291
	292	/* Uninorth AGP bus */
	293
57fd7b7f	294	dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197	295	qdev_init_nofail(dev);
57fd7b7f	296	s = SYS_BUS_DEVICE(dev);
8558d942	297	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	298	d = U3_AGP_HOST_BRIDGE(dev);
0f921197	299
40c5dce9 PB	300	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	301	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
46f3069c BS	302	0x80000000ULL, 0x70000000ULL);
	303	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	304	&d->pci_hole);
	305
8a0e1104	306	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	307	pci_unin_set_irq, pci_unin_map_irq,
	308	pic,
	309	&d->pci_mmio,
	310	address_space_io,
60a0e443	311	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
0f921197 AG	312
	313	sysbus_mmio_map(s, 0, 0xf0800000);
	314	sysbus_mmio_map(s, 1, 0xf0c00000);
	315
57fd7b7f	316	pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197	317
57fd7b7f	318	return h->bus;
0f921197 AG	319	}
0f921197 AG	320
9af21dbe	321	static void unin_main_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	322	{
502a5395 PB	323	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	324	d->config[0x0D] = 0x10; // latency_timer
502a5395	325	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04	326	}
502a5395	327
9af21dbe	328	static void unin_agp_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	329	{
502a5395 PB	330	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	331	d->config[0x0D] = 0x10; // latency_timer
502a5395	332	// d->config[0x34] = 0x80; // capabilities_pointer
2e29bd04	333	}
502a5395	334
9af21dbe	335	static void u3_agp_pci_host_realize(PCIDevice d, Error *errp)
0f921197	336	{
0f921197 AG	337	/* cache line size */
	338	d->config[0x0C] = 0x08;
	339	/* latency timer */
	340	d->config[0x0D] = 0x10;
0f921197 AG	341	}
0f921197 AG	342
9af21dbe	343	static void unin_internal_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	344	{
502a5395 PB	345	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	346	d->config[0x0D] = 0x10; // latency_timer
502a5395	347	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04 BS	348	}
2e29bd04 BS	349
40021f08 AL	350	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	351	{
	352	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	353	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	354
9af21dbe	355	k->realize = unin_main_pci_host_realize;
40021f08 AL	356	k->vendor_id = PCI_VENDOR_ID_APPLE;
	357	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	358	k->revision = 0x00;
	359	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	360	/*
	361	* PCI-facing part of the host bridge, not usable without the
	362	* host-facing part, which can't be device_add'ed, yet.
	363	*/
	364	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	365	}
40021f08 AL	366
4240abff	367	static const TypeInfo unin_main_pci_host_info = {
40021f08	368	.name = "uni-north-pci",
39bffca2 AL	369	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	370	.instance_size = sizeof(PCIDevice),
40021f08	371	.class_init = unin_main_pci_host_class_init,
2e29bd04 BS	372	};
2e29bd04 BS	373
40021f08 AL	374	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	375	{
	376	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	377	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	378
9af21dbe	379	k->realize = u3_agp_pci_host_realize;
40021f08 AL	380	k->vendor_id = PCI_VENDOR_ID_APPLE;
	381	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	382	k->revision = 0x00;
	383	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	384	/*
	385	* PCI-facing part of the host bridge, not usable without the
	386	* host-facing part, which can't be device_add'ed, yet.
	387	*/
	388	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	389	}
40021f08 AL	390
4240abff	391	static const TypeInfo u3_agp_pci_host_info = {
40021f08	392	.name = "u3-agp",
39bffca2 AL	393	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	394	.instance_size = sizeof(PCIDevice),
40021f08	395	.class_init = u3_agp_pci_host_class_init,
0f921197 AG	396	};
0f921197 AG	397
40021f08 AL	398	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	399	{
	400	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	401	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	402
9af21dbe	403	k->realize = unin_agp_pci_host_realize;
40021f08 AL	404	k->vendor_id = PCI_VENDOR_ID_APPLE;
	405	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	406	k->revision = 0x00;
	407	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	408	/*
	409	* PCI-facing part of the host bridge, not usable without the
	410	* host-facing part, which can't be device_add'ed, yet.
	411	*/
	412	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	413	}
40021f08 AL	414
4240abff	415	static const TypeInfo unin_agp_pci_host_info = {
40021f08	416	.name = "uni-north-agp",
39bffca2 AL	417	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	418	.instance_size = sizeof(PCIDevice),
40021f08	419	.class_init = unin_agp_pci_host_class_init,
2e29bd04 BS	420	};
2e29bd04 BS	421
40021f08 AL	422	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	423	{
	424	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	425	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	426
9af21dbe	427	k->realize = unin_internal_pci_host_realize;
40021f08 AL	428	k->vendor_id = PCI_VENDOR_ID_APPLE;
	429	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	430	k->revision = 0x00;
	431	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	432	/*
	433	* PCI-facing part of the host bridge, not usable without the
	434	* host-facing part, which can't be device_add'ed, yet.
	435	*/
	436	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	437	}
40021f08 AL	438
4240abff	439	static const TypeInfo unin_internal_pci_host_info = {
40021f08	440	.name = "uni-north-internal-pci",
39bffca2 AL	441	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	442	.instance_size = sizeof(PCIDevice),
40021f08	443	.class_init = unin_internal_pci_host_class_init,
2e29bd04 BS	444	};
2e29bd04 BS	445
999e12bb AL	446	static void pci_unin_main_class_init(ObjectClass klass, void data)
	447	{
	448	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	449
	450	sbc->init = pci_unin_main_init_device;
	451	}
	452
4240abff	453	static const TypeInfo pci_unin_main_info = {
57fd7b7f	454	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	455	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	456	.instance_size = sizeof(UNINState),
39bffca2 AL	457	.class_init = pci_unin_main_class_init,
70f9c987 AF	458	};
70f9c987 AF	459
999e12bb AL	460	static void pci_u3_agp_class_init(ObjectClass klass, void data)
	461	{
	462	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	463
	464	sbc->init = pci_u3_agp_init_device;
	465	}
	466
4240abff	467	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	468	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	469	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	470	.instance_size = sizeof(UNINState),
39bffca2 AL	471	.class_init = pci_u3_agp_class_init,
70f9c987 AF	472	};
70f9c987 AF	473
999e12bb AL	474	static void pci_unin_agp_class_init(ObjectClass klass, void data)
	475	{
	476	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	477
	478	sbc->init = pci_unin_agp_init_device;
	479	}
	480
4240abff	481	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	482	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	483	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	484	.instance_size = sizeof(UNINState),
39bffca2 AL	485	.class_init = pci_unin_agp_class_init,
70f9c987 AF	486	};
70f9c987 AF	487
999e12bb AL	488	static void pci_unin_internal_class_init(ObjectClass klass, void data)
	489	{
	490	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
	491
	492	sbc->init = pci_unin_internal_init_device;
	493	}
	494
4240abff	495	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	496	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	497	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	498	.instance_size = sizeof(UNINState),
39bffca2 AL	499	.class_init = pci_unin_internal_class_init,
70f9c987 AF	500	};
70f9c987 AF	501
83f7d43a	502	static void unin_register_types(void)
2e29bd04	503	{
39bffca2 AL	504	type_register_static(&unin_main_pci_host_info);
	505	type_register_static(&u3_agp_pci_host_info);
	506	type_register_static(&unin_agp_pci_host_info);
	507	type_register_static(&unin_internal_pci_host_info);
	508
	509	type_register_static(&pci_unin_main_info);
	510	type_register_static(&pci_u3_agp_info);
	511	type_register_static(&pci_unin_agp_info);
	512	type_register_static(&pci_unin_internal_info);
502a5395	513	}
2e29bd04	514
83f7d43a	515	type_init(unin_register_types)