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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU Uninorth PCI host (for all Mac99 and newer machines) | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0b8fa32f | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
64552b6b | 26 | #include "hw/irq.h" |
83c9f4ca | 27 | #include "hw/ppc/mac.h" |
a27bd6c7 | 28 | #include "hw/qdev-properties.h" |
0b8fa32f | 29 | #include "qemu/module.h" |
83c9f4ca PB |
30 | #include "hw/pci/pci.h" |
31 | #include "hw/pci/pci_host.h" | |
5d2eaa02 | 32 | #include "hw/pci-host/uninorth.h" |
0b0c5e90 | 33 | #include "trace.h" |
f3902383 | 34 | |
fa0be69a AG |
35 | static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
36 | ||
d2b59317 | 37 | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 38 | { |
39d97e14 | 39 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
d2b59317 PB |
40 | } |
41 | ||
5d4e84c8 | 42 | static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 43 | { |
c90c393c | 44 | UNINHostState *s = opaque; |
5d4e84c8 | 45 | |
0b0c5e90 | 46 | trace_unin_set_irq(unin_irq_line[irq_num], level); |
e7755cc1 | 47 | qemu_set_irq(s->irqs[irq_num], level); |
502a5395 PB |
48 | } |
49 | ||
d86f0e32 AG |
50 | static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) |
51 | { | |
52 | uint32_t retval; | |
53 | ||
54 | if (reg & (1u << 31)) { | |
55 | /* XXX OpenBIOS compatibility hack */ | |
56 | retval = reg | (addr & 3); | |
57 | } else if (reg & 1) { | |
58 | /* CFA1 style */ | |
59 | retval = (reg & ~7u) | (addr & 7); | |
60 | } else { | |
61 | uint32_t slot, func; | |
62 | ||
63 | /* Grab CFA0 style values */ | |
5863d374 SH |
64 | slot = ctz32(reg & 0xfffff800); |
65 | if (slot == 32) { | |
66 | slot = -1; /* XXX: should this be 0? */ | |
67 | } | |
d86f0e32 AG |
68 | func = (reg >> 8) & 7; |
69 | ||
70 | /* ... and then convert them to x86 format */ | |
71 | /* config pointer */ | |
72 | retval = (reg & (0xff - 7)) | (addr & 7); | |
73 | /* slot */ | |
74 | retval |= slot << 11; | |
75 | /* fn */ | |
76 | retval |= func << 8; | |
77 | } | |
78 | ||
0b0c5e90 | 79 | trace_unin_get_config_reg(reg, addr, retval); |
d86f0e32 AG |
80 | |
81 | return retval; | |
82 | } | |
83 | ||
a8170e5e | 84 | static void unin_data_write(void *opaque, hwaddr addr, |
d0ed8076 | 85 | uint64_t val, unsigned len) |
d86f0e32 | 86 | { |
c90c393c | 87 | UNINHostState *s = opaque; |
67c332fd | 88 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
0b0c5e90 | 89 | trace_unin_data_write(addr, len, val); |
67c332fd AF |
90 | pci_data_write(phb->bus, |
91 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 AG |
92 | val, len); |
93 | } | |
94 | ||
a8170e5e | 95 | static uint64_t unin_data_read(void *opaque, hwaddr addr, |
d0ed8076 | 96 | unsigned len) |
d86f0e32 | 97 | { |
c90c393c | 98 | UNINHostState *s = opaque; |
67c332fd | 99 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
d86f0e32 AG |
100 | uint32_t val; |
101 | ||
67c332fd AF |
102 | val = pci_data_read(phb->bus, |
103 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 | 104 | len); |
0b0c5e90 | 105 | trace_unin_data_read(addr, len, val); |
d86f0e32 AG |
106 | return val; |
107 | } | |
108 | ||
d0ed8076 AK |
109 | static const MemoryRegionOps unin_data_ops = { |
110 | .read = unin_data_read, | |
111 | .write = unin_data_write, | |
112 | .endianness = DEVICE_LITTLE_ENDIAN, | |
113 | }; | |
114 | ||
c90c393c | 115 | static void pci_unin_init_irqs(UNINHostState *s) |
e7755cc1 MCA |
116 | { |
117 | int i; | |
118 | ||
119 | for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { | |
120 | s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]); | |
121 | } | |
122 | } | |
123 | ||
03756c84 MCA |
124 | static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev) |
125 | { | |
126 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); | |
127 | ||
128 | return g_strdup_printf("%x", s->ofw_addr); | |
129 | } | |
130 | ||
32cde615 MCA |
131 | static void pci_unin_main_realize(DeviceState *dev, Error **errp) |
132 | { | |
c90c393c | 133 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); |
32cde615 MCA |
134 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
135 | ||
136 | h->bus = pci_register_root_bus(dev, NULL, | |
137 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 138 | s, |
32cde615 | 139 | &s->pci_mmio, |
e226efbb | 140 | &s->pci_io, |
32cde615 MCA |
141 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
142 | ||
c1d66d37 | 143 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); |
e7755cc1 | 144 | pci_unin_init_irqs(s); |
32cde615 MCA |
145 | |
146 | /* DEC 21154 bridge */ | |
147 | #if 0 | |
148 | /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */ | |
149 | pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154"); | |
150 | #endif | |
151 | } | |
152 | ||
02034599 | 153 | static void pci_unin_main_init(Object *obj) |
502a5395 | 154 | { |
c90c393c | 155 | UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); |
02034599 MCA |
156 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
157 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
502a5395 PB |
158 | |
159 | /* Use values found on a real PowerMac */ | |
160 | /* Uninorth main bus */ | |
40c5dce9 | 161 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 162 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 163 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
164 | "unin-pci-conf-data", 0x1000); |
165 | ||
166 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
167 | 0x100000000ULL); | |
e226efbb MCA |
168 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
169 | "unin-pci-isa-mmio", 0x00800000); | |
132e9906 | 170 | |
7b19318b MCA |
171 | memory_region_init_alias(&s->pci_hole, OBJECT(s), |
172 | "unin-pci-hole", &s->pci_mmio, | |
173 | 0x80000000ULL, 0x10000000ULL); | |
174 | ||
e7755cc1 MCA |
175 | object_property_add_link(obj, "pic", TYPE_OPENPIC, |
176 | (Object **) &s->pic, | |
177 | qdev_prop_allow_set_link_before_realize, | |
178 | 0, NULL); | |
179 | ||
02034599 MCA |
180 | sysbus_init_mmio(sbd, &h->conf_mem); |
181 | sysbus_init_mmio(sbd, &h->data_mem); | |
7b19318b | 182 | sysbus_init_mmio(sbd, &s->pci_hole); |
e226efbb | 183 | sysbus_init_mmio(sbd, &s->pci_io); |
2e29bd04 BS |
184 | } |
185 | ||
32cde615 MCA |
186 | static void pci_u3_agp_realize(DeviceState *dev, Error **errp) |
187 | { | |
c90c393c | 188 | UNINHostState *s = U3_AGP_HOST_BRIDGE(dev); |
32cde615 MCA |
189 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
190 | ||
191 | h->bus = pci_register_root_bus(dev, NULL, | |
192 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 193 | s, |
32cde615 | 194 | &s->pci_mmio, |
e226efbb | 195 | &s->pci_io, |
32cde615 MCA |
196 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
197 | ||
198 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); | |
e7755cc1 | 199 | pci_unin_init_irqs(s); |
32cde615 MCA |
200 | } |
201 | ||
02034599 | 202 | static void pci_u3_agp_init(Object *obj) |
0f921197 | 203 | { |
c90c393c | 204 | UNINHostState *s = U3_AGP_HOST_BRIDGE(obj); |
02034599 MCA |
205 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
206 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
0f921197 AG |
207 | |
208 | /* Uninorth U3 AGP bus */ | |
40c5dce9 | 209 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 210 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 211 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
212 | "unin-pci-conf-data", 0x1000); |
213 | ||
214 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
215 | 0x100000000ULL); | |
e226efbb MCA |
216 | memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, |
217 | "unin-pci-isa-mmio", 0x00800000); | |
132e9906 | 218 | |
8ce3f743 MCA |
219 | memory_region_init_alias(&s->pci_hole, OBJECT(s), |
220 | "unin-pci-hole", &s->pci_mmio, | |
221 | 0x80000000ULL, 0x70000000ULL); | |
222 | ||
e7755cc1 MCA |
223 | object_property_add_link(obj, "pic", TYPE_OPENPIC, |
224 | (Object **) &s->pic, | |
225 | qdev_prop_allow_set_link_before_realize, | |
226 | 0, NULL); | |
227 | ||
02034599 MCA |
228 | sysbus_init_mmio(sbd, &h->conf_mem); |
229 | sysbus_init_mmio(sbd, &h->data_mem); | |
8ce3f743 | 230 | sysbus_init_mmio(sbd, &s->pci_hole); |
e226efbb | 231 | sysbus_init_mmio(sbd, &s->pci_io); |
0f921197 AG |
232 | } |
233 | ||
32cde615 MCA |
234 | static void pci_unin_agp_realize(DeviceState *dev, Error **errp) |
235 | { | |
c90c393c | 236 | UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); |
32cde615 MCA |
237 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
238 | ||
239 | h->bus = pci_register_root_bus(dev, NULL, | |
240 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 241 | s, |
32cde615 | 242 | &s->pci_mmio, |
e226efbb | 243 | &s->pci_io, |
32cde615 | 244 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); |
c1d66d37 MCA |
245 | |
246 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); | |
e7755cc1 | 247 | pci_unin_init_irqs(s); |
32cde615 MCA |
248 | } |
249 | ||
02034599 | 250 | static void pci_unin_agp_init(Object *obj) |
2e29bd04 | 251 | { |
c90c393c | 252 | UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); |
02034599 MCA |
253 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
254 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
255 | |
256 | /* Uninorth AGP bus */ | |
40c5dce9 | 257 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 258 | obj, "unin-agp-conf-idx", 0x1000); |
40c5dce9 | 259 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 260 | obj, "unin-agp-conf-data", 0x1000); |
e7755cc1 MCA |
261 | |
262 | object_property_add_link(obj, "pic", TYPE_OPENPIC, | |
263 | (Object **) &s->pic, | |
264 | qdev_prop_allow_set_link_before_realize, | |
265 | 0, NULL); | |
266 | ||
02034599 MCA |
267 | sysbus_init_mmio(sbd, &h->conf_mem); |
268 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
269 | } |
270 | ||
1ff861d2 MCA |
271 | static void pci_unin_internal_realize(DeviceState *dev, Error **errp) |
272 | { | |
c90c393c | 273 | UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); |
1ff861d2 MCA |
274 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
275 | ||
276 | h->bus = pci_register_root_bus(dev, NULL, | |
277 | pci_unin_set_irq, pci_unin_map_irq, | |
e7755cc1 | 278 | s, |
1ff861d2 | 279 | &s->pci_mmio, |
e226efbb | 280 | &s->pci_io, |
1ff861d2 MCA |
281 | PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); |
282 | ||
283 | pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); | |
e7755cc1 | 284 | pci_unin_init_irqs(s); |
1ff861d2 MCA |
285 | } |
286 | ||
02034599 | 287 | static void pci_unin_internal_init(Object *obj) |
2e29bd04 | 288 | { |
c90c393c | 289 | UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); |
02034599 MCA |
290 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
291 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
292 | |
293 | /* Uninorth internal bus */ | |
40c5dce9 | 294 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 295 | obj, "unin-pci-conf-idx", 0x1000); |
40c5dce9 | 296 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 297 | obj, "unin-pci-conf-data", 0x1000); |
e7755cc1 MCA |
298 | |
299 | object_property_add_link(obj, "pic", TYPE_OPENPIC, | |
300 | (Object **) &s->pic, | |
301 | qdev_prop_allow_set_link_before_realize, | |
302 | 0, NULL); | |
303 | ||
02034599 MCA |
304 | sysbus_init_mmio(sbd, &h->conf_mem); |
305 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
306 | } |
307 | ||
9af21dbe | 308 | static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 309 | { |
4d309c96 MCA |
310 | /* cache_line_size */ |
311 | d->config[0x0C] = 0x08; | |
312 | /* latency_timer */ | |
313 | d->config[0x0D] = 0x10; | |
314 | /* capabilities_pointer */ | |
315 | d->config[0x34] = 0x00; | |
4d309c96 | 316 | |
98ae3b27 JA |
317 | /* |
318 | * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI | |
319 | * memory space with base 0x80000000, size 0x10000000 for Apple's | |
320 | * AppleMacRiscPCI driver | |
321 | */ | |
322 | d->config[0x48] = 0x0; | |
323 | d->config[0x49] = 0x0; | |
324 | d->config[0x4a] = 0x0; | |
325 | d->config[0x4b] = 0x1; | |
2e29bd04 | 326 | } |
502a5395 | 327 | |
c1d66d37 MCA |
328 | static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) |
329 | { | |
330 | /* cache_line_size */ | |
331 | d->config[0x0C] = 0x08; | |
332 | /* latency_timer */ | |
333 | d->config[0x0D] = 0x10; | |
334 | /* capabilities_pointer | |
335 | d->config[0x34] = 0x80; */ | |
336 | } | |
337 | ||
9af21dbe | 338 | static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) |
0f921197 | 339 | { |
0f921197 AG |
340 | /* cache line size */ |
341 | d->config[0x0C] = 0x08; | |
342 | /* latency timer */ | |
343 | d->config[0x0D] = 0x10; | |
0f921197 AG |
344 | } |
345 | ||
9af21dbe | 346 | static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 347 | { |
4d309c96 MCA |
348 | /* cache_line_size */ |
349 | d->config[0x0C] = 0x08; | |
350 | /* latency_timer */ | |
351 | d->config[0x0D] = 0x10; | |
352 | /* capabilities_pointer */ | |
353 | d->config[0x34] = 0x00; | |
2e29bd04 BS |
354 | } |
355 | ||
40021f08 AL |
356 | static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) |
357 | { | |
358 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 359 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 360 | |
9af21dbe | 361 | k->realize = unin_main_pci_host_realize; |
40021f08 AL |
362 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
363 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; | |
364 | k->revision = 0x00; | |
365 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
366 | /* |
367 | * PCI-facing part of the host bridge, not usable without the | |
368 | * host-facing part, which can't be device_add'ed, yet. | |
369 | */ | |
e90f2a8c | 370 | dc->user_creatable = false; |
40021f08 AL |
371 | } |
372 | ||
4240abff | 373 | static const TypeInfo unin_main_pci_host_info = { |
40021f08 | 374 | .name = "uni-north-pci", |
39bffca2 AL |
375 | .parent = TYPE_PCI_DEVICE, |
376 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 377 | .class_init = unin_main_pci_host_class_init, |
fd3b02c8 EH |
378 | .interfaces = (InterfaceInfo[]) { |
379 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
380 | { }, | |
381 | }, | |
2e29bd04 BS |
382 | }; |
383 | ||
40021f08 AL |
384 | static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) |
385 | { | |
386 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 387 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 388 | |
9af21dbe | 389 | k->realize = u3_agp_pci_host_realize; |
40021f08 AL |
390 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
391 | k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; | |
392 | k->revision = 0x00; | |
393 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
394 | /* |
395 | * PCI-facing part of the host bridge, not usable without the | |
396 | * host-facing part, which can't be device_add'ed, yet. | |
397 | */ | |
e90f2a8c | 398 | dc->user_creatable = false; |
40021f08 AL |
399 | } |
400 | ||
4240abff | 401 | static const TypeInfo u3_agp_pci_host_info = { |
40021f08 | 402 | .name = "u3-agp", |
39bffca2 AL |
403 | .parent = TYPE_PCI_DEVICE, |
404 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 405 | .class_init = u3_agp_pci_host_class_init, |
fd3b02c8 EH |
406 | .interfaces = (InterfaceInfo[]) { |
407 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
408 | { }, | |
409 | }, | |
0f921197 AG |
410 | }; |
411 | ||
40021f08 AL |
412 | static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) |
413 | { | |
414 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 415 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 416 | |
9af21dbe | 417 | k->realize = unin_agp_pci_host_realize; |
40021f08 AL |
418 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
419 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; | |
420 | k->revision = 0x00; | |
421 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
422 | /* |
423 | * PCI-facing part of the host bridge, not usable without the | |
424 | * host-facing part, which can't be device_add'ed, yet. | |
425 | */ | |
e90f2a8c | 426 | dc->user_creatable = false; |
40021f08 AL |
427 | } |
428 | ||
4240abff | 429 | static const TypeInfo unin_agp_pci_host_info = { |
40021f08 | 430 | .name = "uni-north-agp", |
39bffca2 AL |
431 | .parent = TYPE_PCI_DEVICE, |
432 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 433 | .class_init = unin_agp_pci_host_class_init, |
fd3b02c8 EH |
434 | .interfaces = (InterfaceInfo[]) { |
435 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
436 | { }, | |
437 | }, | |
2e29bd04 BS |
438 | }; |
439 | ||
40021f08 AL |
440 | static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) |
441 | { | |
442 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 443 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 444 | |
9af21dbe | 445 | k->realize = unin_internal_pci_host_realize; |
40021f08 AL |
446 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
447 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; | |
448 | k->revision = 0x00; | |
449 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
450 | /* |
451 | * PCI-facing part of the host bridge, not usable without the | |
452 | * host-facing part, which can't be device_add'ed, yet. | |
453 | */ | |
e90f2a8c | 454 | dc->user_creatable = false; |
40021f08 AL |
455 | } |
456 | ||
4240abff | 457 | static const TypeInfo unin_internal_pci_host_info = { |
40021f08 | 458 | .name = "uni-north-internal-pci", |
39bffca2 AL |
459 | .parent = TYPE_PCI_DEVICE, |
460 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 461 | .class_init = unin_internal_pci_host_class_init, |
fd3b02c8 EH |
462 | .interfaces = (InterfaceInfo[]) { |
463 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
464 | { }, | |
465 | }, | |
2e29bd04 BS |
466 | }; |
467 | ||
03756c84 MCA |
468 | static Property pci_unin_main_pci_host_props[] = { |
469 | DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1), | |
470 | DEFINE_PROP_END_OF_LIST() | |
471 | }; | |
472 | ||
999e12bb AL |
473 | static void pci_unin_main_class_init(ObjectClass *klass, void *data) |
474 | { | |
1d16f86a | 475 | DeviceClass *dc = DEVICE_CLASS(klass); |
03756c84 | 476 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
999e12bb | 477 | |
32cde615 | 478 | dc->realize = pci_unin_main_realize; |
03756c84 | 479 | dc->props = pci_unin_main_pci_host_props; |
1d16f86a | 480 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
03756c84 MCA |
481 | dc->fw_name = "pci"; |
482 | sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address; | |
999e12bb AL |
483 | } |
484 | ||
4240abff | 485 | static const TypeInfo pci_unin_main_info = { |
57fd7b7f | 486 | .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, |
8558d942 | 487 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 488 | .instance_size = sizeof(UNINHostState), |
02034599 | 489 | .instance_init = pci_unin_main_init, |
39bffca2 | 490 | .class_init = pci_unin_main_class_init, |
70f9c987 AF |
491 | }; |
492 | ||
999e12bb AL |
493 | static void pci_u3_agp_class_init(ObjectClass *klass, void *data) |
494 | { | |
1d16f86a | 495 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 496 | |
32cde615 | 497 | dc->realize = pci_u3_agp_realize; |
1d16f86a | 498 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
499 | } |
500 | ||
4240abff | 501 | static const TypeInfo pci_u3_agp_info = { |
57fd7b7f | 502 | .name = TYPE_U3_AGP_HOST_BRIDGE, |
8558d942 | 503 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 504 | .instance_size = sizeof(UNINHostState), |
02034599 | 505 | .instance_init = pci_u3_agp_init, |
39bffca2 | 506 | .class_init = pci_u3_agp_class_init, |
70f9c987 AF |
507 | }; |
508 | ||
999e12bb AL |
509 | static void pci_unin_agp_class_init(ObjectClass *klass, void *data) |
510 | { | |
1d16f86a | 511 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 512 | |
32cde615 | 513 | dc->realize = pci_unin_agp_realize; |
1d16f86a | 514 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
515 | } |
516 | ||
4240abff | 517 | static const TypeInfo pci_unin_agp_info = { |
57fd7b7f | 518 | .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, |
8558d942 | 519 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 520 | .instance_size = sizeof(UNINHostState), |
02034599 | 521 | .instance_init = pci_unin_agp_init, |
39bffca2 | 522 | .class_init = pci_unin_agp_class_init, |
70f9c987 AF |
523 | }; |
524 | ||
999e12bb AL |
525 | static void pci_unin_internal_class_init(ObjectClass *klass, void *data) |
526 | { | |
1d16f86a | 527 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 528 | |
1ff861d2 | 529 | dc->realize = pci_unin_internal_realize; |
1d16f86a | 530 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
531 | } |
532 | ||
4240abff | 533 | static const TypeInfo pci_unin_internal_info = { |
57fd7b7f | 534 | .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, |
8558d942 | 535 | .parent = TYPE_PCI_HOST_BRIDGE, |
c90c393c | 536 | .instance_size = sizeof(UNINHostState), |
02034599 | 537 | .instance_init = pci_unin_internal_init, |
39bffca2 | 538 | .class_init = pci_unin_internal_class_init, |
70f9c987 AF |
539 | }; |
540 | ||
0662946a MCA |
541 | /* UniN device */ |
542 | static void unin_write(void *opaque, hwaddr addr, uint64_t value, | |
543 | unsigned size) | |
544 | { | |
545 | trace_unin_write(addr, value); | |
0662946a MCA |
546 | } |
547 | ||
548 | static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) | |
549 | { | |
550 | uint32_t value; | |
551 | ||
0662946a MCA |
552 | switch (addr) { |
553 | case 0: | |
45fefe7c MCA |
554 | value = UNINORTH_VERSION_10A; |
555 | break; | |
556 | default: | |
557 | value = 0; | |
0662946a MCA |
558 | } |
559 | ||
560 | trace_unin_read(addr, value); | |
561 | ||
562 | return value; | |
563 | } | |
564 | ||
565 | static const MemoryRegionOps unin_ops = { | |
566 | .read = unin_read, | |
567 | .write = unin_write, | |
568 | .endianness = DEVICE_BIG_ENDIAN, | |
569 | }; | |
570 | ||
571 | static void unin_init(Object *obj) | |
572 | { | |
573 | UNINState *s = UNI_NORTH(obj); | |
574 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
575 | ||
45fefe7c | 576 | memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000); |
0662946a MCA |
577 | |
578 | sysbus_init_mmio(sbd, &s->mem); | |
579 | } | |
580 | ||
581 | static void unin_class_init(ObjectClass *klass, void *data) | |
582 | { | |
583 | DeviceClass *dc = DEVICE_CLASS(klass); | |
584 | ||
585 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); | |
586 | } | |
587 | ||
588 | static const TypeInfo unin_info = { | |
589 | .name = TYPE_UNI_NORTH, | |
590 | .parent = TYPE_SYS_BUS_DEVICE, | |
591 | .instance_size = sizeof(UNINState), | |
592 | .instance_init = unin_init, | |
593 | .class_init = unin_class_init, | |
594 | }; | |
595 | ||
83f7d43a | 596 | static void unin_register_types(void) |
2e29bd04 | 597 | { |
39bffca2 AL |
598 | type_register_static(&unin_main_pci_host_info); |
599 | type_register_static(&u3_agp_pci_host_info); | |
600 | type_register_static(&unin_agp_pci_host_info); | |
601 | type_register_static(&unin_internal_pci_host_info); | |
602 | ||
603 | type_register_static(&pci_unin_main_info); | |
604 | type_register_static(&pci_u3_agp_info); | |
605 | type_register_static(&pci_unin_agp_info); | |
606 | type_register_static(&pci_unin_internal_info); | |
0662946a MCA |
607 | |
608 | type_register_static(&unin_info); | |
502a5395 | 609 | } |
2e29bd04 | 610 | |
83f7d43a | 611 | type_init(unin_register_types) |