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Commit | Line | Data |
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502a5395 PB |
1 | /* |
2 | * QEMU Uninorth PCI host (for all Mac99 and newer machines) | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
0d75590d | 24 | #include "qemu/osdep.h" |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/ppc/mac.h" | |
27 | #include "hw/pci/pci.h" | |
28 | #include "hw/pci/pci_host.h" | |
5d2eaa02 | 29 | #include "hw/pci-host/uninorth.h" |
0b0c5e90 | 30 | #include "trace.h" |
f3902383 | 31 | |
fa0be69a AG |
32 | static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
33 | ||
d2b59317 | 34 | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 35 | { |
39d97e14 | 36 | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
d2b59317 PB |
37 | } |
38 | ||
5d4e84c8 | 39 | static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 40 | { |
5d4e84c8 JQ |
41 | qemu_irq *pic = opaque; |
42 | ||
0b0c5e90 | 43 | trace_unin_set_irq(unin_irq_line[irq_num], level); |
fa0be69a | 44 | qemu_set_irq(pic[unin_irq_line[irq_num]], level); |
502a5395 PB |
45 | } |
46 | ||
d86f0e32 AG |
47 | static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) |
48 | { | |
49 | uint32_t retval; | |
50 | ||
51 | if (reg & (1u << 31)) { | |
52 | /* XXX OpenBIOS compatibility hack */ | |
53 | retval = reg | (addr & 3); | |
54 | } else if (reg & 1) { | |
55 | /* CFA1 style */ | |
56 | retval = (reg & ~7u) | (addr & 7); | |
57 | } else { | |
58 | uint32_t slot, func; | |
59 | ||
60 | /* Grab CFA0 style values */ | |
5863d374 SH |
61 | slot = ctz32(reg & 0xfffff800); |
62 | if (slot == 32) { | |
63 | slot = -1; /* XXX: should this be 0? */ | |
64 | } | |
d86f0e32 AG |
65 | func = (reg >> 8) & 7; |
66 | ||
67 | /* ... and then convert them to x86 format */ | |
68 | /* config pointer */ | |
69 | retval = (reg & (0xff - 7)) | (addr & 7); | |
70 | /* slot */ | |
71 | retval |= slot << 11; | |
72 | /* fn */ | |
73 | retval |= func << 8; | |
74 | } | |
75 | ||
0b0c5e90 | 76 | trace_unin_get_config_reg(reg, addr, retval); |
d86f0e32 AG |
77 | |
78 | return retval; | |
79 | } | |
80 | ||
a8170e5e | 81 | static void unin_data_write(void *opaque, hwaddr addr, |
d0ed8076 | 82 | uint64_t val, unsigned len) |
d86f0e32 | 83 | { |
d0ed8076 | 84 | UNINState *s = opaque; |
67c332fd | 85 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
0b0c5e90 | 86 | trace_unin_data_write(addr, len, val); |
67c332fd AF |
87 | pci_data_write(phb->bus, |
88 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 AG |
89 | val, len); |
90 | } | |
91 | ||
a8170e5e | 92 | static uint64_t unin_data_read(void *opaque, hwaddr addr, |
d0ed8076 | 93 | unsigned len) |
d86f0e32 | 94 | { |
d0ed8076 | 95 | UNINState *s = opaque; |
67c332fd | 96 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
d86f0e32 AG |
97 | uint32_t val; |
98 | ||
67c332fd AF |
99 | val = pci_data_read(phb->bus, |
100 | unin_get_config_reg(phb->config_reg, addr), | |
d86f0e32 | 101 | len); |
0b0c5e90 | 102 | trace_unin_data_read(addr, len, val); |
d86f0e32 AG |
103 | return val; |
104 | } | |
105 | ||
d0ed8076 AK |
106 | static const MemoryRegionOps unin_data_ops = { |
107 | .read = unin_data_read, | |
108 | .write = unin_data_write, | |
109 | .endianness = DEVICE_LITTLE_ENDIAN, | |
110 | }; | |
111 | ||
32cde615 MCA |
112 | static void pci_unin_main_realize(DeviceState *dev, Error **errp) |
113 | { | |
114 | UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); | |
115 | PCIHostState *h = PCI_HOST_BRIDGE(dev); | |
116 | ||
117 | h->bus = pci_register_root_bus(dev, NULL, | |
118 | pci_unin_set_irq, pci_unin_map_irq, | |
119 | s->pic_irqs, | |
120 | &s->pci_mmio, | |
121 | get_system_io(), | |
122 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); | |
123 | ||
c1d66d37 | 124 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); |
32cde615 MCA |
125 | |
126 | /* DEC 21154 bridge */ | |
127 | #if 0 | |
128 | /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */ | |
129 | pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154"); | |
130 | #endif | |
131 | } | |
132 | ||
02034599 | 133 | static void pci_unin_main_init(Object *obj) |
502a5395 | 134 | { |
132e9906 | 135 | UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); |
02034599 MCA |
136 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
137 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
502a5395 PB |
138 | |
139 | /* Use values found on a real PowerMac */ | |
140 | /* Uninorth main bus */ | |
40c5dce9 | 141 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 142 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 143 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
144 | "unin-pci-conf-data", 0x1000); |
145 | ||
146 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
147 | 0x100000000ULL); | |
148 | ||
02034599 MCA |
149 | sysbus_init_mmio(sbd, &h->conf_mem); |
150 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
151 | } |
152 | ||
32cde615 MCA |
153 | static void pci_u3_agp_realize(DeviceState *dev, Error **errp) |
154 | { | |
155 | UNINState *s = U3_AGP_HOST_BRIDGE(dev); | |
156 | PCIHostState *h = PCI_HOST_BRIDGE(dev); | |
157 | ||
158 | h->bus = pci_register_root_bus(dev, NULL, | |
159 | pci_unin_set_irq, pci_unin_map_irq, | |
160 | s->pic_irqs, | |
161 | &s->pci_mmio, | |
162 | get_system_io(), | |
163 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); | |
164 | ||
165 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); | |
166 | } | |
167 | ||
02034599 | 168 | static void pci_u3_agp_init(Object *obj) |
0f921197 | 169 | { |
132e9906 | 170 | UNINState *s = U3_AGP_HOST_BRIDGE(obj); |
02034599 MCA |
171 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
172 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
0f921197 AG |
173 | |
174 | /* Uninorth U3 AGP bus */ | |
40c5dce9 | 175 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 176 | obj, "unin-pci-conf-idx", 0x1000); |
02034599 | 177 | memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, |
132e9906 MCA |
178 | "unin-pci-conf-data", 0x1000); |
179 | ||
180 | memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", | |
181 | 0x100000000ULL); | |
182 | ||
02034599 MCA |
183 | sysbus_init_mmio(sbd, &h->conf_mem); |
184 | sysbus_init_mmio(sbd, &h->data_mem); | |
0f921197 AG |
185 | } |
186 | ||
32cde615 MCA |
187 | static void pci_unin_agp_realize(DeviceState *dev, Error **errp) |
188 | { | |
189 | UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); | |
190 | PCIHostState *h = PCI_HOST_BRIDGE(dev); | |
191 | ||
192 | h->bus = pci_register_root_bus(dev, NULL, | |
193 | pci_unin_set_irq, pci_unin_map_irq, | |
194 | s->pic_irqs, | |
195 | &s->pci_mmio, | |
196 | get_system_io(), | |
197 | PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); | |
c1d66d37 MCA |
198 | |
199 | pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); | |
32cde615 MCA |
200 | } |
201 | ||
02034599 | 202 | static void pci_unin_agp_init(Object *obj) |
2e29bd04 | 203 | { |
02034599 MCA |
204 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
205 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
206 | |
207 | /* Uninorth AGP bus */ | |
40c5dce9 | 208 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 209 | obj, "unin-agp-conf-idx", 0x1000); |
40c5dce9 | 210 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 211 | obj, "unin-agp-conf-data", 0x1000); |
02034599 MCA |
212 | sysbus_init_mmio(sbd, &h->conf_mem); |
213 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
214 | } |
215 | ||
02034599 | 216 | static void pci_unin_internal_init(Object *obj) |
2e29bd04 | 217 | { |
02034599 MCA |
218 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
219 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
2e29bd04 BS |
220 | |
221 | /* Uninorth internal bus */ | |
40c5dce9 | 222 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, |
132e9906 | 223 | obj, "unin-pci-conf-idx", 0x1000); |
40c5dce9 | 224 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, |
132e9906 | 225 | obj, "unin-pci-conf-data", 0x1000); |
02034599 MCA |
226 | sysbus_init_mmio(sbd, &h->conf_mem); |
227 | sysbus_init_mmio(sbd, &h->data_mem); | |
2e29bd04 BS |
228 | } |
229 | ||
0f4b5415 | 230 | UNINState *pci_pmac_init(qemu_irq *pic, |
32cde615 | 231 | MemoryRegion *address_space_mem) |
2e29bd04 BS |
232 | { |
233 | DeviceState *dev; | |
234 | SysBusDevice *s; | |
235 | UNINState *d; | |
236 | ||
237 | /* Use values found on a real PowerMac */ | |
2e29bd04 | 238 | /* Uninorth AGP bus */ |
57fd7b7f | 239 | dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); |
0b065209 | 240 | qdev_prop_set_ptr(dev, "pic-irqs", pic); |
d27d06f2 | 241 | qdev_init_nofail(dev); |
57fd7b7f | 242 | s = SYS_BUS_DEVICE(dev); |
d27d06f2 BS |
243 | sysbus_mmio_map(s, 0, 0xf0800000); |
244 | sysbus_mmio_map(s, 1, 0xf0c00000); | |
2e29bd04 BS |
245 | |
246 | /* Uninorth internal bus */ | |
247 | #if 0 | |
248 | /* XXX: not needed for now */ | |
57fd7b7f | 249 | pci_create_simple(h->bus, PCI_DEVFN(14, 0), |
70f9c987 | 250 | "uni-north-internal-pci"); |
57fd7b7f | 251 | dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); |
d27d06f2 | 252 | qdev_init_nofail(dev); |
57fd7b7f | 253 | s = SYS_BUS_DEVICE(dev); |
d27d06f2 BS |
254 | sysbus_mmio_map(s, 0, 0xf4800000); |
255 | sysbus_mmio_map(s, 1, 0xf4c00000); | |
2e29bd04 BS |
256 | #endif |
257 | ||
32cde615 MCA |
258 | /* Uninorth main bus */ |
259 | dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); | |
260 | qdev_prop_set_ptr(dev, "pic-irqs", pic); | |
261 | qdev_init_nofail(dev); | |
262 | s = SYS_BUS_DEVICE(dev); | |
263 | d = UNI_NORTH_PCI_HOST_BRIDGE(dev); | |
264 | memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio, | |
265 | 0x80000000ULL, 0x10000000ULL); | |
266 | memory_region_add_subregion(address_space_mem, 0x80000000ULL, | |
267 | &d->pci_hole); | |
268 | ||
269 | sysbus_mmio_map(s, 0, 0xf2800000); | |
270 | sysbus_mmio_map(s, 1, 0xf2c00000); | |
271 | ||
0f4b5415 | 272 | return d; |
2e29bd04 BS |
273 | } |
274 | ||
0f4b5415 | 275 | UNINState *pci_pmac_u3_init(qemu_irq *pic, |
32cde615 | 276 | MemoryRegion *address_space_mem) |
0f921197 AG |
277 | { |
278 | DeviceState *dev; | |
279 | SysBusDevice *s; | |
280 | UNINState *d; | |
281 | ||
282 | /* Uninorth AGP bus */ | |
57fd7b7f | 283 | dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); |
0b065209 | 284 | qdev_prop_set_ptr(dev, "pic-irqs", pic); |
0f921197 | 285 | qdev_init_nofail(dev); |
57fd7b7f | 286 | s = SYS_BUS_DEVICE(dev); |
57fd7b7f | 287 | d = U3_AGP_HOST_BRIDGE(dev); |
0f921197 | 288 | |
40c5dce9 | 289 | memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio, |
46f3069c BS |
290 | 0x80000000ULL, 0x70000000ULL); |
291 | memory_region_add_subregion(address_space_mem, 0x80000000ULL, | |
292 | &d->pci_hole); | |
293 | ||
0f921197 AG |
294 | sysbus_mmio_map(s, 0, 0xf0800000); |
295 | sysbus_mmio_map(s, 1, 0xf0c00000); | |
296 | ||
0f4b5415 | 297 | return d; |
0f921197 AG |
298 | } |
299 | ||
9af21dbe | 300 | static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 301 | { |
4d309c96 MCA |
302 | /* cache_line_size */ |
303 | d->config[0x0C] = 0x08; | |
304 | /* latency_timer */ | |
305 | d->config[0x0D] = 0x10; | |
306 | /* capabilities_pointer */ | |
307 | d->config[0x34] = 0x00; | |
4d309c96 | 308 | |
98ae3b27 JA |
309 | /* |
310 | * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI | |
311 | * memory space with base 0x80000000, size 0x10000000 for Apple's | |
312 | * AppleMacRiscPCI driver | |
313 | */ | |
314 | d->config[0x48] = 0x0; | |
315 | d->config[0x49] = 0x0; | |
316 | d->config[0x4a] = 0x0; | |
317 | d->config[0x4b] = 0x1; | |
2e29bd04 | 318 | } |
502a5395 | 319 | |
c1d66d37 MCA |
320 | static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) |
321 | { | |
322 | /* cache_line_size */ | |
323 | d->config[0x0C] = 0x08; | |
324 | /* latency_timer */ | |
325 | d->config[0x0D] = 0x10; | |
326 | /* capabilities_pointer | |
327 | d->config[0x34] = 0x80; */ | |
328 | } | |
329 | ||
9af21dbe | 330 | static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) |
0f921197 | 331 | { |
0f921197 AG |
332 | /* cache line size */ |
333 | d->config[0x0C] = 0x08; | |
334 | /* latency timer */ | |
335 | d->config[0x0D] = 0x10; | |
0f921197 AG |
336 | } |
337 | ||
9af21dbe | 338 | static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) |
2e29bd04 | 339 | { |
4d309c96 MCA |
340 | /* cache_line_size */ |
341 | d->config[0x0C] = 0x08; | |
342 | /* latency_timer */ | |
343 | d->config[0x0D] = 0x10; | |
344 | /* capabilities_pointer */ | |
345 | d->config[0x34] = 0x00; | |
2e29bd04 BS |
346 | } |
347 | ||
40021f08 AL |
348 | static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) |
349 | { | |
350 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 351 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 352 | |
9af21dbe | 353 | k->realize = unin_main_pci_host_realize; |
40021f08 AL |
354 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
355 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; | |
356 | k->revision = 0x00; | |
357 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
358 | /* |
359 | * PCI-facing part of the host bridge, not usable without the | |
360 | * host-facing part, which can't be device_add'ed, yet. | |
361 | */ | |
e90f2a8c | 362 | dc->user_creatable = false; |
40021f08 AL |
363 | } |
364 | ||
4240abff | 365 | static const TypeInfo unin_main_pci_host_info = { |
40021f08 | 366 | .name = "uni-north-pci", |
39bffca2 AL |
367 | .parent = TYPE_PCI_DEVICE, |
368 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 369 | .class_init = unin_main_pci_host_class_init, |
fd3b02c8 EH |
370 | .interfaces = (InterfaceInfo[]) { |
371 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
372 | { }, | |
373 | }, | |
2e29bd04 BS |
374 | }; |
375 | ||
40021f08 AL |
376 | static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) |
377 | { | |
378 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 379 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 380 | |
9af21dbe | 381 | k->realize = u3_agp_pci_host_realize; |
40021f08 AL |
382 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
383 | k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; | |
384 | k->revision = 0x00; | |
385 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
386 | /* |
387 | * PCI-facing part of the host bridge, not usable without the | |
388 | * host-facing part, which can't be device_add'ed, yet. | |
389 | */ | |
e90f2a8c | 390 | dc->user_creatable = false; |
40021f08 AL |
391 | } |
392 | ||
4240abff | 393 | static const TypeInfo u3_agp_pci_host_info = { |
40021f08 | 394 | .name = "u3-agp", |
39bffca2 AL |
395 | .parent = TYPE_PCI_DEVICE, |
396 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 397 | .class_init = u3_agp_pci_host_class_init, |
fd3b02c8 EH |
398 | .interfaces = (InterfaceInfo[]) { |
399 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
400 | { }, | |
401 | }, | |
0f921197 AG |
402 | }; |
403 | ||
40021f08 AL |
404 | static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) |
405 | { | |
406 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 407 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 408 | |
9af21dbe | 409 | k->realize = unin_agp_pci_host_realize; |
40021f08 AL |
410 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
411 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; | |
412 | k->revision = 0x00; | |
413 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
414 | /* |
415 | * PCI-facing part of the host bridge, not usable without the | |
416 | * host-facing part, which can't be device_add'ed, yet. | |
417 | */ | |
e90f2a8c | 418 | dc->user_creatable = false; |
40021f08 AL |
419 | } |
420 | ||
4240abff | 421 | static const TypeInfo unin_agp_pci_host_info = { |
40021f08 | 422 | .name = "uni-north-agp", |
39bffca2 AL |
423 | .parent = TYPE_PCI_DEVICE, |
424 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 425 | .class_init = unin_agp_pci_host_class_init, |
fd3b02c8 EH |
426 | .interfaces = (InterfaceInfo[]) { |
427 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
428 | { }, | |
429 | }, | |
2e29bd04 BS |
430 | }; |
431 | ||
40021f08 AL |
432 | static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) |
433 | { | |
434 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
08c58f92 | 435 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 436 | |
9af21dbe | 437 | k->realize = unin_internal_pci_host_realize; |
40021f08 AL |
438 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
439 | k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; | |
440 | k->revision = 0x00; | |
441 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
08c58f92 MA |
442 | /* |
443 | * PCI-facing part of the host bridge, not usable without the | |
444 | * host-facing part, which can't be device_add'ed, yet. | |
445 | */ | |
e90f2a8c | 446 | dc->user_creatable = false; |
40021f08 AL |
447 | } |
448 | ||
4240abff | 449 | static const TypeInfo unin_internal_pci_host_info = { |
40021f08 | 450 | .name = "uni-north-internal-pci", |
39bffca2 AL |
451 | .parent = TYPE_PCI_DEVICE, |
452 | .instance_size = sizeof(PCIDevice), | |
40021f08 | 453 | .class_init = unin_internal_pci_host_class_init, |
fd3b02c8 EH |
454 | .interfaces = (InterfaceInfo[]) { |
455 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
456 | { }, | |
457 | }, | |
2e29bd04 BS |
458 | }; |
459 | ||
0b065209 MCA |
460 | static Property pci_unin_main_properties[] = { |
461 | DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), | |
462 | DEFINE_PROP_END_OF_LIST(), | |
463 | }; | |
464 | ||
999e12bb AL |
465 | static void pci_unin_main_class_init(ObjectClass *klass, void *data) |
466 | { | |
1d16f86a | 467 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 468 | |
32cde615 | 469 | dc->realize = pci_unin_main_realize; |
0b065209 | 470 | dc->props = pci_unin_main_properties; |
1d16f86a | 471 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
472 | } |
473 | ||
4240abff | 474 | static const TypeInfo pci_unin_main_info = { |
57fd7b7f | 475 | .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, |
8558d942 | 476 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 477 | .instance_size = sizeof(UNINState), |
02034599 | 478 | .instance_init = pci_unin_main_init, |
39bffca2 | 479 | .class_init = pci_unin_main_class_init, |
70f9c987 AF |
480 | }; |
481 | ||
0b065209 MCA |
482 | static Property pci_u3_agp_properties[] = { |
483 | DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), | |
484 | DEFINE_PROP_END_OF_LIST(), | |
485 | }; | |
486 | ||
999e12bb AL |
487 | static void pci_u3_agp_class_init(ObjectClass *klass, void *data) |
488 | { | |
1d16f86a | 489 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 490 | |
32cde615 | 491 | dc->realize = pci_u3_agp_realize; |
0b065209 | 492 | dc->props = pci_u3_agp_properties; |
1d16f86a | 493 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
494 | } |
495 | ||
4240abff | 496 | static const TypeInfo pci_u3_agp_info = { |
57fd7b7f | 497 | .name = TYPE_U3_AGP_HOST_BRIDGE, |
8558d942 | 498 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 499 | .instance_size = sizeof(UNINState), |
02034599 | 500 | .instance_init = pci_u3_agp_init, |
39bffca2 | 501 | .class_init = pci_u3_agp_class_init, |
70f9c987 AF |
502 | }; |
503 | ||
0b065209 MCA |
504 | static Property pci_unin_agp_class_properties[] = { |
505 | DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), | |
506 | DEFINE_PROP_END_OF_LIST(), | |
507 | }; | |
508 | ||
999e12bb AL |
509 | static void pci_unin_agp_class_init(ObjectClass *klass, void *data) |
510 | { | |
1d16f86a | 511 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 512 | |
32cde615 | 513 | dc->realize = pci_unin_agp_realize; |
0b065209 | 514 | dc->props = pci_unin_agp_class_properties; |
1d16f86a | 515 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
516 | } |
517 | ||
4240abff | 518 | static const TypeInfo pci_unin_agp_info = { |
57fd7b7f | 519 | .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, |
8558d942 | 520 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 521 | .instance_size = sizeof(UNINState), |
02034599 | 522 | .instance_init = pci_unin_agp_init, |
39bffca2 | 523 | .class_init = pci_unin_agp_class_init, |
70f9c987 AF |
524 | }; |
525 | ||
999e12bb AL |
526 | static void pci_unin_internal_class_init(ObjectClass *klass, void *data) |
527 | { | |
1d16f86a | 528 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 529 | |
1d16f86a | 530 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
999e12bb AL |
531 | } |
532 | ||
4240abff | 533 | static const TypeInfo pci_unin_internal_info = { |
57fd7b7f | 534 | .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, |
8558d942 | 535 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 536 | .instance_size = sizeof(UNINState), |
02034599 | 537 | .instance_init = pci_unin_internal_init, |
39bffca2 | 538 | .class_init = pci_unin_internal_class_init, |
70f9c987 AF |
539 | }; |
540 | ||
83f7d43a | 541 | static void unin_register_types(void) |
2e29bd04 | 542 | { |
39bffca2 AL |
543 | type_register_static(&unin_main_pci_host_info); |
544 | type_register_static(&u3_agp_pci_host_info); | |
545 | type_register_static(&unin_agp_pci_host_info); | |
546 | type_register_static(&unin_internal_pci_host_info); | |
547 | ||
548 | type_register_static(&pci_unin_main_info); | |
549 | type_register_static(&pci_u3_agp_info); | |
550 | type_register_static(&pci_unin_agp_info); | |
551 | type_register_static(&pci_unin_internal_info); | |
502a5395 | 552 | } |
2e29bd04 | 553 | |
83f7d43a | 554 | type_init(unin_register_types) |