[mirror_qemu.git] / hw / pci-host / uninorth.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/uninorth.h"
#include "trace.h"

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    UNINState *s = opaque;

    trace_unin_set_irq(unin_irq_line[irq_num], level);
    qemu_set_irq(s->irqs[irq_num], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ctz32(reg & 0xfffff800);
        if (slot == 32) {
            slot = -1; /* XXX: should this be 0? */
        }
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }

    trace_unin_get_config_reg(reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    trace_unin_data_write(addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    trace_unin_data_read(addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void pci_unin_init_irqs(UNINState *s)
{
    int i;

    for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
        s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
    }
}

static void pci_unin_main_realize(DeviceState *dev, Error **errp)
{
    UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    PCIHostState *h = PCI_HOST_BRIDGE(dev);

    h->bus = pci_register_root_bus(dev, NULL,
                                   pci_unin_set_irq, pci_unin_map_irq,
                                   s,
                                   &s->pci_mmio,
                                   &s->pci_io,
                                   PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
    pci_unin_init_irqs(s);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif
}

static void pci_unin_main_init(Object *obj)
{
    UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          obj, "unin-pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
                          "unin-pci-conf-data", 0x1000);

    memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
                       0x100000000ULL);
    memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
                          "unin-pci-isa-mmio", 0x00800000);

    memory_region_init_alias(&s->pci_hole, OBJECT(s),
                             "unin-pci-hole", &s->pci_mmio,
                             0x80000000ULL, 0x10000000ULL);

    object_property_add_link(obj, "pic", TYPE_OPENPIC,
                             (Object **) &s->pic,
                             qdev_prop_allow_set_link_before_realize,
                             0, NULL);

    sysbus_init_mmio(sbd, &h->conf_mem);
    sysbus_init_mmio(sbd, &h->data_mem);
    sysbus_init_mmio(sbd, &s->pci_hole);
    sysbus_init_mmio(sbd, &s->pci_io);
}

static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
{
    UNINState *s = U3_AGP_HOST_BRIDGE(dev);
    PCIHostState *h = PCI_HOST_BRIDGE(dev);

    h->bus = pci_register_root_bus(dev, NULL,
                                   pci_unin_set_irq, pci_unin_map_irq,
                                   s,
                                   &s->pci_mmio,
                                   &s->pci_io,
                                   PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
    pci_unin_init_irqs(s);
}

static void pci_u3_agp_init(Object *obj)
{
    UNINState *s = U3_AGP_HOST_BRIDGE(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    /* Uninorth U3 AGP bus */
    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          obj, "unin-pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
                          "unin-pci-conf-data", 0x1000);

    memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
                       0x100000000ULL);
    memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
                          "unin-pci-isa-mmio", 0x00800000);

    memory_region_init_alias(&s->pci_hole, OBJECT(s),
                             "unin-pci-hole", &s->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);

    object_property_add_link(obj, "pic", TYPE_OPENPIC,
                             (Object **) &s->pic,
                             qdev_prop_allow_set_link_before_realize,
                             0, NULL);

    sysbus_init_mmio(sbd, &h->conf_mem);
    sysbus_init_mmio(sbd, &h->data_mem);
    sysbus_init_mmio(sbd, &s->pci_hole);
    sysbus_init_mmio(sbd, &s->pci_io);
}

static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
{
    UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
    PCIHostState *h = PCI_HOST_BRIDGE(dev);

    h->bus = pci_register_root_bus(dev, NULL,
                                   pci_unin_set_irq, pci_unin_map_irq,
                                   s,
                                   &s->pci_mmio,
                                   &s->pci_io,
                                   PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    pci_unin_init_irqs(s);
}

static void pci_unin_agp_init(Object *obj)
{
    UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    /* Uninorth AGP bus */
    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          obj, "unin-agp-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          obj, "unin-agp-conf-data", 0x1000);

    object_property_add_link(obj, "pic", TYPE_OPENPIC,
                             (Object **) &s->pic,
                             qdev_prop_allow_set_link_before_realize,
                             0, NULL);

    sysbus_init_mmio(sbd, &h->conf_mem);
    sysbus_init_mmio(sbd, &h->data_mem);
}

static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
{
    UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
    PCIHostState *h = PCI_HOST_BRIDGE(dev);

    h->bus = pci_register_root_bus(dev, NULL,
                                   pci_unin_set_irq, pci_unin_map_irq,
                                   s,
                                   &s->pci_mmio,
                                   &s->pci_io,
                                   PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);

    pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
    pci_unin_init_irqs(s);
}

static void pci_unin_internal_init(Object *obj)
{
    UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    /* Uninorth internal bus */
    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          obj, "unin-pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          obj, "unin-pci-conf-data", 0x1000);

    object_property_add_link(obj, "pic", TYPE_OPENPIC,
                             (Object **) &s->pic,
                             qdev_prop_allow_set_link_before_realize,
                             0, NULL);

    sysbus_init_mmio(sbd, &h->conf_mem);
    sysbus_init_mmio(sbd, &h->data_mem);
}

static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache_line_size */
    d->config[0x0C] = 0x08;
    /* latency_timer */
    d->config[0x0D] = 0x10;
    /* capabilities_pointer */
    d->config[0x34] = 0x00;

    /*
     * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
     * memory space with base 0x80000000, size 0x10000000 for Apple's
     * AppleMacRiscPCI driver
     */
    d->config[0x48] = 0x0;
    d->config[0x49] = 0x0;
    d->config[0x4a] = 0x0;
    d->config[0x4b] = 0x1;
}

static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache_line_size */
    d->config[0x0C] = 0x08;
    /* latency_timer */
    d->config[0x0D] = 0x10;
    /* capabilities_pointer
    d->config[0x34] = 0x80; */
}

static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
}

static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache_line_size */
    d->config[0x0C] = 0x08;
    /* latency_timer */
    d->config[0x0D] = 0x10;
    /* capabilities_pointer */
    d->config[0x34] = 0x00;
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_main_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = u3_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_internal_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->user_creatable = false;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pci_unin_main_realize;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .instance_init = pci_unin_main_init,
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pci_u3_agp_realize;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .instance_init = pci_u3_agp_init,
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pci_unin_agp_realize;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .instance_init = pci_unin_agp_init,
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = pci_unin_internal_realize;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .instance_init = pci_unin_internal_init,
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
	26	#include "hw/ppc/mac.h"
	27	#include "hw/pci/pci.h"
	28	#include "hw/pci/pci_host.h"
5d2eaa02	29	#include "hw/pci-host/uninorth.h"
0b0c5e90	30	#include "trace.h"
f3902383	31
fa0be69a AG	32	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	33
d2b59317	34	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	35	{
39d97e14	36	return (irq_num + (pci_dev->devfn >> 3)) & 3;
d2b59317 PB	37	}
d2b59317 PB	38
5d4e84c8	39	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	40	{
e7755cc1	41	UNINState *s = opaque;
5d4e84c8	42
0b0c5e90	43	trace_unin_set_irq(unin_irq_line[irq_num], level);
e7755cc1	44	qemu_set_irq(s->irqs[irq_num], level);
502a5395 PB	45	}
502a5395 PB	46
d86f0e32 AG	47	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	48	{
	49	uint32_t retval;
	50
	51	if (reg & (1u << 31)) {
	52	/* XXX OpenBIOS compatibility hack */
	53	retval = reg \| (addr & 3);
	54	} else if (reg & 1) {
	55	/* CFA1 style */
	56	retval = (reg & ~7u) \| (addr & 7);
	57	} else {
	58	uint32_t slot, func;
	59
	60	/* Grab CFA0 style values */
5863d374 SH	61	slot = ctz32(reg & 0xfffff800);
	62	if (slot == 32) {
	63	slot = -1; /* XXX: should this be 0? */
	64	}
d86f0e32 AG	65	func = (reg >> 8) & 7;
	66
	67	/* ... and then convert them to x86 format */
	68	/* config pointer */
	69	retval = (reg & (0xff - 7)) \| (addr & 7);
	70	/* slot */
	71	retval \|= slot << 11;
	72	/* fn */
	73	retval \|= func << 8;
	74	}
	75
0b0c5e90	76	trace_unin_get_config_reg(reg, addr, retval);
d86f0e32 AG	77
	78	return retval;
	79	}
	80
a8170e5e	81	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	82	uint64_t val, unsigned len)
d86f0e32	83	{
d0ed8076	84	UNINState *s = opaque;
67c332fd	85	PCIHostState *phb = PCI_HOST_BRIDGE(s);
0b0c5e90	86	trace_unin_data_write(addr, len, val);
67c332fd AF	87	pci_data_write(phb->bus,
67c332fd AF	88	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	89	val, len);
	90	}
	91
a8170e5e	92	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	93	unsigned len)
d86f0e32	94	{
d0ed8076	95	UNINState *s = opaque;
67c332fd	96	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	97	uint32_t val;
d86f0e32 AG	98
67c332fd AF	99	val = pci_data_read(phb->bus,
67c332fd AF	100	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	101	len);
0b0c5e90	102	trace_unin_data_read(addr, len, val);
d86f0e32 AG	103	return val;
	104	}
	105
d0ed8076 AK	106	static const MemoryRegionOps unin_data_ops = {
	107	.read = unin_data_read,
	108	.write = unin_data_write,
	109	.endianness = DEVICE_LITTLE_ENDIAN,
	110	};
	111
e7755cc1 MCA	112	static void pci_unin_init_irqs(UNINState *s)
	113	{
	114	int i;
	115
	116	for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
	117	s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
	118	}
	119	}
	120
32cde615 MCA	121	static void pci_unin_main_realize(DeviceState dev, Error *errp)
	122	{
	123	UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
	124	PCIHostState *h = PCI_HOST_BRIDGE(dev);
	125
	126	h->bus = pci_register_root_bus(dev, NULL,
	127	pci_unin_set_irq, pci_unin_map_irq,
e7755cc1	128	s,
32cde615	129	&s->pci_mmio,
e226efbb	130	&s->pci_io,
32cde615 MCA	131	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
32cde615 MCA	132
c1d66d37	133	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
e7755cc1	134	pci_unin_init_irqs(s);
32cde615 MCA	135
	136	/* DEC 21154 bridge */
	137	#if 0
	138	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
	139	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
	140	#endif
	141	}
	142
02034599	143	static void pci_unin_main_init(Object *obj)
502a5395	144	{
132e9906	145	UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
02034599 MCA	146	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
02034599 MCA	147	PCIHostState *h = PCI_HOST_BRIDGE(obj);
502a5395 PB	148
	149	/* Use values found on a real PowerMac */
	150	/* Uninorth main bus */
40c5dce9	151	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
132e9906	152	obj, "unin-pci-conf-idx", 0x1000);
02034599	153	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
132e9906 MCA	154	"unin-pci-conf-data", 0x1000);
	155
	156	memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
	157	0x100000000ULL);
e226efbb MCA	158	memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
e226efbb MCA	159	"unin-pci-isa-mmio", 0x00800000);
132e9906	160
7b19318b MCA	161	memory_region_init_alias(&s->pci_hole, OBJECT(s),
	162	"unin-pci-hole", &s->pci_mmio,
	163	0x80000000ULL, 0x10000000ULL);
	164
e7755cc1 MCA	165	object_property_add_link(obj, "pic", TYPE_OPENPIC,
	166	(Object **) &s->pic,
	167	qdev_prop_allow_set_link_before_realize,
	168	0, NULL);
	169
02034599 MCA	170	sysbus_init_mmio(sbd, &h->conf_mem);
02034599 MCA	171	sysbus_init_mmio(sbd, &h->data_mem);
7b19318b	172	sysbus_init_mmio(sbd, &s->pci_hole);
e226efbb	173	sysbus_init_mmio(sbd, &s->pci_io);
2e29bd04 BS	174	}
2e29bd04 BS	175
32cde615 MCA	176	static void pci_u3_agp_realize(DeviceState dev, Error *errp)
	177	{
	178	UNINState *s = U3_AGP_HOST_BRIDGE(dev);
	179	PCIHostState *h = PCI_HOST_BRIDGE(dev);
	180
	181	h->bus = pci_register_root_bus(dev, NULL,
	182	pci_unin_set_irq, pci_unin_map_irq,
e7755cc1	183	s,
32cde615	184	&s->pci_mmio,
e226efbb	185	&s->pci_io,
32cde615 MCA	186	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
	187
	188	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
e7755cc1	189	pci_unin_init_irqs(s);
32cde615 MCA	190	}
32cde615 MCA	191
02034599	192	static void pci_u3_agp_init(Object *obj)
0f921197	193	{
132e9906	194	UNINState *s = U3_AGP_HOST_BRIDGE(obj);
02034599 MCA	195	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
02034599 MCA	196	PCIHostState *h = PCI_HOST_BRIDGE(obj);
0f921197 AG	197
0f921197 AG	198	/* Uninorth U3 AGP bus */
40c5dce9	199	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
132e9906	200	obj, "unin-pci-conf-idx", 0x1000);
02034599	201	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
132e9906 MCA	202	"unin-pci-conf-data", 0x1000);
	203
	204	memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
	205	0x100000000ULL);
e226efbb MCA	206	memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
e226efbb MCA	207	"unin-pci-isa-mmio", 0x00800000);
132e9906	208
8ce3f743 MCA	209	memory_region_init_alias(&s->pci_hole, OBJECT(s),
	210	"unin-pci-hole", &s->pci_mmio,
	211	0x80000000ULL, 0x70000000ULL);
	212
e7755cc1 MCA	213	object_property_add_link(obj, "pic", TYPE_OPENPIC,
	214	(Object **) &s->pic,
	215	qdev_prop_allow_set_link_before_realize,
	216	0, NULL);
	217
02034599 MCA	218	sysbus_init_mmio(sbd, &h->conf_mem);
02034599 MCA	219	sysbus_init_mmio(sbd, &h->data_mem);
8ce3f743	220	sysbus_init_mmio(sbd, &s->pci_hole);
e226efbb	221	sysbus_init_mmio(sbd, &s->pci_io);
0f921197 AG	222	}
0f921197 AG	223
32cde615 MCA	224	static void pci_unin_agp_realize(DeviceState dev, Error *errp)
	225	{
	226	UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
	227	PCIHostState *h = PCI_HOST_BRIDGE(dev);
	228
	229	h->bus = pci_register_root_bus(dev, NULL,
	230	pci_unin_set_irq, pci_unin_map_irq,
e7755cc1	231	s,
32cde615	232	&s->pci_mmio,
e226efbb	233	&s->pci_io,
32cde615	234	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
c1d66d37 MCA	235
c1d66d37 MCA	236	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
e7755cc1	237	pci_unin_init_irqs(s);
32cde615 MCA	238	}
32cde615 MCA	239
02034599	240	static void pci_unin_agp_init(Object *obj)
2e29bd04	241	{
e7755cc1	242	UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
02034599 MCA	243	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
02034599 MCA	244	PCIHostState *h = PCI_HOST_BRIDGE(obj);
2e29bd04 BS	245
2e29bd04 BS	246	/* Uninorth AGP bus */
40c5dce9	247	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
132e9906	248	obj, "unin-agp-conf-idx", 0x1000);
40c5dce9	249	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
132e9906	250	obj, "unin-agp-conf-data", 0x1000);
e7755cc1 MCA	251
	252	object_property_add_link(obj, "pic", TYPE_OPENPIC,
	253	(Object **) &s->pic,
	254	qdev_prop_allow_set_link_before_realize,
	255	0, NULL);
	256
02034599 MCA	257	sysbus_init_mmio(sbd, &h->conf_mem);
02034599 MCA	258	sysbus_init_mmio(sbd, &h->data_mem);
2e29bd04 BS	259	}
2e29bd04 BS	260
1ff861d2 MCA	261	static void pci_unin_internal_realize(DeviceState dev, Error *errp)
	262	{
	263	UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
	264	PCIHostState *h = PCI_HOST_BRIDGE(dev);
	265
	266	h->bus = pci_register_root_bus(dev, NULL,
	267	pci_unin_set_irq, pci_unin_map_irq,
e7755cc1	268	s,
1ff861d2	269	&s->pci_mmio,
e226efbb	270	&s->pci_io,
1ff861d2 MCA	271	PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
	272
	273	pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
e7755cc1	274	pci_unin_init_irqs(s);
1ff861d2 MCA	275	}
1ff861d2 MCA	276
02034599	277	static void pci_unin_internal_init(Object *obj)
2e29bd04	278	{
e7755cc1	279	UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
02034599 MCA	280	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
02034599 MCA	281	PCIHostState *h = PCI_HOST_BRIDGE(obj);
2e29bd04 BS	282
2e29bd04 BS	283	/* Uninorth internal bus */
40c5dce9	284	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
132e9906	285	obj, "unin-pci-conf-idx", 0x1000);
40c5dce9	286	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
132e9906	287	obj, "unin-pci-conf-data", 0x1000);
e7755cc1 MCA	288
	289	object_property_add_link(obj, "pic", TYPE_OPENPIC,
	290	(Object **) &s->pic,
	291	qdev_prop_allow_set_link_before_realize,
	292	0, NULL);
	293
02034599 MCA	294	sysbus_init_mmio(sbd, &h->conf_mem);
02034599 MCA	295	sysbus_init_mmio(sbd, &h->data_mem);
2e29bd04 BS	296	}
2e29bd04 BS	297
9af21dbe	298	static void unin_main_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	299	{
4d309c96 MCA	300	/* cache_line_size */
	301	d->config[0x0C] = 0x08;
	302	/* latency_timer */
	303	d->config[0x0D] = 0x10;
	304	/* capabilities_pointer */
	305	d->config[0x34] = 0x00;
4d309c96	306
98ae3b27 JA	307	/*
	308	* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
	309	* memory space with base 0x80000000, size 0x10000000 for Apple's
	310	* AppleMacRiscPCI driver
	311	*/
	312	d->config[0x48] = 0x0;
	313	d->config[0x49] = 0x0;
	314	d->config[0x4a] = 0x0;
	315	d->config[0x4b] = 0x1;
2e29bd04	316	}
502a5395	317
c1d66d37 MCA	318	static void unin_agp_pci_host_realize(PCIDevice d, Error *errp)
	319	{
	320	/* cache_line_size */
	321	d->config[0x0C] = 0x08;
	322	/* latency_timer */
	323	d->config[0x0D] = 0x10;
	324	/* capabilities_pointer
	325	d->config[0x34] = 0x80; */
	326	}
	327
9af21dbe	328	static void u3_agp_pci_host_realize(PCIDevice d, Error *errp)
0f921197	329	{
0f921197 AG	330	/* cache line size */
	331	d->config[0x0C] = 0x08;
	332	/* latency timer */
	333	d->config[0x0D] = 0x10;
0f921197 AG	334	}
0f921197 AG	335
9af21dbe	336	static void unin_internal_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	337	{
4d309c96 MCA	338	/* cache_line_size */
	339	d->config[0x0C] = 0x08;
	340	/* latency_timer */
	341	d->config[0x0D] = 0x10;
	342	/* capabilities_pointer */
	343	d->config[0x34] = 0x00;
2e29bd04 BS	344	}
2e29bd04 BS	345
40021f08 AL	346	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	347	{
	348	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	349	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	350
9af21dbe	351	k->realize = unin_main_pci_host_realize;
40021f08 AL	352	k->vendor_id = PCI_VENDOR_ID_APPLE;
	353	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	354	k->revision = 0x00;
	355	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	356	/*
	357	* PCI-facing part of the host bridge, not usable without the
	358	* host-facing part, which can't be device_add'ed, yet.
	359	*/
e90f2a8c	360	dc->user_creatable = false;
40021f08 AL	361	}
40021f08 AL	362
4240abff	363	static const TypeInfo unin_main_pci_host_info = {
40021f08	364	.name = "uni-north-pci",
39bffca2 AL	365	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	366	.instance_size = sizeof(PCIDevice),
40021f08	367	.class_init = unin_main_pci_host_class_init,
fd3b02c8 EH	368	.interfaces = (InterfaceInfo[]) {
	369	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	370	{ },
	371	},
2e29bd04 BS	372	};
2e29bd04 BS	373
40021f08 AL	374	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	375	{
	376	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	377	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	378
9af21dbe	379	k->realize = u3_agp_pci_host_realize;
40021f08 AL	380	k->vendor_id = PCI_VENDOR_ID_APPLE;
	381	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	382	k->revision = 0x00;
	383	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	384	/*
	385	* PCI-facing part of the host bridge, not usable without the
	386	* host-facing part, which can't be device_add'ed, yet.
	387	*/
e90f2a8c	388	dc->user_creatable = false;
40021f08 AL	389	}
40021f08 AL	390
4240abff	391	static const TypeInfo u3_agp_pci_host_info = {
40021f08	392	.name = "u3-agp",
39bffca2 AL	393	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	394	.instance_size = sizeof(PCIDevice),
40021f08	395	.class_init = u3_agp_pci_host_class_init,
fd3b02c8 EH	396	.interfaces = (InterfaceInfo[]) {
	397	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	398	{ },
	399	},
0f921197 AG	400	};
0f921197 AG	401
40021f08 AL	402	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	403	{
	404	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	405	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	406
9af21dbe	407	k->realize = unin_agp_pci_host_realize;
40021f08 AL	408	k->vendor_id = PCI_VENDOR_ID_APPLE;
	409	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	410	k->revision = 0x00;
	411	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	412	/*
	413	* PCI-facing part of the host bridge, not usable without the
	414	* host-facing part, which can't be device_add'ed, yet.
	415	*/
e90f2a8c	416	dc->user_creatable = false;
40021f08 AL	417	}
40021f08 AL	418
4240abff	419	static const TypeInfo unin_agp_pci_host_info = {
40021f08	420	.name = "uni-north-agp",
39bffca2 AL	421	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	422	.instance_size = sizeof(PCIDevice),
40021f08	423	.class_init = unin_agp_pci_host_class_init,
fd3b02c8 EH	424	.interfaces = (InterfaceInfo[]) {
	425	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	426	{ },
	427	},
2e29bd04 BS	428	};
2e29bd04 BS	429
40021f08 AL	430	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	431	{
	432	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	433	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	434
9af21dbe	435	k->realize = unin_internal_pci_host_realize;
40021f08 AL	436	k->vendor_id = PCI_VENDOR_ID_APPLE;
	437	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	438	k->revision = 0x00;
	439	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	440	/*
	441	* PCI-facing part of the host bridge, not usable without the
	442	* host-facing part, which can't be device_add'ed, yet.
	443	*/
e90f2a8c	444	dc->user_creatable = false;
40021f08 AL	445	}
40021f08 AL	446
4240abff	447	static const TypeInfo unin_internal_pci_host_info = {
40021f08	448	.name = "uni-north-internal-pci",
39bffca2 AL	449	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	450	.instance_size = sizeof(PCIDevice),
40021f08	451	.class_init = unin_internal_pci_host_class_init,
fd3b02c8 EH	452	.interfaces = (InterfaceInfo[]) {
	453	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	454	{ },
	455	},
2e29bd04 BS	456	};
2e29bd04 BS	457
999e12bb AL	458	static void pci_unin_main_class_init(ObjectClass klass, void data)
999e12bb AL	459	{
1d16f86a	460	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	461
32cde615	462	dc->realize = pci_unin_main_realize;
1d16f86a	463	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	464	}
999e12bb AL	465
4240abff	466	static const TypeInfo pci_unin_main_info = {
57fd7b7f	467	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	468	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2	469	.instance_size = sizeof(UNINState),
02034599	470	.instance_init = pci_unin_main_init,
39bffca2	471	.class_init = pci_unin_main_class_init,
70f9c987 AF	472	};
70f9c987 AF	473
999e12bb AL	474	static void pci_u3_agp_class_init(ObjectClass klass, void data)
999e12bb AL	475	{
1d16f86a	476	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	477
32cde615	478	dc->realize = pci_u3_agp_realize;
1d16f86a	479	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	480	}
999e12bb AL	481
4240abff	482	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	483	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	484	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2	485	.instance_size = sizeof(UNINState),
02034599	486	.instance_init = pci_u3_agp_init,
39bffca2	487	.class_init = pci_u3_agp_class_init,
70f9c987 AF	488	};
70f9c987 AF	489
999e12bb AL	490	static void pci_unin_agp_class_init(ObjectClass klass, void data)
999e12bb AL	491	{
1d16f86a	492	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	493
32cde615	494	dc->realize = pci_unin_agp_realize;
1d16f86a	495	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	496	}
999e12bb AL	497
4240abff	498	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	499	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	500	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2	501	.instance_size = sizeof(UNINState),
02034599	502	.instance_init = pci_unin_agp_init,
39bffca2	503	.class_init = pci_unin_agp_class_init,
70f9c987 AF	504	};
70f9c987 AF	505
999e12bb AL	506	static void pci_unin_internal_class_init(ObjectClass klass, void data)
999e12bb AL	507	{
1d16f86a	508	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	509
1ff861d2	510	dc->realize = pci_unin_internal_realize;
1d16f86a	511	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	512	}
999e12bb AL	513
4240abff	514	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	515	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	516	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2	517	.instance_size = sizeof(UNINState),
02034599	518	.instance_init = pci_unin_internal_init,
39bffca2	519	.class_init = pci_unin_internal_class_init,
70f9c987 AF	520	};
70f9c987 AF	521
83f7d43a	522	static void unin_register_types(void)
2e29bd04	523	{
39bffca2 AL	524	type_register_static(&unin_main_pci_host_info);
	525	type_register_static(&u3_agp_pci_host_info);
	526	type_register_static(&unin_agp_pci_host_info);
	527	type_register_static(&unin_internal_pci_host_info);
	528
	529	type_register_static(&pci_unin_main_info);
	530	type_register_static(&pci_u3_agp_info);
	531	type_register_static(&pci_unin_agp_info);
	532	type_register_static(&pci_unin_internal_info);
502a5395	533	}
2e29bd04	534
83f7d43a	535	type_init(unin_register_types)