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Commit | Line | Data |
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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the LGPL. |
502a5395 PB |
8 | */ |
9 | ||
83c9f4ca PB |
10 | #include "hw/sysbus.h" |
11 | #include "hw/pci/pci.h" | |
0688810b | 12 | #include "hw/pci/pci_bus.h" |
83c9f4ca | 13 | #include "hw/pci/pci_host.h" |
022c62cb | 14 | #include "exec/address-spaces.h" |
0027b06d | 15 | |
66a96d70 PM |
16 | /* Old and buggy versions of QEMU used the wrong mapping from |
17 | * PCI IRQs to system interrupt lines. Unfortunately the Linux | |
18 | * kernel also had the corresponding bug in setting up interrupts | |
19 | * (so older kernels work on QEMU and not on real hardware). | |
20 | * We automatically detect these broken kernels and flip back | |
21 | * to the broken irq mapping by spotting guest writes to the | |
22 | * PCI_INTERRUPT_LINE register to see where the guest thinks | |
23 | * interrupts are going to be routed. So we start in state | |
24 | * ASSUME_OK on reset, and transition to either BROKEN or | |
25 | * FORCE_OK at the first write to an INTERRUPT_LINE register for | |
26 | * a slot where broken and correct interrupt mapping would differ. | |
27 | * Once in either BROKEN or FORCE_OK we never transition again; | |
28 | * this allows a newer kernel to use the INTERRUPT_LINE | |
29 | * registers arbitrarily once it has indicated that it isn't | |
30 | * broken in its init code somewhere. | |
31 | */ | |
32 | enum { | |
33 | PCI_VPB_IRQMAP_ASSUME_OK, | |
34 | PCI_VPB_IRQMAP_BROKEN, | |
35 | PCI_VPB_IRQMAP_FORCE_OK, | |
36 | }; | |
37 | ||
0027b06d | 38 | typedef struct { |
0688810b PM |
39 | PCIHostState parent_obj; |
40 | ||
0027b06d | 41 | qemu_irq irq[4]; |
45de094e AK |
42 | MemoryRegion mem_config; |
43 | MemoryRegion mem_config2; | |
967c2607 PM |
44 | MemoryRegion pci_io_space; |
45 | MemoryRegion pci_io_window; | |
0688810b PM |
46 | PCIBus pci_bus; |
47 | PCIDevice pci_dev; | |
48 | ||
49 | /* Constant for life of device: */ | |
50 | int realview; | |
66a96d70 PM |
51 | |
52 | /* Variable state: */ | |
53 | uint8_t irq_mapping; | |
0027b06d | 54 | } PCIVPBState; |
502a5395 | 55 | |
cd93dbf3 PM |
56 | #define TYPE_VERSATILE_PCI "versatile_pci" |
57 | #define PCI_VPB(obj) \ | |
58 | OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI) | |
59 | ||
60 | #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host" | |
61 | #define PCI_VPB_HOST(obj) \ | |
62 | OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST) | |
63 | ||
a8170e5e | 64 | static inline uint32_t vpb_pci_config_addr(hwaddr addr) |
502a5395 | 65 | { |
80b3ada7 | 66 | return addr & 0xffffff; |
502a5395 PB |
67 | } |
68 | ||
a8170e5e | 69 | static void pci_vpb_config_write(void *opaque, hwaddr addr, |
45de094e | 70 | uint64_t val, unsigned size) |
502a5395 | 71 | { |
66a96d70 PM |
72 | PCIVPBState *s = opaque; |
73 | if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE | |
74 | && s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) { | |
75 | uint8_t devfn = addr >> 8; | |
76 | if ((PCI_SLOT(devfn) % PCI_NUM_PINS) != 2) { | |
77 | if (val == 27) { | |
78 | s->irq_mapping = PCI_VPB_IRQMAP_BROKEN; | |
79 | } else { | |
80 | s->irq_mapping = PCI_VPB_IRQMAP_FORCE_OK; | |
81 | } | |
82 | } | |
83 | } | |
84 | pci_data_write(&s->pci_bus, vpb_pci_config_addr(addr), val, size); | |
502a5395 PB |
85 | } |
86 | ||
a8170e5e | 87 | static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr, |
45de094e | 88 | unsigned size) |
502a5395 | 89 | { |
66a96d70 | 90 | PCIVPBState *s = opaque; |
502a5395 | 91 | uint32_t val; |
66a96d70 | 92 | val = pci_data_read(&s->pci_bus, vpb_pci_config_addr(addr), size); |
502a5395 PB |
93 | return val; |
94 | } | |
95 | ||
45de094e AK |
96 | static const MemoryRegionOps pci_vpb_config_ops = { |
97 | .read = pci_vpb_config_read, | |
98 | .write = pci_vpb_config_write, | |
99 | .endianness = DEVICE_NATIVE_ENDIAN, | |
502a5395 PB |
100 | }; |
101 | ||
d2b59317 PB |
102 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
103 | { | |
66a96d70 PM |
104 | PCIVPBState *s = container_of(d->bus, PCIVPBState, pci_bus); |
105 | ||
106 | if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) { | |
107 | /* Legacy broken IRQ mapping for compatibility with old and | |
108 | * buggy Linux guests | |
109 | */ | |
110 | return irq_num; | |
111 | } | |
112 | ||
113 | /* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane | |
114 | * name slot IntA IntB IntC IntD | |
115 | * A 31 IRQ28 IRQ29 IRQ30 IRQ27 | |
116 | * B 30 IRQ27 IRQ28 IRQ29 IRQ30 | |
117 | * C 29 IRQ30 IRQ27 IRQ28 IRQ29 | |
118 | * Slot C is for the host bridge; A and B the peripherals. | |
119 | * Our output irqs 0..3 correspond to the baseboard's 27..30. | |
120 | * | |
121 | * This mapping function takes account of an oddity in the PB926 | |
122 | * board wiring, where the FPGA's P_nINTA input is connected to | |
123 | * the INTB connection on the board PCI edge connector, P_nINTB | |
124 | * is connected to INTC, and so on, so everything is one number | |
125 | * further round from where you might expect. | |
126 | */ | |
127 | return pci_swizzle_map_irq_fn(d, irq_num + 2); | |
128 | } | |
129 | ||
130 | static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num) | |
131 | { | |
132 | /* Slot to IRQ mapping for RealView EB and PB1176 backplane | |
133 | * name slot IntA IntB IntC IntD | |
134 | * A 31 IRQ50 IRQ51 IRQ48 IRQ49 | |
135 | * B 30 IRQ49 IRQ50 IRQ51 IRQ48 | |
136 | * C 29 IRQ48 IRQ49 IRQ50 IRQ51 | |
137 | * Slot C is for the host bridge; A and B the peripherals. | |
138 | * Our output irqs 0..3 correspond to the baseboard's 48..51. | |
139 | * | |
140 | * The PB1176 and EB boards don't have the PB926 wiring oddity | |
141 | * described above; P_nINTA connects to INTA, P_nINTB to INTB | |
142 | * and so on, which is why this mapping function is different. | |
143 | */ | |
144 | return pci_swizzle_map_irq_fn(d, irq_num + 3); | |
d2b59317 PB |
145 | } |
146 | ||
5d4e84c8 | 147 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 148 | { |
5d4e84c8 JQ |
149 | qemu_irq *pic = opaque; |
150 | ||
97aff481 | 151 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
152 | } |
153 | ||
66a96d70 PM |
154 | static void pci_vpb_reset(DeviceState *d) |
155 | { | |
156 | PCIVPBState *s = PCI_VPB(d); | |
157 | ||
158 | s->irq_mapping = PCI_VPB_IRQMAP_ASSUME_OK; | |
159 | } | |
160 | ||
0688810b PM |
161 | static void pci_vpb_init(Object *obj) |
162 | { | |
163 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
164 | PCIVPBState *s = PCI_VPB(obj); | |
165 | ||
967c2607 PM |
166 | memory_region_init(&s->pci_io_space, "pci_io", 1ULL << 32); |
167 | ||
0688810b | 168 | pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), "pci", |
967c2607 | 169 | get_system_memory(), &s->pci_io_space, |
0688810b PM |
170 | PCI_DEVFN(11, 0), TYPE_PCI_BUS); |
171 | h->bus = &s->pci_bus; | |
172 | ||
173 | object_initialize(&s->pci_dev, TYPE_VERSATILE_PCI_HOST); | |
174 | qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus)); | |
5f37ef92 PM |
175 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(29, 0), "addr", |
176 | NULL); | |
0688810b PM |
177 | } |
178 | ||
cd93dbf3 | 179 | static void pci_vpb_realize(DeviceState *dev, Error **errp) |
0027b06d | 180 | { |
cd93dbf3 PM |
181 | PCIVPBState *s = PCI_VPB(dev); |
182 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
66a96d70 | 183 | pci_map_irq_fn mapfn; |
97aff481 | 184 | int i; |
e69954b9 | 185 | |
97aff481 | 186 | for (i = 0; i < 4; i++) { |
cd93dbf3 | 187 | sysbus_init_irq(sbd, &s->irq[i]); |
e69954b9 | 188 | } |
0688810b | 189 | |
66a96d70 PM |
190 | if (s->realview) { |
191 | mapfn = pci_vpb_rv_map_irq; | |
192 | } else { | |
193 | mapfn = pci_vpb_map_irq; | |
194 | } | |
195 | ||
196 | pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); | |
0027b06d | 197 | |
502a5395 PB |
198 | /* ??? Register memory space. */ |
199 | ||
7d6e771f PM |
200 | /* Our memory regions are: |
201 | * 0 : PCI self config window | |
202 | * 1 : PCI config window | |
5fb8084f | 203 | * 2 : PCI IO window |
7d6e771f | 204 | */ |
66a96d70 | 205 | memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, s, |
45de094e | 206 | "pci-vpb-selfconfig", 0x1000000); |
cd93dbf3 | 207 | sysbus_init_mmio(sbd, &s->mem_config); |
66a96d70 | 208 | memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, s, |
45de094e | 209 | "pci-vpb-config", 0x1000000); |
cd93dbf3 | 210 | sysbus_init_mmio(sbd, &s->mem_config2); |
967c2607 PM |
211 | |
212 | /* The window into I/O space is always into a fixed base address; | |
213 | * its size is the same for both realview and versatile. | |
214 | */ | |
215 | memory_region_init_alias(&s->pci_io_window, "pci-vbp-io-window", | |
216 | &s->pci_io_space, 0, 0x100000); | |
217 | ||
218 | sysbus_init_mmio(sbd, &s->pci_io_space); | |
45de094e | 219 | |
0688810b PM |
220 | /* TODO Remove once realize propagates to child devices. */ |
221 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); | |
0027b06d | 222 | } |
502a5395 | 223 | |
81a322d4 | 224 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 225 | { |
a408b1de | 226 | pci_set_word(d->config + PCI_STATUS, |
c5c86c53 | 227 | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); |
01764fe0 | 228 | pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); |
81a322d4 | 229 | return 0; |
0027b06d | 230 | } |
502a5395 | 231 | |
40021f08 AL |
232 | static void versatile_pci_host_class_init(ObjectClass *klass, void *data) |
233 | { | |
234 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
235 | ||
236 | k->init = versatile_pci_host_init; | |
237 | k->vendor_id = PCI_VENDOR_ID_XILINX; | |
238 | k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30; | |
239 | k->class_id = PCI_CLASS_PROCESSOR_CO; | |
240 | } | |
241 | ||
8c43a6f0 | 242 | static const TypeInfo versatile_pci_host_info = { |
cd93dbf3 | 243 | .name = TYPE_VERSATILE_PCI_HOST, |
39bffca2 AL |
244 | .parent = TYPE_PCI_DEVICE, |
245 | .instance_size = sizeof(PCIDevice), | |
246 | .class_init = versatile_pci_host_class_init, | |
0aab0d3a GH |
247 | }; |
248 | ||
999e12bb AL |
249 | static void pci_vpb_class_init(ObjectClass *klass, void *data) |
250 | { | |
cd93dbf3 | 251 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 252 | |
cd93dbf3 | 253 | dc->realize = pci_vpb_realize; |
66a96d70 | 254 | dc->reset = pci_vpb_reset; |
999e12bb AL |
255 | } |
256 | ||
8c43a6f0 | 257 | static const TypeInfo pci_vpb_info = { |
cd93dbf3 | 258 | .name = TYPE_VERSATILE_PCI, |
0688810b | 259 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 260 | .instance_size = sizeof(PCIVPBState), |
0688810b | 261 | .instance_init = pci_vpb_init, |
39bffca2 | 262 | .class_init = pci_vpb_class_init, |
999e12bb AL |
263 | }; |
264 | ||
cd93dbf3 | 265 | static void pci_realview_init(Object *obj) |
999e12bb | 266 | { |
cd93dbf3 | 267 | PCIVPBState *s = PCI_VPB(obj); |
999e12bb | 268 | |
cd93dbf3 | 269 | s->realview = 1; |
999e12bb AL |
270 | } |
271 | ||
8c43a6f0 | 272 | static const TypeInfo pci_realview_info = { |
39bffca2 | 273 | .name = "realview_pci", |
cd93dbf3 PM |
274 | .parent = TYPE_VERSATILE_PCI, |
275 | .instance_init = pci_realview_init, | |
999e12bb AL |
276 | }; |
277 | ||
83f7d43a | 278 | static void versatile_pci_register_types(void) |
0027b06d | 279 | { |
39bffca2 AL |
280 | type_register_static(&pci_vpb_info); |
281 | type_register_static(&pci_realview_info); | |
282 | type_register_static(&versatile_pci_host_info); | |
502a5395 | 283 | } |
0027b06d | 284 | |
83f7d43a | 285 | type_init(versatile_pci_register_types) |