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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the LGPL. |
502a5395 PB |
8 | */ |
9 | ||
83c9f4ca PB |
10 | #include "hw/sysbus.h" |
11 | #include "hw/pci/pci.h" | |
0688810b | 12 | #include "hw/pci/pci_bus.h" |
83c9f4ca | 13 | #include "hw/pci/pci_host.h" |
022c62cb | 14 | #include "exec/address-spaces.h" |
0027b06d | 15 | |
66a96d70 PM |
16 | /* Old and buggy versions of QEMU used the wrong mapping from |
17 | * PCI IRQs to system interrupt lines. Unfortunately the Linux | |
18 | * kernel also had the corresponding bug in setting up interrupts | |
19 | * (so older kernels work on QEMU and not on real hardware). | |
20 | * We automatically detect these broken kernels and flip back | |
21 | * to the broken irq mapping by spotting guest writes to the | |
22 | * PCI_INTERRUPT_LINE register to see where the guest thinks | |
23 | * interrupts are going to be routed. So we start in state | |
24 | * ASSUME_OK on reset, and transition to either BROKEN or | |
25 | * FORCE_OK at the first write to an INTERRUPT_LINE register for | |
26 | * a slot where broken and correct interrupt mapping would differ. | |
27 | * Once in either BROKEN or FORCE_OK we never transition again; | |
28 | * this allows a newer kernel to use the INTERRUPT_LINE | |
29 | * registers arbitrarily once it has indicated that it isn't | |
30 | * broken in its init code somewhere. | |
bc04d891 PM |
31 | * |
32 | * Unfortunately we have to cope with multiple different | |
33 | * variants on the broken kernel behaviour: | |
34 | * phase I (before kernel commit 1bc39ac5d) kernels assume old | |
35 | * QEMU behaviour, so they use IRQ 27 for all slots | |
36 | * phase II (1bc39ac5d and later, but before e3e92a7be6) kernels | |
37 | * swizzle IRQs between slots, but do it wrongly, so they | |
38 | * work only for every fourth PCI card, and only if (like old | |
39 | * QEMU) the PCI host device is at slot 0 rather than where | |
40 | * the h/w actually puts it | |
41 | * phase III (e3e92a7be6 and later) kernels still swizzle IRQs between | |
42 | * slots wrongly, but add a fixed offset of 64 to everything | |
43 | * they write to PCI_INTERRUPT_LINE. | |
44 | * | |
45 | * We live in hope of a mythical phase IV kernel which might | |
46 | * actually behave in ways that work on the hardware. Such a | |
47 | * kernel should probably start off by writing some value neither | |
48 | * 27 nor 91 to slot zero's PCI_INTERRUPT_LINE register to | |
49 | * disable the autodetection. After that it can do what it likes. | |
50 | * | |
51 | * Slot % 4 | hw | I | II | III | |
52 | * ------------------------------- | |
53 | * 0 | 29 | 27 | 27 | 91 | |
54 | * 1 | 30 | 27 | 28 | 92 | |
55 | * 2 | 27 | 27 | 29 | 93 | |
56 | * 3 | 28 | 27 | 30 | 94 | |
66a96d70 PM |
57 | */ |
58 | enum { | |
59 | PCI_VPB_IRQMAP_ASSUME_OK, | |
60 | PCI_VPB_IRQMAP_BROKEN, | |
61 | PCI_VPB_IRQMAP_FORCE_OK, | |
62 | }; | |
63 | ||
0027b06d | 64 | typedef struct { |
0688810b PM |
65 | PCIHostState parent_obj; |
66 | ||
0027b06d | 67 | qemu_irq irq[4]; |
7468d73a | 68 | MemoryRegion controlregs; |
45de094e AK |
69 | MemoryRegion mem_config; |
70 | MemoryRegion mem_config2; | |
89a32d32 | 71 | /* Containers representing the PCI address spaces */ |
967c2607 | 72 | MemoryRegion pci_io_space; |
89a32d32 PM |
73 | MemoryRegion pci_mem_space; |
74 | /* Alias regions into PCI address spaces which we expose as sysbus regions. | |
75 | * The offsets into pci_mem_space are controlled by the imap registers. | |
76 | */ | |
967c2607 | 77 | MemoryRegion pci_io_window; |
89a32d32 | 78 | MemoryRegion pci_mem_window[3]; |
0688810b PM |
79 | PCIBus pci_bus; |
80 | PCIDevice pci_dev; | |
81 | ||
82 | /* Constant for life of device: */ | |
83 | int realview; | |
89a32d32 | 84 | uint32_t mem_win_size[3]; |
66a96d70 PM |
85 | |
86 | /* Variable state: */ | |
7468d73a PM |
87 | uint32_t imap[3]; |
88 | uint32_t smap[3]; | |
89 | uint32_t selfid; | |
90 | uint32_t flags; | |
66a96d70 | 91 | uint8_t irq_mapping; |
0027b06d | 92 | } PCIVPBState; |
502a5395 | 93 | |
89a32d32 PM |
94 | static void pci_vpb_update_window(PCIVPBState *s, int i) |
95 | { | |
96 | /* Adjust the offset of the alias region we use for | |
97 | * the memory window i to account for a change in the | |
98 | * value of the corresponding IMAP register. | |
99 | * Note that the semantics of the IMAP register differ | |
100 | * for realview and versatile variants of the controller. | |
101 | */ | |
102 | hwaddr offset; | |
103 | if (s->realview) { | |
104 | /* Top bits of register (masked according to window size) provide | |
105 | * top bits of PCI address. | |
106 | */ | |
107 | offset = s->imap[i] & ~(s->mem_win_size[i] - 1); | |
108 | } else { | |
109 | /* Bottom 4 bits of register provide top 4 bits of PCI address */ | |
110 | offset = s->imap[i] << 28; | |
111 | } | |
112 | memory_region_set_alias_offset(&s->pci_mem_window[i], offset); | |
113 | } | |
114 | ||
115 | static void pci_vpb_update_all_windows(PCIVPBState *s) | |
116 | { | |
117 | /* Update all alias windows based on the current register state */ | |
118 | int i; | |
119 | ||
120 | for (i = 0; i < 3; i++) { | |
121 | pci_vpb_update_window(s, i); | |
122 | } | |
123 | } | |
124 | ||
125 | static int pci_vpb_post_load(void *opaque, int version_id) | |
126 | { | |
127 | PCIVPBState *s = opaque; | |
128 | pci_vpb_update_all_windows(s); | |
129 | return 0; | |
130 | } | |
131 | ||
7468d73a PM |
132 | static const VMStateDescription pci_vpb_vmstate = { |
133 | .name = "versatile-pci", | |
134 | .version_id = 1, | |
135 | .minimum_version_id = 1, | |
89a32d32 | 136 | .post_load = pci_vpb_post_load, |
7468d73a PM |
137 | .fields = (VMStateField[]) { |
138 | VMSTATE_UINT32_ARRAY(imap, PCIVPBState, 3), | |
139 | VMSTATE_UINT32_ARRAY(smap, PCIVPBState, 3), | |
140 | VMSTATE_UINT32(selfid, PCIVPBState), | |
141 | VMSTATE_UINT32(flags, PCIVPBState), | |
142 | VMSTATE_UINT8(irq_mapping, PCIVPBState), | |
143 | VMSTATE_END_OF_LIST() | |
144 | } | |
145 | }; | |
146 | ||
cd93dbf3 PM |
147 | #define TYPE_VERSATILE_PCI "versatile_pci" |
148 | #define PCI_VPB(obj) \ | |
149 | OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI) | |
150 | ||
151 | #define TYPE_VERSATILE_PCI_HOST "versatile_pci_host" | |
152 | #define PCI_VPB_HOST(obj) \ | |
153 | OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST) | |
154 | ||
7468d73a PM |
155 | typedef enum { |
156 | PCI_IMAP0 = 0x0, | |
157 | PCI_IMAP1 = 0x4, | |
158 | PCI_IMAP2 = 0x8, | |
159 | PCI_SELFID = 0xc, | |
160 | PCI_FLAGS = 0x10, | |
161 | PCI_SMAP0 = 0x14, | |
162 | PCI_SMAP1 = 0x18, | |
163 | PCI_SMAP2 = 0x1c, | |
164 | } PCIVPBControlRegs; | |
165 | ||
166 | static void pci_vpb_reg_write(void *opaque, hwaddr addr, | |
167 | uint64_t val, unsigned size) | |
168 | { | |
169 | PCIVPBState *s = opaque; | |
170 | ||
171 | switch (addr) { | |
172 | case PCI_IMAP0: | |
173 | case PCI_IMAP1: | |
174 | case PCI_IMAP2: | |
175 | { | |
176 | int win = (addr - PCI_IMAP0) >> 2; | |
177 | s->imap[win] = val; | |
89a32d32 | 178 | pci_vpb_update_window(s, win); |
7468d73a PM |
179 | break; |
180 | } | |
181 | case PCI_SELFID: | |
182 | s->selfid = val; | |
183 | break; | |
184 | case PCI_FLAGS: | |
185 | s->flags = val; | |
186 | break; | |
187 | case PCI_SMAP0: | |
188 | case PCI_SMAP1: | |
189 | case PCI_SMAP2: | |
190 | { | |
191 | int win = (addr - PCI_SMAP0) >> 2; | |
192 | s->smap[win] = val; | |
193 | break; | |
194 | } | |
195 | default: | |
196 | qemu_log_mask(LOG_GUEST_ERROR, | |
197 | "pci_vpb_reg_write: Bad offset %x\n", (int)addr); | |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
202 | static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr, | |
203 | unsigned size) | |
204 | { | |
205 | PCIVPBState *s = opaque; | |
206 | ||
207 | switch (addr) { | |
208 | case PCI_IMAP0: | |
209 | case PCI_IMAP1: | |
210 | case PCI_IMAP2: | |
211 | { | |
212 | int win = (addr - PCI_IMAP0) >> 2; | |
213 | return s->imap[win]; | |
214 | } | |
215 | case PCI_SELFID: | |
216 | return s->selfid; | |
217 | case PCI_FLAGS: | |
218 | return s->flags; | |
219 | case PCI_SMAP0: | |
220 | case PCI_SMAP1: | |
221 | case PCI_SMAP2: | |
222 | { | |
223 | int win = (addr - PCI_SMAP0) >> 2; | |
224 | return s->smap[win]; | |
225 | } | |
226 | default: | |
227 | qemu_log_mask(LOG_GUEST_ERROR, | |
228 | "pci_vpb_reg_read: Bad offset %x\n", (int)addr); | |
229 | return 0; | |
230 | } | |
231 | } | |
232 | ||
233 | static const MemoryRegionOps pci_vpb_reg_ops = { | |
234 | .read = pci_vpb_reg_read, | |
235 | .write = pci_vpb_reg_write, | |
236 | .endianness = DEVICE_NATIVE_ENDIAN, | |
237 | .valid = { | |
238 | .min_access_size = 4, | |
239 | .max_access_size = 4, | |
240 | }, | |
241 | }; | |
242 | ||
bc04d891 PM |
243 | static int pci_vpb_broken_irq(int slot, int irq) |
244 | { | |
245 | /* Determine whether this IRQ value for this slot represents a | |
246 | * known broken Linux kernel behaviour for this slot. | |
247 | * Return one of the PCI_VPB_IRQMAP_ constants: | |
248 | * BROKEN : if this definitely looks like a broken kernel | |
249 | * FORCE_OK : if this definitely looks good | |
250 | * ASSUME_OK : if we can't tell | |
251 | */ | |
252 | slot %= PCI_NUM_PINS; | |
253 | ||
254 | if (irq == 27) { | |
255 | if (slot == 2) { | |
256 | /* Might be a Phase I kernel, or might be a fixed kernel, | |
257 | * since slot 2 is where we expect this IRQ. | |
258 | */ | |
259 | return PCI_VPB_IRQMAP_ASSUME_OK; | |
260 | } | |
261 | /* Phase I kernel */ | |
262 | return PCI_VPB_IRQMAP_BROKEN; | |
263 | } | |
264 | if (irq == slot + 27) { | |
265 | /* Phase II kernel */ | |
266 | return PCI_VPB_IRQMAP_BROKEN; | |
267 | } | |
268 | if (irq == slot + 27 + 64) { | |
269 | /* Phase III kernel */ | |
270 | return PCI_VPB_IRQMAP_BROKEN; | |
271 | } | |
272 | /* Anything else must be a fixed kernel, possibly using an | |
273 | * arbitrary irq map. | |
274 | */ | |
275 | return PCI_VPB_IRQMAP_FORCE_OK; | |
276 | } | |
277 | ||
a8170e5e | 278 | static void pci_vpb_config_write(void *opaque, hwaddr addr, |
45de094e | 279 | uint64_t val, unsigned size) |
502a5395 | 280 | { |
66a96d70 PM |
281 | PCIVPBState *s = opaque; |
282 | if (!s->realview && (addr & 0xff) == PCI_INTERRUPT_LINE | |
283 | && s->irq_mapping == PCI_VPB_IRQMAP_ASSUME_OK) { | |
284 | uint8_t devfn = addr >> 8; | |
bc04d891 | 285 | s->irq_mapping = pci_vpb_broken_irq(PCI_SLOT(devfn), val); |
66a96d70 | 286 | } |
af9277e6 | 287 | pci_data_write(&s->pci_bus, addr, val, size); |
502a5395 PB |
288 | } |
289 | ||
a8170e5e | 290 | static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr, |
45de094e | 291 | unsigned size) |
502a5395 | 292 | { |
66a96d70 | 293 | PCIVPBState *s = opaque; |
502a5395 | 294 | uint32_t val; |
af9277e6 | 295 | val = pci_data_read(&s->pci_bus, addr, size); |
502a5395 PB |
296 | return val; |
297 | } | |
298 | ||
45de094e AK |
299 | static const MemoryRegionOps pci_vpb_config_ops = { |
300 | .read = pci_vpb_config_read, | |
301 | .write = pci_vpb_config_write, | |
302 | .endianness = DEVICE_NATIVE_ENDIAN, | |
502a5395 PB |
303 | }; |
304 | ||
d2b59317 PB |
305 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
306 | { | |
66a96d70 PM |
307 | PCIVPBState *s = container_of(d->bus, PCIVPBState, pci_bus); |
308 | ||
309 | if (s->irq_mapping == PCI_VPB_IRQMAP_BROKEN) { | |
310 | /* Legacy broken IRQ mapping for compatibility with old and | |
311 | * buggy Linux guests | |
312 | */ | |
313 | return irq_num; | |
314 | } | |
315 | ||
316 | /* Slot to IRQ mapping for RealView Platform Baseboard 926 backplane | |
317 | * name slot IntA IntB IntC IntD | |
318 | * A 31 IRQ28 IRQ29 IRQ30 IRQ27 | |
319 | * B 30 IRQ27 IRQ28 IRQ29 IRQ30 | |
320 | * C 29 IRQ30 IRQ27 IRQ28 IRQ29 | |
321 | * Slot C is for the host bridge; A and B the peripherals. | |
322 | * Our output irqs 0..3 correspond to the baseboard's 27..30. | |
323 | * | |
324 | * This mapping function takes account of an oddity in the PB926 | |
325 | * board wiring, where the FPGA's P_nINTA input is connected to | |
326 | * the INTB connection on the board PCI edge connector, P_nINTB | |
327 | * is connected to INTC, and so on, so everything is one number | |
328 | * further round from where you might expect. | |
329 | */ | |
330 | return pci_swizzle_map_irq_fn(d, irq_num + 2); | |
331 | } | |
332 | ||
333 | static int pci_vpb_rv_map_irq(PCIDevice *d, int irq_num) | |
334 | { | |
335 | /* Slot to IRQ mapping for RealView EB and PB1176 backplane | |
336 | * name slot IntA IntB IntC IntD | |
337 | * A 31 IRQ50 IRQ51 IRQ48 IRQ49 | |
338 | * B 30 IRQ49 IRQ50 IRQ51 IRQ48 | |
339 | * C 29 IRQ48 IRQ49 IRQ50 IRQ51 | |
340 | * Slot C is for the host bridge; A and B the peripherals. | |
341 | * Our output irqs 0..3 correspond to the baseboard's 48..51. | |
342 | * | |
343 | * The PB1176 and EB boards don't have the PB926 wiring oddity | |
344 | * described above; P_nINTA connects to INTA, P_nINTB to INTB | |
345 | * and so on, which is why this mapping function is different. | |
346 | */ | |
347 | return pci_swizzle_map_irq_fn(d, irq_num + 3); | |
d2b59317 PB |
348 | } |
349 | ||
5d4e84c8 | 350 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 351 | { |
5d4e84c8 JQ |
352 | qemu_irq *pic = opaque; |
353 | ||
97aff481 | 354 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
355 | } |
356 | ||
66a96d70 PM |
357 | static void pci_vpb_reset(DeviceState *d) |
358 | { | |
359 | PCIVPBState *s = PCI_VPB(d); | |
360 | ||
7468d73a PM |
361 | s->imap[0] = 0; |
362 | s->imap[1] = 0; | |
363 | s->imap[2] = 0; | |
364 | s->smap[0] = 0; | |
365 | s->smap[1] = 0; | |
366 | s->smap[2] = 0; | |
367 | s->selfid = 0; | |
368 | s->flags = 0; | |
66a96d70 | 369 | s->irq_mapping = PCI_VPB_IRQMAP_ASSUME_OK; |
89a32d32 PM |
370 | |
371 | pci_vpb_update_all_windows(s); | |
66a96d70 PM |
372 | } |
373 | ||
0688810b PM |
374 | static void pci_vpb_init(Object *obj) |
375 | { | |
376 | PCIHostState *h = PCI_HOST_BRIDGE(obj); | |
377 | PCIVPBState *s = PCI_VPB(obj); | |
378 | ||
967c2607 | 379 | memory_region_init(&s->pci_io_space, "pci_io", 1ULL << 32); |
89a32d32 | 380 | memory_region_init(&s->pci_mem_space, "pci_mem", 1ULL << 32); |
967c2607 | 381 | |
0688810b | 382 | pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), "pci", |
89a32d32 | 383 | &s->pci_mem_space, &s->pci_io_space, |
0688810b PM |
384 | PCI_DEVFN(11, 0), TYPE_PCI_BUS); |
385 | h->bus = &s->pci_bus; | |
386 | ||
387 | object_initialize(&s->pci_dev, TYPE_VERSATILE_PCI_HOST); | |
388 | qdev_set_parent_bus(DEVICE(&s->pci_dev), BUS(&s->pci_bus)); | |
89a32d32 PM |
389 | |
390 | /* Window sizes for VersatilePB; realview_pci's init will override */ | |
391 | s->mem_win_size[0] = 0x0c000000; | |
392 | s->mem_win_size[1] = 0x10000000; | |
393 | s->mem_win_size[2] = 0x10000000; | |
0688810b PM |
394 | } |
395 | ||
cd93dbf3 | 396 | static void pci_vpb_realize(DeviceState *dev, Error **errp) |
0027b06d | 397 | { |
cd93dbf3 PM |
398 | PCIVPBState *s = PCI_VPB(dev); |
399 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
66a96d70 | 400 | pci_map_irq_fn mapfn; |
97aff481 | 401 | int i; |
e69954b9 | 402 | |
97aff481 | 403 | for (i = 0; i < 4; i++) { |
cd93dbf3 | 404 | sysbus_init_irq(sbd, &s->irq[i]); |
e69954b9 | 405 | } |
0688810b | 406 | |
66a96d70 PM |
407 | if (s->realview) { |
408 | mapfn = pci_vpb_rv_map_irq; | |
409 | } else { | |
410 | mapfn = pci_vpb_map_irq; | |
411 | } | |
412 | ||
413 | pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); | |
0027b06d | 414 | |
7d6e771f | 415 | /* Our memory regions are: |
7468d73a PM |
416 | * 0 : our control registers |
417 | * 1 : PCI self config window | |
418 | * 2 : PCI config window | |
419 | * 3 : PCI IO window | |
89a32d32 | 420 | * 4..6 : PCI memory windows |
7d6e771f | 421 | */ |
7468d73a PM |
422 | memory_region_init_io(&s->controlregs, &pci_vpb_reg_ops, s, "pci-vpb-regs", |
423 | 0x1000); | |
424 | sysbus_init_mmio(sbd, &s->controlregs); | |
66a96d70 | 425 | memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, s, |
45de094e | 426 | "pci-vpb-selfconfig", 0x1000000); |
cd93dbf3 | 427 | sysbus_init_mmio(sbd, &s->mem_config); |
66a96d70 | 428 | memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, s, |
45de094e | 429 | "pci-vpb-config", 0x1000000); |
cd93dbf3 | 430 | sysbus_init_mmio(sbd, &s->mem_config2); |
967c2607 PM |
431 | |
432 | /* The window into I/O space is always into a fixed base address; | |
433 | * its size is the same for both realview and versatile. | |
434 | */ | |
435 | memory_region_init_alias(&s->pci_io_window, "pci-vbp-io-window", | |
436 | &s->pci_io_space, 0, 0x100000); | |
437 | ||
438 | sysbus_init_mmio(sbd, &s->pci_io_space); | |
45de094e | 439 | |
89a32d32 PM |
440 | /* Create the alias regions corresponding to our three windows onto |
441 | * PCI memory space. The sizes vary from board to board; the base | |
442 | * offsets are guest controllable via the IMAP registers. | |
443 | */ | |
444 | for (i = 0; i < 3; i++) { | |
445 | memory_region_init_alias(&s->pci_mem_window[i], "pci-vbp-window", | |
446 | &s->pci_mem_space, 0, s->mem_win_size[i]); | |
447 | sysbus_init_mmio(sbd, &s->pci_mem_window[i]); | |
448 | } | |
449 | ||
0688810b PM |
450 | /* TODO Remove once realize propagates to child devices. */ |
451 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp); | |
0027b06d | 452 | } |
502a5395 | 453 | |
81a322d4 | 454 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 455 | { |
a408b1de | 456 | pci_set_word(d->config + PCI_STATUS, |
c5c86c53 | 457 | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); |
01764fe0 | 458 | pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); |
81a322d4 | 459 | return 0; |
0027b06d | 460 | } |
502a5395 | 461 | |
40021f08 AL |
462 | static void versatile_pci_host_class_init(ObjectClass *klass, void *data) |
463 | { | |
464 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
465 | ||
466 | k->init = versatile_pci_host_init; | |
467 | k->vendor_id = PCI_VENDOR_ID_XILINX; | |
468 | k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30; | |
469 | k->class_id = PCI_CLASS_PROCESSOR_CO; | |
470 | } | |
471 | ||
8c43a6f0 | 472 | static const TypeInfo versatile_pci_host_info = { |
cd93dbf3 | 473 | .name = TYPE_VERSATILE_PCI_HOST, |
39bffca2 AL |
474 | .parent = TYPE_PCI_DEVICE, |
475 | .instance_size = sizeof(PCIDevice), | |
476 | .class_init = versatile_pci_host_class_init, | |
0aab0d3a GH |
477 | }; |
478 | ||
999e12bb AL |
479 | static void pci_vpb_class_init(ObjectClass *klass, void *data) |
480 | { | |
cd93dbf3 | 481 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 482 | |
cd93dbf3 | 483 | dc->realize = pci_vpb_realize; |
66a96d70 | 484 | dc->reset = pci_vpb_reset; |
7468d73a | 485 | dc->vmsd = &pci_vpb_vmstate; |
999e12bb AL |
486 | } |
487 | ||
8c43a6f0 | 488 | static const TypeInfo pci_vpb_info = { |
cd93dbf3 | 489 | .name = TYPE_VERSATILE_PCI, |
0688810b | 490 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 491 | .instance_size = sizeof(PCIVPBState), |
0688810b | 492 | .instance_init = pci_vpb_init, |
39bffca2 | 493 | .class_init = pci_vpb_class_init, |
999e12bb AL |
494 | }; |
495 | ||
cd93dbf3 | 496 | static void pci_realview_init(Object *obj) |
999e12bb | 497 | { |
cd93dbf3 | 498 | PCIVPBState *s = PCI_VPB(obj); |
999e12bb | 499 | |
cd93dbf3 | 500 | s->realview = 1; |
89a32d32 PM |
501 | /* The PCI window sizes are different on Realview boards */ |
502 | s->mem_win_size[0] = 0x01000000; | |
503 | s->mem_win_size[1] = 0x04000000; | |
504 | s->mem_win_size[2] = 0x08000000; | |
999e12bb AL |
505 | } |
506 | ||
8c43a6f0 | 507 | static const TypeInfo pci_realview_info = { |
39bffca2 | 508 | .name = "realview_pci", |
cd93dbf3 PM |
509 | .parent = TYPE_VERSATILE_PCI, |
510 | .instance_init = pci_realview_init, | |
999e12bb AL |
511 | }; |
512 | ||
83f7d43a | 513 | static void versatile_pci_register_types(void) |
0027b06d | 514 | { |
39bffca2 AL |
515 | type_register_static(&pci_vpb_info); |
516 | type_register_static(&pci_realview_info); | |
517 | type_register_static(&versatile_pci_host_info); | |
502a5395 | 518 | } |
0027b06d | 519 | |
83f7d43a | 520 | type_init(versatile_pci_register_types) |