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versatile_pci: Update to realize and instance init functions
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5fafdf24 1/*
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2 * ARM Versatile/PB PCI host controller
3 *
0027b06d 4 * Copyright (c) 2006-2009 CodeSourcery.
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5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the LGPL.
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8 */
9
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10#include "hw/sysbus.h"
11#include "hw/pci/pci.h"
12#include "hw/pci/pci_host.h"
022c62cb 13#include "exec/address-spaces.h"
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14
15typedef struct {
16 SysBusDevice busdev;
17 qemu_irq irq[4];
18 int realview;
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19 MemoryRegion mem_config;
20 MemoryRegion mem_config2;
21 MemoryRegion isa;
0027b06d 22} PCIVPBState;
502a5395 23
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24#define TYPE_VERSATILE_PCI "versatile_pci"
25#define PCI_VPB(obj) \
26 OBJECT_CHECK(PCIVPBState, (obj), TYPE_VERSATILE_PCI)
27
28#define TYPE_VERSATILE_PCI_HOST "versatile_pci_host"
29#define PCI_VPB_HOST(obj) \
30 OBJECT_CHECK(PCIDevice, (obj), TYPE_VERSATILE_PCIHOST)
31
a8170e5e 32static inline uint32_t vpb_pci_config_addr(hwaddr addr)
502a5395 33{
80b3ada7 34 return addr & 0xffffff;
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35}
36
a8170e5e 37static void pci_vpb_config_write(void *opaque, hwaddr addr,
45de094e 38 uint64_t val, unsigned size)
502a5395 39{
45de094e 40 pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
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41}
42
a8170e5e 43static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
45de094e 44 unsigned size)
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45{
46 uint32_t val;
45de094e 47 val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
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48 return val;
49}
50
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51static const MemoryRegionOps pci_vpb_config_ops = {
52 .read = pci_vpb_config_read,
53 .write = pci_vpb_config_write,
54 .endianness = DEVICE_NATIVE_ENDIAN,
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55};
56
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57static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
58{
59 return irq_num;
60}
61
5d4e84c8 62static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
502a5395 63{
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64 qemu_irq *pic = opaque;
65
97aff481 66 qemu_set_irq(pic[irq_num], level);
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67}
68
cd93dbf3 69static void pci_vpb_realize(DeviceState *dev, Error **errp)
0027b06d 70{
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71 PCIVPBState *s = PCI_VPB(dev);
72 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
0027b06d 73 PCIBus *bus;
97aff481 74 int i;
e69954b9 75
97aff481 76 for (i = 0; i < 4; i++) {
cd93dbf3 77 sysbus_init_irq(sbd, &s->irq[i]);
e69954b9 78 }
cd93dbf3 79 bus = pci_register_bus(dev, "pci",
02e2da45 80 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
aee97b84 81 get_system_memory(), get_system_io(),
60a0e443 82 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
0027b06d 83
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84 /* ??? Register memory space. */
85
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86 /* Our memory regions are:
87 * 0 : PCI self config window
88 * 1 : PCI config window
5fb8084f 89 * 2 : PCI IO window
7d6e771f 90 */
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91 memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
92 "pci-vpb-selfconfig", 0x1000000);
cd93dbf3 93 sysbus_init_mmio(sbd, &s->mem_config);
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94 memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
95 "pci-vpb-config", 0x1000000);
cd93dbf3 96 sysbus_init_mmio(sbd, &s->mem_config2);
5fb8084f 97 isa_mmio_setup(&s->isa, 0x0100000);
cd93dbf3 98 sysbus_init_mmio(sbd, &s->isa);
45de094e 99
0027b06d 100 pci_create_simple(bus, -1, "versatile_pci_host");
0027b06d 101}
502a5395 102
81a322d4 103static int versatile_pci_host_init(PCIDevice *d)
0027b06d 104{
a408b1de 105 pci_set_word(d->config + PCI_STATUS,
c5c86c53 106 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
01764fe0 107 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
81a322d4 108 return 0;
0027b06d 109}
502a5395 110
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111static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
112{
113 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
114
115 k->init = versatile_pci_host_init;
116 k->vendor_id = PCI_VENDOR_ID_XILINX;
117 k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
118 k->class_id = PCI_CLASS_PROCESSOR_CO;
119}
120
8c43a6f0 121static const TypeInfo versatile_pci_host_info = {
cd93dbf3 122 .name = TYPE_VERSATILE_PCI_HOST,
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123 .parent = TYPE_PCI_DEVICE,
124 .instance_size = sizeof(PCIDevice),
125 .class_init = versatile_pci_host_class_init,
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126};
127
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128static void pci_vpb_class_init(ObjectClass *klass, void *data)
129{
cd93dbf3 130 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 131
cd93dbf3 132 dc->realize = pci_vpb_realize;
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133}
134
8c43a6f0 135static const TypeInfo pci_vpb_info = {
cd93dbf3 136 .name = TYPE_VERSATILE_PCI,
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137 .parent = TYPE_SYS_BUS_DEVICE,
138 .instance_size = sizeof(PCIVPBState),
139 .class_init = pci_vpb_class_init,
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140};
141
cd93dbf3 142static void pci_realview_init(Object *obj)
999e12bb 143{
cd93dbf3 144 PCIVPBState *s = PCI_VPB(obj);
999e12bb 145
cd93dbf3 146 s->realview = 1;
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147}
148
8c43a6f0 149static const TypeInfo pci_realview_info = {
39bffca2 150 .name = "realview_pci",
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151 .parent = TYPE_VERSATILE_PCI,
152 .instance_init = pci_realview_init,
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153};
154
83f7d43a 155static void versatile_pci_register_types(void)
0027b06d 156{
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157 type_register_static(&pci_vpb_info);
158 type_register_static(&pci_realview_info);
159 type_register_static(&versatile_pci_host_info);
502a5395 160}
0027b06d 161
83f7d43a 162type_init(versatile_pci_register_types)