]>
Commit | Line | Data |
---|---|---|
69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
376253ec | 26 | #include "monitor.h" |
87ecb68b | 27 | #include "net.h" |
880345c4 | 28 | #include "sysemu.h" |
c2039bd0 | 29 | #include "loader.h" |
163c8a59 | 30 | #include "qemu-objects.h" |
69b91039 FB |
31 | |
32 | //#define DEBUG_PCI | |
d8d2e079 | 33 | #ifdef DEBUG_PCI |
2e49d64a | 34 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
35 | #else |
36 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
37 | #endif | |
69b91039 | 38 | |
30468f78 | 39 | struct PCIBus { |
02e2da45 | 40 | BusState qbus; |
30468f78 | 41 | int devfn_min; |
502a5395 | 42 | pci_set_irq_fn set_irq; |
d2b59317 | 43 | pci_map_irq_fn map_irq; |
ee995ffb | 44 | pci_hotplug_fn hotplug; |
87c30546 | 45 | DeviceState *hotplug_qdev; |
5d4e84c8 | 46 | void *irq_opaque; |
30468f78 | 47 | PCIDevice *devices[256]; |
80b3ada7 | 48 | PCIDevice *parent_dev; |
2e01c8cf | 49 | target_phys_addr_t mem_base; |
e822a52a IY |
50 | |
51 | QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ | |
52 | QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ | |
53 | ||
d2b59317 PB |
54 | /* The bus IRQ state is the logical OR of the connected devices. |
55 | Keep a count of the number of devices with raised IRQs. */ | |
52fc1d83 | 56 | int nirq; |
10c4c98a GH |
57 | int *irq_count; |
58 | }; | |
59 | ||
60 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); | |
61 | ||
62 | static struct BusInfo pci_bus_info = { | |
63 | .name = "PCI", | |
64 | .size = sizeof(PCIBus), | |
65 | .print_dev = pcibus_dev_print, | |
ee6847d1 | 66 | .props = (Property[]) { |
54586bd1 | 67 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
8c52c8f3 | 68 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), |
88169ddf | 69 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
54586bd1 | 70 | DEFINE_PROP_END_OF_LIST() |
ee6847d1 | 71 | } |
30468f78 | 72 | }; |
69b91039 | 73 | |
1941d19c | 74 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 75 | static void pci_set_irq(void *opaque, int irq_num, int level); |
8c52c8f3 | 76 | static int pci_add_option_rom(PCIDevice *pdev); |
1941d19c | 77 | |
d350d97d AL |
78 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
79 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
80 | |
81 | struct PCIHostBus { | |
82 | int domain; | |
83 | struct PCIBus *bus; | |
84 | QLIST_ENTRY(PCIHostBus) next; | |
85 | }; | |
86 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 87 | |
2d1e9f96 JQ |
88 | static const VMStateDescription vmstate_pcibus = { |
89 | .name = "PCIBUS", | |
90 | .version_id = 1, | |
91 | .minimum_version_id = 1, | |
92 | .minimum_version_id_old = 1, | |
93 | .fields = (VMStateField []) { | |
94 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 95 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 96 | VMSTATE_END_OF_LIST() |
52fc1d83 | 97 | } |
2d1e9f96 | 98 | }; |
52fc1d83 | 99 | |
b3b11697 | 100 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 101 | { |
b3b11697 IY |
102 | uint8_t type; |
103 | ||
104 | if (reg != PCI_ROM_SLOT) | |
105 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
106 | ||
107 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
108 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
109 | } |
110 | ||
d036bb21 MT |
111 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
112 | { | |
113 | return (d->irq_state >> irq_num) & 0x1; | |
114 | } | |
115 | ||
116 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
117 | { | |
118 | d->irq_state &= ~(0x1 << irq_num); | |
119 | d->irq_state |= level << irq_num; | |
120 | } | |
121 | ||
122 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
123 | { | |
124 | PCIBus *bus; | |
125 | for (;;) { | |
126 | bus = pci_dev->bus; | |
127 | irq_num = bus->map_irq(pci_dev, irq_num); | |
128 | if (bus->set_irq) | |
129 | break; | |
130 | pci_dev = bus->parent_dev; | |
131 | } | |
132 | bus->irq_count[irq_num] += change; | |
133 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
134 | } | |
135 | ||
f9bf77dd MT |
136 | /* Update interrupt status bit in config space on interrupt |
137 | * state change. */ | |
138 | static void pci_update_irq_status(PCIDevice *dev) | |
139 | { | |
140 | if (dev->irq_state) { | |
141 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
142 | } else { | |
143 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
144 | } | |
145 | } | |
146 | ||
5330de09 MT |
147 | static void pci_device_reset(PCIDevice *dev) |
148 | { | |
c0b1905b MT |
149 | int r; |
150 | ||
d036bb21 | 151 | dev->irq_state = 0; |
f9bf77dd | 152 | pci_update_irq_status(dev); |
c0b1905b MT |
153 | dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
154 | PCI_COMMAND_MASTER); | |
155 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; | |
156 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
157 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
158 | if (!dev->io_regions[r].size) { | |
159 | continue; | |
160 | } | |
b3b11697 | 161 | pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
c0b1905b MT |
162 | } |
163 | pci_update_mappings(dev); | |
5330de09 MT |
164 | } |
165 | ||
6eaa6847 GN |
166 | static void pci_bus_reset(void *opaque) |
167 | { | |
a60380a5 | 168 | PCIBus *bus = opaque; |
6eaa6847 GN |
169 | int i; |
170 | ||
171 | for (i = 0; i < bus->nirq; i++) { | |
172 | bus->irq_count[i] = 0; | |
173 | } | |
5330de09 MT |
174 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
175 | if (bus->devices[i]) { | |
176 | pci_device_reset(bus->devices[i]); | |
177 | } | |
6eaa6847 GN |
178 | } |
179 | } | |
180 | ||
e822a52a IY |
181 | static void pci_host_bus_register(int domain, PCIBus *bus) |
182 | { | |
183 | struct PCIHostBus *host; | |
184 | host = qemu_mallocz(sizeof(*host)); | |
185 | host->domain = domain; | |
186 | host->bus = bus; | |
187 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
188 | } | |
189 | ||
c469e1dd | 190 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
191 | { |
192 | struct PCIHostBus *host; | |
193 | ||
194 | QLIST_FOREACH(host, &host_buses, next) { | |
195 | if (host->domain == domain) { | |
196 | return host->bus; | |
197 | } | |
198 | } | |
199 | ||
200 | return NULL; | |
201 | } | |
202 | ||
21eea4b3 GH |
203 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
204 | const char *name, int devfn_min) | |
30468f78 | 205 | { |
21eea4b3 | 206 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
502a5395 | 207 | bus->devfn_min = devfn_min; |
e822a52a IY |
208 | |
209 | /* host bridge */ | |
210 | QLIST_INIT(&bus->child); | |
211 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
212 | ||
5084bca1 | 213 | vmstate_register(-1, &vmstate_pcibus, bus); |
a08d4367 | 214 | qemu_register_reset(pci_bus_reset, bus); |
21eea4b3 GH |
215 | } |
216 | ||
217 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) | |
218 | { | |
219 | PCIBus *bus; | |
220 | ||
221 | bus = qemu_mallocz(sizeof(*bus)); | |
222 | bus->qbus.qdev_allocated = 1; | |
223 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
224 | return bus; | |
225 | } | |
226 | ||
227 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
228 | void *irq_opaque, int nirq) | |
229 | { | |
230 | bus->set_irq = set_irq; | |
231 | bus->map_irq = map_irq; | |
232 | bus->irq_opaque = irq_opaque; | |
233 | bus->nirq = nirq; | |
234 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
235 | } | |
236 | ||
87c30546 | 237 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
238 | { |
239 | bus->qbus.allow_hotplug = 1; | |
240 | bus->hotplug = hotplug; | |
87c30546 | 241 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
242 | } |
243 | ||
2e01c8cf BS |
244 | void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base) |
245 | { | |
246 | bus->mem_base = base; | |
247 | } | |
248 | ||
21eea4b3 GH |
249 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
250 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
251 | void *irq_opaque, int devfn_min, int nirq) | |
252 | { | |
253 | PCIBus *bus; | |
254 | ||
255 | bus = pci_bus_new(parent, name, devfn_min); | |
256 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
257 | return bus; |
258 | } | |
69b91039 | 259 | |
e822a52a IY |
260 | static void pci_register_secondary_bus(PCIBus *parent, |
261 | PCIBus *bus, | |
03587182 GH |
262 | PCIDevice *dev, |
263 | pci_map_irq_fn map_irq, | |
264 | const char *name) | |
80b3ada7 | 265 | { |
03587182 | 266 | qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
80b3ada7 PB |
267 | bus->map_irq = map_irq; |
268 | bus->parent_dev = dev; | |
e822a52a IY |
269 | |
270 | QLIST_INIT(&bus->child); | |
271 | QLIST_INSERT_HEAD(&parent->child, bus, sibling); | |
272 | } | |
273 | ||
274 | static void pci_unregister_secondary_bus(PCIBus *bus) | |
275 | { | |
276 | assert(QLIST_EMPTY(&bus->child)); | |
277 | QLIST_REMOVE(bus, sibling); | |
80b3ada7 PB |
278 | } |
279 | ||
502a5395 PB |
280 | int pci_bus_num(PCIBus *s) |
281 | { | |
e94ff650 IY |
282 | if (!s->parent_dev) |
283 | return 0; /* pci host bridge */ | |
284 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
285 | } |
286 | ||
73534f2f | 287 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 288 | { |
73534f2f | 289 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 290 | uint8_t *config; |
52fc1d83 AZ |
291 | int i; |
292 | ||
a9f49946 IY |
293 | assert(size == pci_config_size(s)); |
294 | config = qemu_malloc(size); | |
295 | ||
296 | qemu_get_buffer(f, config, size); | |
297 | for (i = 0; i < size; ++i) { | |
298 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) { | |
299 | qemu_free(config); | |
bd4b65ee | 300 | return -EINVAL; |
a9f49946 IY |
301 | } |
302 | } | |
303 | memcpy(s->config, config, size); | |
bd4b65ee | 304 | |
1941d19c | 305 | pci_update_mappings(s); |
52fc1d83 | 306 | |
a9f49946 | 307 | qemu_free(config); |
30ca2aab FB |
308 | return 0; |
309 | } | |
310 | ||
73534f2f | 311 | /* just put buffer */ |
84e2e3eb | 312 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 313 | { |
dbe73d7f | 314 | const uint8_t **v = pv; |
a9f49946 | 315 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 316 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
317 | } |
318 | ||
319 | static VMStateInfo vmstate_info_pci_config = { | |
320 | .name = "pci config", | |
321 | .get = get_pci_config_device, | |
322 | .put = put_pci_config_device, | |
323 | }; | |
324 | ||
d036bb21 MT |
325 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
326 | { | |
c3f8f611 | 327 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
328 | uint32_t irq_state[PCI_NUM_PINS]; |
329 | int i; | |
330 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
331 | irq_state[i] = qemu_get_be32(f); | |
332 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
333 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
334 | irq_state[i]); | |
335 | return -EINVAL; | |
336 | } | |
337 | } | |
338 | ||
339 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
340 | pci_set_irq_state(s, i, irq_state[i]); | |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
347 | { | |
348 | int i; | |
c3f8f611 | 349 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
350 | |
351 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
352 | qemu_put_be32(f, pci_irq_state(s, i)); | |
353 | } | |
354 | } | |
355 | ||
356 | static VMStateInfo vmstate_info_pci_irq_state = { | |
357 | .name = "pci irq state", | |
358 | .get = get_pci_irq_state, | |
359 | .put = put_pci_irq_state, | |
360 | }; | |
361 | ||
73534f2f JQ |
362 | const VMStateDescription vmstate_pci_device = { |
363 | .name = "PCIDevice", | |
364 | .version_id = 2, | |
365 | .minimum_version_id = 1, | |
366 | .minimum_version_id_old = 1, | |
367 | .fields = (VMStateField []) { | |
368 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
369 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
370 | vmstate_info_pci_config, | |
371 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
372 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
373 | vmstate_info_pci_irq_state, | |
374 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
375 | VMSTATE_END_OF_LIST() |
376 | } | |
377 | }; | |
378 | ||
379 | const VMStateDescription vmstate_pcie_device = { | |
380 | .name = "PCIDevice", | |
381 | .version_id = 2, | |
382 | .minimum_version_id = 1, | |
383 | .minimum_version_id_old = 1, | |
384 | .fields = (VMStateField []) { | |
385 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
386 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
387 | vmstate_info_pci_config, | |
388 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
389 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
390 | vmstate_info_pci_irq_state, | |
391 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
392 | VMSTATE_END_OF_LIST() |
393 | } | |
394 | }; | |
395 | ||
a9f49946 IY |
396 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
397 | { | |
398 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
399 | } | |
400 | ||
73534f2f JQ |
401 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
402 | { | |
f9bf77dd MT |
403 | /* Clear interrupt status bit: it is implicit |
404 | * in irq_state which we are saving. | |
405 | * This makes us compatible with old devices | |
406 | * which never set or clear this bit. */ | |
407 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 408 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
409 | /* Restore the interrupt status bit. */ |
410 | pci_update_irq_status(s); | |
73534f2f JQ |
411 | } |
412 | ||
413 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
414 | { | |
f9bf77dd MT |
415 | int ret; |
416 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
417 | /* Restore the interrupt status bit. */ | |
418 | pci_update_irq_status(s); | |
419 | return ret; | |
73534f2f JQ |
420 | } |
421 | ||
5e434f4e | 422 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 423 | { |
5e434f4e IY |
424 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
425 | pci_default_sub_vendor_id); | |
426 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
427 | pci_default_sub_device_id); | |
d350d97d AL |
428 | } |
429 | ||
880345c4 AL |
430 | /* |
431 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error | |
432 | */ | |
433 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) | |
434 | { | |
435 | const char *p; | |
436 | char *e; | |
437 | unsigned long val; | |
438 | unsigned long dom = 0, bus = 0; | |
439 | unsigned slot = 0; | |
440 | ||
441 | p = addr; | |
442 | val = strtoul(p, &e, 16); | |
443 | if (e == p) | |
444 | return -1; | |
445 | if (*e == ':') { | |
446 | bus = val; | |
447 | p = e + 1; | |
448 | val = strtoul(p, &e, 16); | |
449 | if (e == p) | |
450 | return -1; | |
451 | if (*e == ':') { | |
452 | dom = bus; | |
453 | bus = val; | |
454 | p = e + 1; | |
455 | val = strtoul(p, &e, 16); | |
456 | if (e == p) | |
457 | return -1; | |
458 | } | |
459 | } | |
460 | ||
461 | if (dom > 0xffff || bus > 0xff || val > 0x1f) | |
462 | return -1; | |
463 | ||
464 | slot = val; | |
465 | ||
466 | if (*e) | |
467 | return -1; | |
468 | ||
469 | /* Note: QEMU doesn't implement domains other than 0 */ | |
c469e1dd | 470 | if (!pci_find_bus(pci_find_root_bus(dom), bus)) |
880345c4 AL |
471 | return -1; |
472 | ||
473 | *domp = dom; | |
474 | *busp = bus; | |
475 | *slotp = slot; | |
476 | return 0; | |
477 | } | |
478 | ||
e9283f8b JK |
479 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
480 | unsigned *slotp) | |
880345c4 | 481 | { |
e9283f8b JK |
482 | /* strip legacy tag */ |
483 | if (!strncmp(addr, "pci_addr=", 9)) { | |
484 | addr += 9; | |
485 | } | |
486 | if (pci_parse_devaddr(addr, domp, busp, slotp)) { | |
487 | monitor_printf(mon, "Invalid pci address\n"); | |
880345c4 | 488 | return -1; |
e9283f8b JK |
489 | } |
490 | return 0; | |
880345c4 AL |
491 | } |
492 | ||
49bd1458 | 493 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
494 | { |
495 | int dom, bus; | |
496 | unsigned slot; | |
497 | ||
498 | if (!devaddr) { | |
499 | *devfnp = -1; | |
c469e1dd | 500 | return pci_find_bus(pci_find_root_bus(0), 0); |
5607c388 MA |
501 | } |
502 | ||
503 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { | |
504 | return NULL; | |
505 | } | |
506 | ||
507 | *devfnp = slot << 3; | |
c469e1dd | 508 | return pci_find_bus(pci_find_root_bus(0), bus); |
5607c388 MA |
509 | } |
510 | ||
bd4b65ee MT |
511 | static void pci_init_cmask(PCIDevice *dev) |
512 | { | |
513 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
514 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
515 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
516 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
517 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
518 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
519 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
520 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
521 | } | |
522 | ||
b7ee1603 MT |
523 | static void pci_init_wmask(PCIDevice *dev) |
524 | { | |
a9f49946 IY |
525 | int config_size = pci_config_size(dev); |
526 | ||
b7ee1603 MT |
527 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
528 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 529 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
530 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
531 | PCI_COMMAND_INTX_DISABLE); | |
3e21ffc9 IY |
532 | |
533 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
534 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
535 | } |
536 | ||
fb231628 IY |
537 | static void pci_init_wmask_bridge(PCIDevice *d) |
538 | { | |
539 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
540 | PCI_SEC_LETENCY_TIMER */ | |
541 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
542 | ||
543 | /* base and limit */ | |
544 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
545 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
546 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
547 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
548 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
549 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
550 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
551 | PCI_PREF_RANGE_MASK & 0xffff); | |
552 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
553 | PCI_PREF_RANGE_MASK & 0xffff); | |
554 | ||
555 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
556 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
557 | ||
558 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); | |
559 | } | |
560 | ||
a9f49946 IY |
561 | static void pci_config_alloc(PCIDevice *pci_dev) |
562 | { | |
563 | int config_size = pci_config_size(pci_dev); | |
564 | ||
565 | pci_dev->config = qemu_mallocz(config_size); | |
566 | pci_dev->cmask = qemu_mallocz(config_size); | |
567 | pci_dev->wmask = qemu_mallocz(config_size); | |
568 | pci_dev->used = qemu_mallocz(config_size); | |
569 | } | |
570 | ||
571 | static void pci_config_free(PCIDevice *pci_dev) | |
572 | { | |
573 | qemu_free(pci_dev->config); | |
574 | qemu_free(pci_dev->cmask); | |
575 | qemu_free(pci_dev->wmask); | |
576 | qemu_free(pci_dev->used); | |
577 | } | |
578 | ||
69b91039 | 579 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
580 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
581 | const char *name, int devfn, | |
582 | PCIConfigReadFunc *config_read, | |
fb231628 IY |
583 | PCIConfigWriteFunc *config_write, |
584 | uint8_t header_type) | |
69b91039 | 585 | { |
69b91039 | 586 | if (devfn < 0) { |
b47b0706 IY |
587 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
588 | devfn += 8) { | |
30468f78 | 589 | if (!bus->devices[devfn]) |
69b91039 FB |
590 | goto found; |
591 | } | |
1ecda02b | 592 | error_report("PCI: no devfn available for %s, all in use", name); |
09e3acc6 | 593 | return NULL; |
69b91039 | 594 | found: ; |
07b7d053 | 595 | } else if (bus->devices[devfn]) { |
1ecda02b MA |
596 | error_report("PCI: devfn %d not available for %s, in use by %s", |
597 | devfn, name, bus->devices[devfn]->name); | |
09e3acc6 | 598 | return NULL; |
69b91039 | 599 | } |
30468f78 | 600 | pci_dev->bus = bus; |
69b91039 FB |
601 | pci_dev->devfn = devfn; |
602 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 603 | pci_dev->irq_state = 0; |
a9f49946 | 604 | pci_config_alloc(pci_dev); |
fb231628 IY |
605 | |
606 | header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
607 | if (header_type == PCI_HEADER_TYPE_NORMAL) { | |
608 | pci_set_default_subsystem_id(pci_dev); | |
609 | } | |
bd4b65ee | 610 | pci_init_cmask(pci_dev); |
b7ee1603 | 611 | pci_init_wmask(pci_dev); |
fb231628 IY |
612 | if (header_type == PCI_HEADER_TYPE_BRIDGE) { |
613 | pci_init_wmask_bridge(pci_dev); | |
614 | } | |
0ac32c83 FB |
615 | |
616 | if (!config_read) | |
617 | config_read = pci_default_read_config; | |
618 | if (!config_write) | |
619 | config_write = pci_default_write_config; | |
69b91039 FB |
620 | pci_dev->config_read = config_read; |
621 | pci_dev->config_write = config_write; | |
30468f78 | 622 | bus->devices[devfn] = pci_dev; |
e369cad7 | 623 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 624 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
625 | return pci_dev; |
626 | } | |
627 | ||
925fe64a AW |
628 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
629 | { | |
630 | qemu_free_irqs(pci_dev->irq); | |
631 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
632 | pci_config_free(pci_dev); | |
633 | } | |
634 | ||
6b1b92d3 PB |
635 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
636 | int instance_size, int devfn, | |
637 | PCIConfigReadFunc *config_read, | |
638 | PCIConfigWriteFunc *config_write) | |
639 | { | |
640 | PCIDevice *pci_dev; | |
641 | ||
642 | pci_dev = qemu_mallocz(instance_size); | |
643 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
fb231628 IY |
644 | config_read, config_write, |
645 | PCI_HEADER_TYPE_NORMAL); | |
09e3acc6 GH |
646 | if (pci_dev == NULL) { |
647 | hw_error("PCI: can't register device\n"); | |
648 | } | |
6b1b92d3 PB |
649 | return pci_dev; |
650 | } | |
2e01c8cf BS |
651 | |
652 | static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus, | |
653 | target_phys_addr_t addr) | |
5851e08c | 654 | { |
2e01c8cf | 655 | return addr + bus->mem_base; |
5851e08c AL |
656 | } |
657 | ||
658 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
659 | { | |
660 | PCIIORegion *r; | |
661 | int i; | |
662 | ||
663 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
664 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 665 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 666 | continue; |
0392a017 | 667 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
a0c7a97e | 668 | isa_unassign_ioport(r->addr, r->filtered_size); |
5851e08c | 669 | } else { |
2e01c8cf BS |
670 | cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, |
671 | r->addr), | |
672 | r->filtered_size, | |
673 | IO_MEM_UNASSIGNED); | |
5851e08c AL |
674 | } |
675 | } | |
676 | } | |
677 | ||
a36a344d | 678 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 679 | { |
a36a344d | 680 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 681 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
682 | int ret = 0; |
683 | ||
e3936fa5 GH |
684 | if (info->exit) |
685 | ret = info->exit(pci_dev); | |
5851e08c AL |
686 | if (ret) |
687 | return ret; | |
688 | ||
689 | pci_unregister_io_regions(pci_dev); | |
925fe64a | 690 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
691 | return 0; |
692 | } | |
693 | ||
28c2c264 | 694 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
6e355d90 | 695 | pcibus_t size, int type, |
69b91039 FB |
696 | PCIMapIORegionFunc *map_func) |
697 | { | |
698 | PCIIORegion *r; | |
d7ce493a | 699 | uint32_t addr; |
6e355d90 | 700 | pcibus_t wmask; |
69b91039 | 701 | |
8a8696a3 | 702 | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
69b91039 | 703 | return; |
a4c20c6a AL |
704 | |
705 | if (size & (size-1)) { | |
706 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 707 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
708 | exit(1); |
709 | } | |
710 | ||
69b91039 | 711 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 712 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 | 713 | r->size = size; |
a0c7a97e | 714 | r->filtered_size = size; |
69b91039 FB |
715 | r->type = type; |
716 | r->map_func = map_func; | |
b7ee1603 MT |
717 | |
718 | wmask = ~(size - 1); | |
b3b11697 | 719 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 720 | if (region_num == PCI_ROM_SLOT) { |
b7ee1603 | 721 | /* ROM enable bit is writeable */ |
5330de09 | 722 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 723 | } |
b0ff8eb2 | 724 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
725 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
726 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
727 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
728 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
729 | } else { | |
730 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
731 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
732 | } | |
69b91039 FB |
733 | } |
734 | ||
a0c7a97e IY |
735 | static uint32_t pci_config_get_io_base(PCIDevice *d, |
736 | uint32_t base, uint32_t base_upper16) | |
737 | { | |
738 | uint32_t val; | |
739 | ||
740 | val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; | |
741 | if (d->config[base] & PCI_IO_RANGE_TYPE_32) { | |
10c9c329 | 742 | val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; |
a0c7a97e IY |
743 | } |
744 | return val; | |
745 | } | |
746 | ||
d46636b8 | 747 | static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base) |
a0c7a97e | 748 | { |
d46636b8 | 749 | return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) |
a0c7a97e IY |
750 | << 16; |
751 | } | |
752 | ||
d46636b8 | 753 | static pcibus_t pci_config_get_pref_base(PCIDevice *d, |
a0c7a97e IY |
754 | uint32_t base, uint32_t upper) |
755 | { | |
d46636b8 IY |
756 | pcibus_t tmp; |
757 | pcibus_t val; | |
758 | ||
759 | tmp = (pcibus_t)pci_get_word(d->config + base); | |
760 | val = (tmp & PCI_PREF_RANGE_MASK) << 16; | |
761 | if (tmp & PCI_PREF_RANGE_TYPE_64) { | |
762 | val |= (pcibus_t)pci_get_long(d->config + upper) << 32; | |
763 | } | |
a0c7a97e IY |
764 | return val; |
765 | } | |
766 | ||
767 | static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type) | |
768 | { | |
769 | pcibus_t base; | |
770 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
771 | base = pci_config_get_io_base(bridge, | |
772 | PCI_IO_BASE, PCI_IO_BASE_UPPER16); | |
773 | } else { | |
774 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
775 | base = pci_config_get_pref_base( | |
776 | bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); | |
777 | } else { | |
778 | base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); | |
779 | } | |
780 | } | |
781 | ||
782 | return base; | |
783 | } | |
784 | ||
785 | static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type) | |
786 | { | |
787 | pcibus_t limit; | |
788 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
789 | limit = pci_config_get_io_base(bridge, | |
790 | PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); | |
791 | limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ | |
792 | } else { | |
793 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { | |
794 | limit = pci_config_get_pref_base( | |
795 | bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); | |
796 | } else { | |
797 | limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); | |
798 | } | |
799 | limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ | |
800 | } | |
801 | return limit; | |
802 | } | |
803 | ||
804 | static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, | |
805 | uint8_t type) | |
806 | { | |
807 | pcibus_t base = *addr; | |
808 | pcibus_t limit = *addr + *size - 1; | |
809 | PCIDevice *br; | |
810 | ||
811 | for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { | |
812 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
813 | ||
814 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
815 | if (!(cmd & PCI_COMMAND_IO)) { | |
816 | goto no_map; | |
817 | } | |
818 | } else { | |
819 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
820 | goto no_map; | |
821 | } | |
822 | } | |
823 | ||
824 | base = MAX(base, pci_bridge_get_base(br, type)); | |
825 | limit = MIN(limit, pci_bridge_get_limit(br, type)); | |
826 | } | |
827 | ||
828 | if (base > limit) { | |
88a95564 | 829 | goto no_map; |
a0c7a97e | 830 | } |
88a95564 MT |
831 | *addr = base; |
832 | *size = limit - base + 1; | |
833 | return; | |
834 | no_map: | |
835 | *addr = PCI_BAR_UNMAPPED; | |
836 | *size = 0; | |
a0c7a97e IY |
837 | } |
838 | ||
876a350d MT |
839 | static pcibus_t pci_bar_address(PCIDevice *d, |
840 | int reg, uint8_t type, pcibus_t size) | |
841 | { | |
842 | pcibus_t new_addr, last_addr; | |
843 | int bar = pci_bar(d, reg); | |
844 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
845 | ||
846 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
847 | if (!(cmd & PCI_COMMAND_IO)) { | |
848 | return PCI_BAR_UNMAPPED; | |
849 | } | |
850 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
851 | last_addr = new_addr + size - 1; | |
852 | /* NOTE: we have only 64K ioports on PC */ | |
853 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
854 | return PCI_BAR_UNMAPPED; | |
855 | } | |
856 | return new_addr; | |
857 | } | |
858 | ||
859 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
860 | return PCI_BAR_UNMAPPED; | |
861 | } | |
862 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
863 | new_addr = pci_get_quad(d->config + bar); | |
864 | } else { | |
865 | new_addr = pci_get_long(d->config + bar); | |
866 | } | |
867 | /* the ROM slot has a specific enable bit */ | |
868 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
869 | return PCI_BAR_UNMAPPED; | |
870 | } | |
871 | new_addr &= ~(size - 1); | |
872 | last_addr = new_addr + size - 1; | |
873 | /* NOTE: we do not support wrapping */ | |
874 | /* XXX: as we cannot support really dynamic | |
875 | mappings, we handle specific values as invalid | |
876 | mappings. */ | |
877 | if (last_addr <= new_addr || new_addr == 0 || | |
878 | last_addr == PCI_BAR_UNMAPPED) { | |
879 | return PCI_BAR_UNMAPPED; | |
880 | } | |
881 | ||
882 | /* Now pcibus_t is 64bit. | |
883 | * Check if 32 bit BAR wraps around explicitly. | |
884 | * Without this, PC ide doesn't work well. | |
885 | * TODO: remove this work around. | |
886 | */ | |
887 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
888 | return PCI_BAR_UNMAPPED; | |
889 | } | |
890 | ||
891 | /* | |
892 | * OS is allowed to set BAR beyond its addressable | |
893 | * bits. For example, 32 bit OS can set 64bit bar | |
894 | * to >4G. Check it. TODO: we might need to support | |
895 | * it in the future for e.g. PAE. | |
896 | */ | |
897 | if (last_addr >= TARGET_PHYS_ADDR_MAX) { | |
898 | return PCI_BAR_UNMAPPED; | |
899 | } | |
900 | ||
901 | return new_addr; | |
902 | } | |
903 | ||
0ac32c83 FB |
904 | static void pci_update_mappings(PCIDevice *d) |
905 | { | |
906 | PCIIORegion *r; | |
876a350d | 907 | int i; |
c71b5b4a | 908 | pcibus_t new_addr, filtered_size; |
3b46e624 | 909 | |
8a8696a3 | 910 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 911 | r = &d->io_regions[i]; |
a9688570 IY |
912 | |
913 | /* this region isn't registered */ | |
ec503442 | 914 | if (!r->size) |
a9688570 IY |
915 | continue; |
916 | ||
876a350d | 917 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 | 918 | |
a0c7a97e IY |
919 | /* bridge filtering */ |
920 | filtered_size = r->size; | |
921 | if (new_addr != PCI_BAR_UNMAPPED) { | |
922 | pci_bridge_filter(d, &new_addr, &filtered_size, r->type); | |
923 | } | |
924 | ||
a9688570 | 925 | /* This bar isn't changed */ |
a0c7a97e | 926 | if (new_addr == r->addr && filtered_size == r->filtered_size) |
a9688570 IY |
927 | continue; |
928 | ||
929 | /* now do the real mapping */ | |
930 | if (r->addr != PCI_BAR_UNMAPPED) { | |
931 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
932 | int class; | |
933 | /* NOTE: specific hack for IDE in PC case: | |
934 | only one byte must be mapped. */ | |
935 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
936 | if (class == 0x0101 && r->size == 4) { | |
937 | isa_unassign_ioport(r->addr + 2, 1); | |
938 | } else { | |
a0c7a97e | 939 | isa_unassign_ioport(r->addr, r->filtered_size); |
0ac32c83 | 940 | } |
a9688570 | 941 | } else { |
c71b5b4a | 942 | cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), |
a0c7a97e | 943 | r->filtered_size, |
a9688570 | 944 | IO_MEM_UNASSIGNED); |
a0c7a97e | 945 | qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
0ac32c83 FB |
946 | } |
947 | } | |
a9688570 | 948 | r->addr = new_addr; |
a0c7a97e | 949 | r->filtered_size = filtered_size; |
a9688570 | 950 | if (r->addr != PCI_BAR_UNMAPPED) { |
a0c7a97e IY |
951 | /* |
952 | * TODO: currently almost all the map funcions assumes | |
953 | * filtered_size == size and addr & ~(size - 1) == addr. | |
954 | * However with bridge filtering, they aren't always true. | |
955 | * Teach them such cases, such that filtered_size < size and | |
956 | * addr & (size - 1) != 0. | |
957 | */ | |
cf616802 BS |
958 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
959 | r->map_func(d, i, r->addr, r->filtered_size, r->type); | |
960 | } else { | |
961 | r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr), | |
962 | r->filtered_size, r->type); | |
963 | } | |
a9688570 | 964 | } |
0ac32c83 FB |
965 | } |
966 | } | |
967 | ||
a7b15a5c MT |
968 | static inline int pci_irq_disabled(PCIDevice *d) |
969 | { | |
970 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
971 | } | |
972 | ||
973 | /* Called after interrupt disabled field update in config space, | |
974 | * assert/deassert interrupts if necessary. | |
975 | * Gets original interrupt disable bit value (before update). */ | |
976 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
977 | { | |
978 | int i, disabled = pci_irq_disabled(d); | |
979 | if (disabled == was_irq_disabled) | |
980 | return; | |
981 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
982 | int state = pci_irq_state(d, i); | |
983 | pci_change_irq_level(d, i, disabled ? -state : state); | |
984 | } | |
985 | } | |
986 | ||
5fafdf24 | 987 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 988 | uint32_t address, int len) |
69b91039 | 989 | { |
5029fe12 IY |
990 | uint32_t val = 0; |
991 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 992 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
993 | memcpy(&val, d->config + address, len); |
994 | return le32_to_cpu(val); | |
0ac32c83 FB |
995 | } |
996 | ||
b7ee1603 | 997 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 998 | { |
a7b15a5c | 999 | int i, was_irq_disabled = pci_irq_disabled(d); |
a9f49946 | 1000 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 1001 | |
91011d4f SW |
1002 | for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
1003 | uint8_t wmask = d->wmask[addr + i]; | |
1004 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); | |
0ac32c83 | 1005 | } |
260c0cd3 | 1006 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1007 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1008 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1009 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1010 | pci_update_mappings(d); |
a7b15a5c MT |
1011 | |
1012 | if (range_covers_byte(addr, l, PCI_COMMAND)) | |
1013 | pci_update_irq_disabled(d, was_irq_disabled); | |
69b91039 FB |
1014 | } |
1015 | ||
502a5395 PB |
1016 | /***********************************************************/ |
1017 | /* generic PCI irq support */ | |
30468f78 | 1018 | |
502a5395 | 1019 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1020 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1021 | { |
a60380a5 | 1022 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1023 | int change; |
3b46e624 | 1024 | |
d036bb21 | 1025 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1026 | if (!change) |
1027 | return; | |
d2b59317 | 1028 | |
d036bb21 | 1029 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1030 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1031 | if (pci_irq_disabled(pci_dev)) |
1032 | return; | |
d036bb21 | 1033 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1034 | } |
1035 | ||
502a5395 PB |
1036 | /***********************************************************/ |
1037 | /* monitor info on PCI */ | |
0ac32c83 | 1038 | |
6650ee6d PB |
1039 | typedef struct { |
1040 | uint16_t class; | |
1041 | const char *desc; | |
1042 | } pci_class_desc; | |
1043 | ||
09bc878a | 1044 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1045 | { |
4ca9c76f | 1046 | { 0x0100, "SCSI controller"}, |
6650ee6d | 1047 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
1048 | { 0x0102, "Floppy controller"}, |
1049 | { 0x0103, "IPI controller"}, | |
1050 | { 0x0104, "RAID controller"}, | |
1051 | { 0x0106, "SATA controller"}, | |
1052 | { 0x0107, "SAS controller"}, | |
1053 | { 0x0180, "Storage controller"}, | |
6650ee6d | 1054 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
1055 | { 0x0201, "Token Ring controller"}, |
1056 | { 0x0202, "FDDI controller"}, | |
1057 | { 0x0203, "ATM controller"}, | |
1058 | { 0x0280, "Network controller"}, | |
6650ee6d | 1059 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
1060 | { 0x0301, "XGA controller"}, |
1061 | { 0x0302, "3D controller"}, | |
1062 | { 0x0380, "Display controller"}, | |
1063 | { 0x0400, "Video controller"}, | |
1064 | { 0x0401, "Audio controller"}, | |
1065 | { 0x0402, "Phone"}, | |
1066 | { 0x0480, "Multimedia controller"}, | |
1067 | { 0x0500, "RAM controller"}, | |
1068 | { 0x0501, "Flash controller"}, | |
1069 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
1070 | { 0x0600, "Host bridge"}, |
1071 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
1072 | { 0x0602, "EISA bridge"}, |
1073 | { 0x0603, "MC bridge"}, | |
6650ee6d | 1074 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
1075 | { 0x0605, "PCMCIA bridge"}, |
1076 | { 0x0606, "NUBUS bridge"}, | |
1077 | { 0x0607, "CARDBUS bridge"}, | |
1078 | { 0x0608, "RACEWAY bridge"}, | |
1079 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
1080 | { 0x0c03, "USB controller"}, |
1081 | { 0, NULL} | |
1082 | }; | |
1083 | ||
163c8a59 LC |
1084 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1085 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
30468f78 | 1086 | { |
163c8a59 LC |
1087 | PCIDevice *d; |
1088 | int devfn; | |
30468f78 | 1089 | |
163c8a59 LC |
1090 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1091 | d = bus->devices[devfn]; | |
1092 | if (d) { | |
1093 | fn(bus, d); | |
1094 | } | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
1099 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
1100 | { | |
1101 | bus = pci_find_bus(bus, bus_num); | |
1102 | ||
1103 | if (bus) { | |
1104 | pci_for_each_device_under_bus(bus, fn); | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | static void pci_device_print(Monitor *mon, QDict *device) | |
1109 | { | |
1110 | QDict *qdict; | |
1111 | QListEntry *entry; | |
1112 | uint64_t addr, size; | |
1113 | ||
1114 | monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus")); | |
1115 | monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n", | |
1116 | qdict_get_int(device, "slot"), | |
1117 | qdict_get_int(device, "function")); | |
376253ec | 1118 | monitor_printf(mon, " "); |
163c8a59 LC |
1119 | |
1120 | qdict = qdict_get_qdict(device, "class_info"); | |
1121 | if (qdict_haskey(qdict, "desc")) { | |
1122 | monitor_printf(mon, "%s", qdict_get_str(qdict, "desc")); | |
6650ee6d | 1123 | } else { |
163c8a59 | 1124 | monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class")); |
72cc6cfe | 1125 | } |
30468f78 | 1126 | |
163c8a59 LC |
1127 | qdict = qdict_get_qdict(device, "id"); |
1128 | monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", | |
1129 | qdict_get_int(qdict, "device"), | |
1130 | qdict_get_int(qdict, "vendor")); | |
1131 | ||
1132 | if (qdict_haskey(device, "irq")) { | |
1133 | monitor_printf(mon, " IRQ %" PRId64 ".\n", | |
1134 | qdict_get_int(device, "irq")); | |
30468f78 | 1135 | } |
b4dccd8d | 1136 | |
163c8a59 LC |
1137 | if (qdict_haskey(device, "pci_bridge")) { |
1138 | QDict *info; | |
1139 | ||
1140 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1141 | ||
1142 | info = qdict_get_qdict(qdict, "bus"); | |
1143 | monitor_printf(mon, " BUS %" PRId64 ".\n", | |
1144 | qdict_get_int(info, "number")); | |
1145 | monitor_printf(mon, " secondary bus %" PRId64 ".\n", | |
1146 | qdict_get_int(info, "secondary")); | |
1147 | monitor_printf(mon, " subordinate bus %" PRId64 ".\n", | |
1148 | qdict_get_int(info, "subordinate")); | |
b4dccd8d | 1149 | |
163c8a59 | 1150 | info = qdict_get_qdict(qdict, "io_range"); |
b4dccd8d | 1151 | monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
163c8a59 LC |
1152 | qdict_get_int(info, "base"), |
1153 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1154 | |
163c8a59 | 1155 | info = qdict_get_qdict(qdict, "memory_range"); |
b4dccd8d IY |
1156 | monitor_printf(mon, |
1157 | " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", | |
163c8a59 LC |
1158 | qdict_get_int(info, "base"), |
1159 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1160 | |
163c8a59 | 1161 | info = qdict_get_qdict(qdict, "prefetchable_range"); |
b4dccd8d | 1162 | monitor_printf(mon, " prefetchable memory range " |
163c8a59 LC |
1163 | "[0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1164 | qdict_get_int(info, "base"), | |
1165 | qdict_get_int(info, "limit")); | |
80b3ada7 | 1166 | } |
14421258 | 1167 | |
163c8a59 LC |
1168 | QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) { |
1169 | qdict = qobject_to_qdict(qlist_entry_obj(entry)); | |
1170 | monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar")); | |
1171 | ||
1172 | addr = qdict_get_int(qdict, "address"); | |
1173 | size = qdict_get_int(qdict, "size"); | |
1174 | ||
1175 | if (!strcmp(qdict_get_str(qdict, "type"), "io")) { | |
1176 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS | |
1177 | " [0x%04"FMT_PCIBUS"].\n", | |
1178 | addr, addr + size - 1); | |
1179 | } else { | |
1180 | monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 1181 | " [0x%08"FMT_PCIBUS"].\n", |
163c8a59 LC |
1182 | qdict_get_bool(qdict, "mem_type_64") ? 64 : 32, |
1183 | qdict_get_bool(qdict, "prefetch") ? | |
1184 | " prefetchable" : "", addr, addr + size - 1); | |
502a5395 | 1185 | } |
77d4bc34 | 1186 | } |
163c8a59 LC |
1187 | |
1188 | monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id")); | |
1189 | ||
d5e4acf7 LC |
1190 | if (qdict_haskey(device, "pci_bridge")) { |
1191 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1192 | if (qdict_haskey(qdict, "devices")) { | |
1193 | QListEntry *dev; | |
1194 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1195 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1196 | } | |
1197 | } | |
1198 | } | |
163c8a59 LC |
1199 | } |
1200 | ||
1201 | void do_pci_info_print(Monitor *mon, const QObject *data) | |
1202 | { | |
1203 | QListEntry *bus, *dev; | |
1204 | ||
1205 | QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) { | |
1206 | QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus)); | |
1207 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1208 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1209 | } | |
80b3ada7 | 1210 | } |
384d8876 FB |
1211 | } |
1212 | ||
163c8a59 LC |
1213 | static QObject *pci_get_dev_class(const PCIDevice *dev) |
1214 | { | |
1215 | int class; | |
1216 | const pci_class_desc *desc; | |
1217 | ||
1218 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1219 | desc = pci_class_descriptions; | |
1220 | while (desc->desc && class != desc->class) | |
1221 | desc++; | |
1222 | ||
1223 | if (desc->desc) { | |
1224 | return qobject_from_jsonf("{ 'desc': %s, 'class': %d }", | |
1225 | desc->desc, class); | |
1226 | } else { | |
1227 | return qobject_from_jsonf("{ 'class': %d }", class); | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | static QObject *pci_get_dev_id(const PCIDevice *dev) | |
1232 | { | |
1233 | return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }", | |
1234 | pci_get_word(dev->config + PCI_VENDOR_ID), | |
1235 | pci_get_word(dev->config + PCI_DEVICE_ID)); | |
1236 | } | |
1237 | ||
1238 | static QObject *pci_get_regions_list(const PCIDevice *dev) | |
1239 | { | |
1240 | int i; | |
1241 | QList *regions_list; | |
1242 | ||
1243 | regions_list = qlist_new(); | |
1244 | ||
1245 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1246 | QObject *obj; | |
1247 | const PCIIORegion *r = &dev->io_regions[i]; | |
1248 | ||
1249 | if (!r->size) { | |
1250 | continue; | |
1251 | } | |
1252 | ||
1253 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1254 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', " | |
1255 | "'address': %" PRId64 ", " | |
1256 | "'size': %" PRId64 " }", | |
1257 | i, r->addr, r->size); | |
1258 | } else { | |
1259 | int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
1260 | ||
1261 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', " | |
1262 | "'mem_type_64': %i, 'prefetch': %i, " | |
1263 | "'address': %" PRId64 ", " | |
1264 | "'size': %" PRId64 " }", | |
1265 | i, mem_type_64, | |
1266 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH, | |
1267 | r->addr, r->size); | |
1268 | } | |
1269 | ||
1270 | qlist_append_obj(regions_list, obj); | |
1271 | } | |
1272 | ||
1273 | return QOBJECT(regions_list); | |
1274 | } | |
1275 | ||
d5e4acf7 LC |
1276 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num); |
1277 | ||
1278 | static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num) | |
163c8a59 | 1279 | { |
b5937f29 | 1280 | uint8_t type; |
163c8a59 LC |
1281 | QObject *obj; |
1282 | ||
1283 | obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p," | |
1284 | " 'qdev_id': %s }", | |
1285 | bus_num, | |
1286 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
1287 | pci_get_dev_class(dev), pci_get_dev_id(dev), | |
1288 | pci_get_regions_list(dev), | |
1289 | dev->qdev.id ? dev->qdev.id : ""); | |
1290 | ||
1291 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
1292 | QDict *qdict = qobject_to_qdict(obj); | |
1293 | qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE])); | |
1294 | } | |
1295 | ||
b5937f29 IY |
1296 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1297 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
163c8a59 LC |
1298 | QDict *qdict; |
1299 | QObject *pci_bridge; | |
1300 | ||
1301 | pci_bridge = qobject_from_jsonf("{ 'bus': " | |
1302 | "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, " | |
1303 | "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1304 | "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1305 | "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }", | |
c021f8e6 | 1306 | dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS], |
163c8a59 LC |
1307 | dev->config[PCI_SUBORDINATE_BUS], |
1308 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1309 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1310 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1311 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1312 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1313 | PCI_BASE_ADDRESS_MEM_PREFETCH), | |
1314 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1315 | PCI_BASE_ADDRESS_MEM_PREFETCH)); | |
1316 | ||
c021f8e6 BS |
1317 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1318 | PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); | |
d5e4acf7 | 1319 | |
c021f8e6 BS |
1320 | if (child_bus) { |
1321 | qdict = qobject_to_qdict(pci_bridge); | |
1322 | qdict_put_obj(qdict, "devices", | |
1323 | pci_get_devices_list(child_bus, | |
1324 | dev->config[PCI_SECONDARY_BUS])); | |
1325 | } | |
1326 | } | |
163c8a59 LC |
1327 | qdict = qobject_to_qdict(obj); |
1328 | qdict_put_obj(qdict, "pci_bridge", pci_bridge); | |
1329 | } | |
1330 | ||
1331 | return obj; | |
1332 | } | |
1333 | ||
1334 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num) | |
384d8876 | 1335 | { |
502a5395 | 1336 | int devfn; |
163c8a59 LC |
1337 | PCIDevice *dev; |
1338 | QList *dev_list; | |
3b46e624 | 1339 | |
163c8a59 LC |
1340 | dev_list = qlist_new(); |
1341 | ||
1342 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1343 | dev = bus->devices[devfn]; | |
1344 | if (dev) { | |
d5e4acf7 | 1345 | qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num)); |
163c8a59 | 1346 | } |
1074df4f | 1347 | } |
163c8a59 LC |
1348 | |
1349 | return QOBJECT(dev_list); | |
1074df4f IY |
1350 | } |
1351 | ||
163c8a59 | 1352 | static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num) |
1074df4f | 1353 | { |
e822a52a | 1354 | bus = pci_find_bus(bus, bus_num); |
502a5395 | 1355 | if (bus) { |
163c8a59 LC |
1356 | return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }", |
1357 | bus_num, pci_get_devices_list(bus, bus_num)); | |
f2aa58c6 | 1358 | } |
163c8a59 LC |
1359 | |
1360 | return NULL; | |
f2aa58c6 FB |
1361 | } |
1362 | ||
163c8a59 LC |
1363 | /** |
1364 | * do_pci_info(): PCI buses and devices information | |
1365 | * | |
1366 | * The returned QObject is a QList of all buses. Each bus is | |
1367 | * represented by a QDict, which has a key with a QList of all | |
1368 | * PCI devices attached to it. Each device is represented by | |
1369 | * a QDict. | |
1370 | * | |
1371 | * The bus QDict contains the following: | |
1372 | * | |
1373 | * - "bus": bus number | |
1374 | * - "devices": a QList of QDicts, each QDict represents a PCI | |
1375 | * device | |
1376 | * | |
1377 | * The PCI device QDict contains the following: | |
1378 | * | |
1379 | * - "bus": identical to the parent's bus number | |
1380 | * - "slot": slot number | |
1381 | * - "function": function number | |
1382 | * - "class_info": a QDict containing: | |
1383 | * - "desc": device class description (optional) | |
1384 | * - "class": device class number | |
1385 | * - "id": a QDict containing: | |
1386 | * - "device": device ID | |
1387 | * - "vendor": vendor ID | |
1388 | * - "irq": device's IRQ if assigned (optional) | |
1389 | * - "qdev_id": qdev id string | |
1390 | * - "pci_bridge": It's a QDict, only present if this device is a | |
1391 | * PCI bridge, contains: | |
1392 | * - "bus": bus number | |
1393 | * - "secondary": secondary bus number | |
1394 | * - "subordinate": subordinate bus number | |
1395 | * - "io_range": a QDict with memory range information | |
1396 | * - "memory_range": a QDict with memory range information | |
1397 | * - "prefetchable_range": a QDict with memory range information | |
d5e4acf7 | 1398 | * - "devices": a QList of PCI devices if there's any attached (optional) |
163c8a59 LC |
1399 | * - "regions": a QList of QDicts, each QDict represents a |
1400 | * memory region of this device | |
1401 | * | |
1402 | * The memory range QDict contains the following: | |
1403 | * | |
1404 | * - "base": base memory address | |
1405 | * - "limit": limit value | |
1406 | * | |
1407 | * The region QDict can be an I/O region or a memory region, | |
1408 | * an I/O region QDict contains the following: | |
1409 | * | |
1410 | * - "type": "io" | |
1411 | * - "bar": BAR number | |
1412 | * - "address": memory address | |
1413 | * - "size": memory size | |
1414 | * | |
1415 | * A memory region QDict contains the following: | |
1416 | * | |
1417 | * - "type": "memory" | |
1418 | * - "bar": BAR number | |
1419 | * - "address": memory address | |
1420 | * - "size": memory size | |
1421 | * - "mem_type_64": true or false | |
1422 | * - "prefetch": true or false | |
1423 | */ | |
1424 | void do_pci_info(Monitor *mon, QObject **ret_data) | |
f2aa58c6 | 1425 | { |
163c8a59 | 1426 | QList *bus_list; |
e822a52a | 1427 | struct PCIHostBus *host; |
163c8a59 LC |
1428 | |
1429 | bus_list = qlist_new(); | |
1430 | ||
e822a52a | 1431 | QLIST_FOREACH(host, &host_buses, next) { |
163c8a59 LC |
1432 | QObject *obj = pci_get_bus_dict(host->bus, 0); |
1433 | if (obj) { | |
1434 | qlist_append_obj(bus_list, obj); | |
1435 | } | |
e822a52a | 1436 | } |
163c8a59 LC |
1437 | |
1438 | *ret_data = QOBJECT(bus_list); | |
77d4bc34 | 1439 | } |
a41b2ff2 | 1440 | |
cb457d76 AL |
1441 | static const char * const pci_nic_models[] = { |
1442 | "ne2k_pci", | |
1443 | "i82551", | |
1444 | "i82557b", | |
1445 | "i82559er", | |
1446 | "rtl8139", | |
1447 | "e1000", | |
1448 | "pcnet", | |
1449 | "virtio", | |
1450 | NULL | |
1451 | }; | |
1452 | ||
9d07d757 PB |
1453 | static const char * const pci_nic_names[] = { |
1454 | "ne2k_pci", | |
1455 | "i82551", | |
1456 | "i82557b", | |
1457 | "i82559er", | |
1458 | "rtl8139", | |
1459 | "e1000", | |
1460 | "pcnet", | |
53c25cea | 1461 | "virtio-net-pci", |
cb457d76 AL |
1462 | NULL |
1463 | }; | |
1464 | ||
a41b2ff2 | 1465 | /* Initialize a PCI NIC. */ |
33e66b86 | 1466 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1467 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1468 | const char *default_devaddr) | |
a41b2ff2 | 1469 | { |
5607c388 | 1470 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1471 | PCIBus *bus; |
1472 | int devfn; | |
5607c388 | 1473 | PCIDevice *pci_dev; |
9d07d757 | 1474 | DeviceState *dev; |
cb457d76 AL |
1475 | int i; |
1476 | ||
07caea31 MA |
1477 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1478 | if (i < 0) | |
1479 | return NULL; | |
1480 | ||
1481 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1482 | if (!bus) { | |
1ecda02b MA |
1483 | error_report("Invalid PCI device address %s for device %s", |
1484 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1485 | return NULL; |
1486 | } | |
1487 | ||
499cf102 | 1488 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1489 | dev = &pci_dev->qdev; |
dea7b3b9 MM |
1490 | if (nd->name) |
1491 | dev->id = qemu_strdup(nd->name); | |
1cc33683 | 1492 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1493 | if (qdev_init(dev) < 0) |
1494 | return NULL; | |
9ee05825 | 1495 | return pci_dev; |
a41b2ff2 PB |
1496 | } |
1497 | ||
07caea31 MA |
1498 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1499 | const char *default_devaddr) | |
1500 | { | |
1501 | PCIDevice *res; | |
1502 | ||
1503 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1504 | exit(0); | |
1505 | ||
1506 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1507 | if (!res) | |
1508 | exit(1); | |
1509 | return res; | |
1510 | } | |
1511 | ||
80b3ada7 PB |
1512 | typedef struct { |
1513 | PCIDevice dev; | |
03587182 GH |
1514 | PCIBus bus; |
1515 | uint32_t vid; | |
1516 | uint32_t did; | |
80b3ada7 PB |
1517 | } PCIBridge; |
1518 | ||
a0c7a97e IY |
1519 | |
1520 | static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) | |
1521 | { | |
1522 | pci_update_mappings(d); | |
1523 | } | |
1524 | ||
1525 | static void pci_bridge_update_mappings(PCIBus *b) | |
1526 | { | |
1527 | PCIBus *child; | |
1528 | ||
1529 | pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); | |
1530 | ||
1531 | QLIST_FOREACH(child, &b->child, sibling) { | |
1532 | pci_bridge_update_mappings(child); | |
1533 | } | |
1534 | } | |
1535 | ||
9596ebb7 | 1536 | static void pci_bridge_write_config(PCIDevice *d, |
80b3ada7 PB |
1537 | uint32_t address, uint32_t val, int len) |
1538 | { | |
80b3ada7 | 1539 | pci_default_write_config(d, address, val, len); |
a0c7a97e IY |
1540 | |
1541 | if (/* io base/limit */ | |
1542 | ranges_overlap(address, len, PCI_IO_BASE, 2) || | |
1543 | ||
1544 | /* memory base/limit, prefetchable base/limit and | |
1545 | io base/limit upper 16 */ | |
1546 | ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { | |
1547 | pci_bridge_update_mappings(d->bus); | |
1548 | } | |
80b3ada7 PB |
1549 | } |
1550 | ||
e822a52a | 1551 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 1552 | { |
470e6363 | 1553 | PCIBus *sec; |
3ae80618 | 1554 | |
470e6363 | 1555 | if (!bus) { |
e822a52a | 1556 | return NULL; |
470e6363 | 1557 | } |
3ae80618 | 1558 | |
e822a52a IY |
1559 | if (pci_bus_num(bus) == bus_num) { |
1560 | return bus; | |
1561 | } | |
1562 | ||
1563 | /* try child bus */ | |
470e6363 IY |
1564 | if (!bus->parent_dev /* host pci bridge */ || |
1565 | (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1566 | bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { | |
1567 | for (; bus; bus = sec) { | |
1568 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1569 | assert(sec->parent_dev); | |
1570 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1571 | return sec; | |
1572 | } | |
1573 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1574 | bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) { | |
1575 | break; | |
1576 | } | |
c021f8e6 | 1577 | } |
e822a52a IY |
1578 | } |
1579 | } | |
1580 | ||
1581 | return NULL; | |
3ae80618 AL |
1582 | } |
1583 | ||
e822a52a | 1584 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
3ae80618 | 1585 | { |
e822a52a | 1586 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
1587 | |
1588 | if (!bus) | |
1589 | return NULL; | |
1590 | ||
1591 | return bus->devices[PCI_DEVFN(slot, function)]; | |
1592 | } | |
1593 | ||
03587182 | 1594 | static int pci_bridge_initfn(PCIDevice *dev) |
80b3ada7 | 1595 | { |
03587182 | 1596 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
480b9f24 | 1597 | |
03587182 GH |
1598 | pci_config_set_vendor_id(s->dev.config, s->vid); |
1599 | pci_config_set_device_id(s->dev.config, s->did); | |
480b9f24 | 1600 | |
74c01823 IY |
1601 | pci_set_word(dev->config + PCI_STATUS, |
1602 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
1603 | pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); | |
d6318738 | 1604 | dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; |
74c01823 IY |
1605 | pci_set_word(dev->config + PCI_SEC_STATUS, |
1606 | PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); | |
03587182 GH |
1607 | return 0; |
1608 | } | |
80b3ada7 | 1609 | |
e822a52a IY |
1610 | static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1611 | { | |
1612 | PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); | |
1613 | PCIBus *bus = &s->bus; | |
1614 | pci_unregister_secondary_bus(bus); | |
1615 | return 0; | |
1616 | } | |
1617 | ||
03587182 GH |
1618 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
1619 | pci_map_irq_fn map_irq, const char *name) | |
1620 | { | |
1621 | PCIDevice *dev; | |
1622 | PCIBridge *s; | |
1623 | ||
499cf102 | 1624 | dev = pci_create(bus, devfn, "pci-bridge"); |
03587182 GH |
1625 | qdev_prop_set_uint32(&dev->qdev, "vendorid", vid); |
1626 | qdev_prop_set_uint32(&dev->qdev, "deviceid", did); | |
e23a1b33 | 1627 | qdev_init_nofail(&dev->qdev); |
03587182 GH |
1628 | |
1629 | s = DO_UPCAST(PCIBridge, dev, dev); | |
e822a52a | 1630 | pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
03587182 | 1631 | return &s->bus; |
80b3ada7 | 1632 | } |
6b1b92d3 | 1633 | |
d6318738 MT |
1634 | PCIDevice *pci_bridge_get_device(PCIBus *bus) |
1635 | { | |
1636 | return bus->parent_dev; | |
1637 | } | |
1638 | ||
81a322d4 | 1639 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1640 | { |
1641 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1642 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1643 | PCIBus *bus; |
ee995ffb | 1644 | int devfn, rc; |
6b1b92d3 | 1645 | |
a9f49946 IY |
1646 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1647 | if (info->is_express) { | |
1648 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1649 | } | |
1650 | ||
02e2da45 | 1651 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 1652 | devfn = pci_dev->devfn; |
16eaedf2 | 1653 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
fb231628 IY |
1654 | info->config_read, info->config_write, |
1655 | info->header_type); | |
09e3acc6 GH |
1656 | if (pci_dev == NULL) |
1657 | return -1; | |
ee995ffb | 1658 | rc = info->init(pci_dev); |
925fe64a AW |
1659 | if (rc != 0) { |
1660 | do_pci_unregister_device(pci_dev); | |
ee995ffb | 1661 | return rc; |
925fe64a | 1662 | } |
8c52c8f3 GH |
1663 | |
1664 | /* rom loading */ | |
1665 | if (pci_dev->romfile == NULL && info->romfile != NULL) | |
1666 | pci_dev->romfile = qemu_strdup(info->romfile); | |
1667 | pci_add_option_rom(pci_dev); | |
1668 | ||
ee995ffb | 1669 | if (qdev->hotplugged) |
87c30546 | 1670 | bus->hotplug(bus->hotplug_qdev, pci_dev, 1); |
ee995ffb GH |
1671 | return 0; |
1672 | } | |
1673 | ||
1674 | static int pci_unplug_device(DeviceState *qdev) | |
1675 | { | |
1676 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
1677 | ||
87c30546 | 1678 | dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0); |
ee995ffb | 1679 | return 0; |
6b1b92d3 PB |
1680 | } |
1681 | ||
0aab0d3a | 1682 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1683 | { |
02e2da45 | 1684 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1685 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1686 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1687 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1688 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1689 | } |
1690 | ||
0aab0d3a GH |
1691 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1692 | { | |
1693 | while (info->qdev.name) { | |
1694 | pci_qdev_register(info); | |
1695 | info++; | |
1696 | } | |
1697 | } | |
1698 | ||
499cf102 | 1699 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
6b1b92d3 PB |
1700 | { |
1701 | DeviceState *dev; | |
1702 | ||
02e2da45 | 1703 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1704 | qdev_prop_set_uint32(dev, "addr", devfn); |
71077c1c GH |
1705 | return DO_UPCAST(PCIDevice, qdev, dev); |
1706 | } | |
6b1b92d3 | 1707 | |
71077c1c GH |
1708 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1709 | { | |
499cf102 | 1710 | PCIDevice *dev = pci_create(bus, devfn, name); |
e23a1b33 | 1711 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1712 | return dev; |
6b1b92d3 | 1713 | } |
6f4cbd39 MT |
1714 | |
1715 | static int pci_find_space(PCIDevice *pdev, uint8_t size) | |
1716 | { | |
a9f49946 | 1717 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1718 | int offset = PCI_CONFIG_HEADER_SIZE; |
1719 | int i; | |
a9f49946 | 1720 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1721 | if (pdev->used[i]) |
1722 | offset = i + 1; | |
1723 | else if (i - offset + 1 == size) | |
1724 | return offset; | |
1725 | return 0; | |
1726 | } | |
1727 | ||
1728 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1729 | uint8_t *prev_p) | |
1730 | { | |
1731 | uint8_t next, prev; | |
1732 | ||
1733 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1734 | return 0; | |
1735 | ||
1736 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1737 | prev = next + PCI_CAP_LIST_NEXT) | |
1738 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1739 | break; | |
1740 | ||
1741 | if (prev_p) | |
1742 | *prev_p = prev; | |
1743 | return next; | |
1744 | } | |
1745 | ||
c2039bd0 AL |
1746 | static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1747 | { | |
1748 | cpu_register_physical_memory(addr, size, pdev->rom_offset); | |
1749 | } | |
1750 | ||
1751 | /* Add an option rom for the device */ | |
8c52c8f3 | 1752 | static int pci_add_option_rom(PCIDevice *pdev) |
c2039bd0 AL |
1753 | { |
1754 | int size; | |
1755 | char *path; | |
1756 | void *ptr; | |
1757 | ||
8c52c8f3 GH |
1758 | if (!pdev->romfile) |
1759 | return 0; | |
1760 | if (strlen(pdev->romfile) == 0) | |
1761 | return 0; | |
1762 | ||
88169ddf GH |
1763 | if (!pdev->rom_bar) { |
1764 | /* | |
1765 | * Load rom via fw_cfg instead of creating a rom bar, | |
1766 | * for 0.11 compatibility. | |
1767 | */ | |
1768 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1769 | if (class == 0x0300) { | |
1770 | rom_add_vga(pdev->romfile); | |
1771 | } else { | |
1772 | rom_add_option(pdev->romfile); | |
1773 | } | |
1774 | return 0; | |
1775 | } | |
1776 | ||
8c52c8f3 | 1777 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1778 | if (path == NULL) { |
8c52c8f3 | 1779 | path = qemu_strdup(pdev->romfile); |
c2039bd0 AL |
1780 | } |
1781 | ||
1782 | size = get_image_size(path); | |
8c52c8f3 | 1783 | if (size < 0) { |
1ecda02b MA |
1784 | error_report("%s: failed to find romfile \"%s\"", |
1785 | __FUNCTION__, pdev->romfile); | |
8c52c8f3 GH |
1786 | return -1; |
1787 | } | |
c2039bd0 AL |
1788 | if (size & (size - 1)) { |
1789 | size = 1 << qemu_fls(size); | |
1790 | } | |
1791 | ||
1792 | pdev->rom_offset = qemu_ram_alloc(size); | |
1793 | ||
1794 | ptr = qemu_get_ram_ptr(pdev->rom_offset); | |
1795 | load_image(path, ptr); | |
1796 | qemu_free(path); | |
1797 | ||
1798 | pci_register_bar(pdev, PCI_ROM_SLOT, size, | |
1799 | 0, pci_map_option_rom); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
6f4cbd39 | 1804 | /* Reserve space and add capability to the linked list in pci config space */ |
1db5a3aa MT |
1805 | int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id, |
1806 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1807 | { |
6f4cbd39 | 1808 | uint8_t *config = pdev->config + offset; |
6f4cbd39 MT |
1809 | config[PCI_CAP_LIST_ID] = cap_id; |
1810 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1811 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1812 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1813 | memset(pdev->used + offset, 0xFF, size); | |
1814 | /* Make capability read-only by default */ | |
1815 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1816 | /* Check capability by default */ |
1817 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1818 | return offset; |
1819 | } | |
1820 | ||
1db5a3aa MT |
1821 | /* Find and reserve space and add capability to the linked list |
1822 | * in pci config space */ | |
1823 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1824 | { | |
1825 | uint8_t offset = pci_find_space(pdev, size); | |
1826 | if (!offset) { | |
1827 | return -ENOSPC; | |
1828 | } | |
1829 | return pci_add_capability_at_offset(pdev, cap_id, offset, size); | |
1830 | } | |
1831 | ||
6f4cbd39 MT |
1832 | /* Unlink capability from the pci config space. */ |
1833 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1834 | { | |
1835 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1836 | if (!offset) | |
1837 | return; | |
1838 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
1839 | /* Make capability writeable again */ | |
1840 | memset(pdev->wmask + offset, 0xff, size); | |
bd4b65ee MT |
1841 | /* Clear cmask as device-specific registers can't be checked */ |
1842 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1843 | memset(pdev->used + offset, 0, size); |
1844 | ||
1845 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1846 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1847 | } | |
1848 | ||
1849 | /* Reserve space for capability at a known offset (to call after load). */ | |
1850 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1851 | { | |
1852 | memset(pdev->used + offset, 0xff, size); | |
1853 | } | |
1854 | ||
1855 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1856 | { | |
1857 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1858 | } | |
10c4c98a GH |
1859 | |
1860 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1861 | { | |
1862 | PCIDevice *d = (PCIDevice *)dev; | |
1863 | const pci_class_desc *desc; | |
1864 | char ctxt[64]; | |
1865 | PCIIORegion *r; | |
1866 | int i, class; | |
1867 | ||
b0ff8eb2 | 1868 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1869 | desc = pci_class_descriptions; |
1870 | while (desc->desc && class != desc->class) | |
1871 | desc++; | |
1872 | if (desc->desc) { | |
1873 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1874 | } else { | |
1875 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1876 | } | |
1877 | ||
1878 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1879 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1880 | indent, "", ctxt, | |
e822a52a IY |
1881 | d->config[PCI_SECONDARY_BUS], |
1882 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), | |
b0ff8eb2 IY |
1883 | pci_get_word(d->config + PCI_VENDOR_ID), |
1884 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1885 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1886 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1887 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1888 | r = &d->io_regions[i]; | |
1889 | if (!r->size) | |
1890 | continue; | |
89e8b13c IY |
1891 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1892 | " [0x%"FMT_PCIBUS"]\n", | |
1893 | indent, "", | |
0392a017 | 1894 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1895 | r->addr, r->addr + r->size - 1); |
1896 | } | |
1897 | } | |
03587182 GH |
1898 | |
1899 | static PCIDeviceInfo bridge_info = { | |
1900 | .qdev.name = "pci-bridge", | |
1901 | .qdev.size = sizeof(PCIBridge), | |
1902 | .init = pci_bridge_initfn, | |
e822a52a | 1903 | .exit = pci_bridge_exitfn, |
03587182 | 1904 | .config_write = pci_bridge_write_config, |
776e1bbb | 1905 | .header_type = PCI_HEADER_TYPE_BRIDGE, |
03587182 GH |
1906 | .qdev.props = (Property[]) { |
1907 | DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), | |
1908 | DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), | |
1909 | DEFINE_PROP_END_OF_LIST(), | |
1910 | } | |
1911 | }; | |
1912 | ||
1913 | static void pci_register_devices(void) | |
1914 | { | |
1915 | pci_qdev_register(&bridge_info); | |
1916 | } | |
1917 | ||
1918 | device_init(pci_register_devices) |