]>
Commit | Line | Data |
---|---|---|
69b91039 FB |
1 | /* |
2 | * QEMU PCI bus manager | |
3 | * | |
4 | * Copyright (c) 2004 Fabrice Bellard | |
5fafdf24 | 5 | * |
69b91039 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
783753fd | 26 | #include "pci_bridge.h" |
cfb0a50a | 27 | #include "pci_internals.h" |
376253ec | 28 | #include "monitor.h" |
87ecb68b | 29 | #include "net.h" |
880345c4 | 30 | #include "sysemu.h" |
c2039bd0 | 31 | #include "loader.h" |
163c8a59 | 32 | #include "qemu-objects.h" |
69b91039 FB |
33 | |
34 | //#define DEBUG_PCI | |
d8d2e079 | 35 | #ifdef DEBUG_PCI |
2e49d64a | 36 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
d8d2e079 IY |
37 | #else |
38 | # define PCI_DPRINTF(format, ...) do { } while (0) | |
39 | #endif | |
69b91039 | 40 | |
10c4c98a | 41 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
4f43c1ff | 42 | static char *pcibus_get_dev_path(DeviceState *dev); |
10c4c98a | 43 | |
cfb0a50a | 44 | struct BusInfo pci_bus_info = { |
10c4c98a GH |
45 | .name = "PCI", |
46 | .size = sizeof(PCIBus), | |
47 | .print_dev = pcibus_dev_print, | |
4f43c1ff | 48 | .get_dev_path = pcibus_get_dev_path, |
ee6847d1 | 49 | .props = (Property[]) { |
54586bd1 | 50 | DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
8c52c8f3 | 51 | DEFINE_PROP_STRING("romfile", PCIDevice, romfile), |
88169ddf | 52 | DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
49823868 IY |
53 | DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, |
54 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), | |
54586bd1 | 55 | DEFINE_PROP_END_OF_LIST() |
ee6847d1 | 56 | } |
30468f78 | 57 | }; |
69b91039 | 58 | |
1941d19c | 59 | static void pci_update_mappings(PCIDevice *d); |
d537cf6c | 60 | static void pci_set_irq(void *opaque, int irq_num, int level); |
8c52c8f3 | 61 | static int pci_add_option_rom(PCIDevice *pdev); |
230741dc | 62 | static void pci_del_option_rom(PCIDevice *pdev); |
1941d19c | 63 | |
d350d97d AL |
64 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
65 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; | |
e822a52a IY |
66 | |
67 | struct PCIHostBus { | |
68 | int domain; | |
69 | struct PCIBus *bus; | |
70 | QLIST_ENTRY(PCIHostBus) next; | |
71 | }; | |
72 | static QLIST_HEAD(, PCIHostBus) host_buses; | |
30468f78 | 73 | |
2d1e9f96 JQ |
74 | static const VMStateDescription vmstate_pcibus = { |
75 | .name = "PCIBUS", | |
76 | .version_id = 1, | |
77 | .minimum_version_id = 1, | |
78 | .minimum_version_id_old = 1, | |
79 | .fields = (VMStateField []) { | |
80 | VMSTATE_INT32_EQUAL(nirq, PCIBus), | |
c7bde572 | 81 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), |
2d1e9f96 | 82 | VMSTATE_END_OF_LIST() |
52fc1d83 | 83 | } |
2d1e9f96 | 84 | }; |
52fc1d83 | 85 | |
b3b11697 | 86 | static int pci_bar(PCIDevice *d, int reg) |
5330de09 | 87 | { |
b3b11697 IY |
88 | uint8_t type; |
89 | ||
90 | if (reg != PCI_ROM_SLOT) | |
91 | return PCI_BASE_ADDRESS_0 + reg * 4; | |
92 | ||
93 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
94 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; | |
5330de09 MT |
95 | } |
96 | ||
d036bb21 MT |
97 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
98 | { | |
99 | return (d->irq_state >> irq_num) & 0x1; | |
100 | } | |
101 | ||
102 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) | |
103 | { | |
104 | d->irq_state &= ~(0x1 << irq_num); | |
105 | d->irq_state |= level << irq_num; | |
106 | } | |
107 | ||
108 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) | |
109 | { | |
110 | PCIBus *bus; | |
111 | for (;;) { | |
112 | bus = pci_dev->bus; | |
113 | irq_num = bus->map_irq(pci_dev, irq_num); | |
114 | if (bus->set_irq) | |
115 | break; | |
116 | pci_dev = bus->parent_dev; | |
117 | } | |
118 | bus->irq_count[irq_num] += change; | |
119 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); | |
120 | } | |
121 | ||
f9bf77dd MT |
122 | /* Update interrupt status bit in config space on interrupt |
123 | * state change. */ | |
124 | static void pci_update_irq_status(PCIDevice *dev) | |
125 | { | |
126 | if (dev->irq_state) { | |
127 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; | |
128 | } else { | |
129 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
130 | } | |
131 | } | |
132 | ||
5330de09 MT |
133 | static void pci_device_reset(PCIDevice *dev) |
134 | { | |
c0b1905b MT |
135 | int r; |
136 | ||
d036bb21 | 137 | dev->irq_state = 0; |
f9bf77dd | 138 | pci_update_irq_status(dev); |
71ebd6dc IY |
139 | /* Clear all writeable bits */ |
140 | pci_set_word(dev->config + PCI_COMMAND, | |
141 | pci_get_word(dev->config + PCI_COMMAND) & | |
142 | ~pci_get_word(dev->wmask + PCI_COMMAND)); | |
c0b1905b MT |
143 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
144 | dev->config[PCI_INTERRUPT_LINE] = 0x0; | |
145 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { | |
71ebd6dc IY |
146 | PCIIORegion *region = &dev->io_regions[r]; |
147 | if (!region->size) { | |
c0b1905b MT |
148 | continue; |
149 | } | |
71ebd6dc IY |
150 | |
151 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && | |
152 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
153 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); | |
154 | } else { | |
155 | pci_set_long(dev->config + pci_bar(dev, r), region->type); | |
156 | } | |
c0b1905b MT |
157 | } |
158 | pci_update_mappings(dev); | |
5330de09 MT |
159 | } |
160 | ||
6eaa6847 GN |
161 | static void pci_bus_reset(void *opaque) |
162 | { | |
a60380a5 | 163 | PCIBus *bus = opaque; |
6eaa6847 GN |
164 | int i; |
165 | ||
166 | for (i = 0; i < bus->nirq; i++) { | |
167 | bus->irq_count[i] = 0; | |
168 | } | |
5330de09 MT |
169 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
170 | if (bus->devices[i]) { | |
171 | pci_device_reset(bus->devices[i]); | |
172 | } | |
6eaa6847 GN |
173 | } |
174 | } | |
175 | ||
e822a52a IY |
176 | static void pci_host_bus_register(int domain, PCIBus *bus) |
177 | { | |
178 | struct PCIHostBus *host; | |
179 | host = qemu_mallocz(sizeof(*host)); | |
180 | host->domain = domain; | |
181 | host->bus = bus; | |
182 | QLIST_INSERT_HEAD(&host_buses, host, next); | |
183 | } | |
184 | ||
c469e1dd | 185 | PCIBus *pci_find_root_bus(int domain) |
e822a52a IY |
186 | { |
187 | struct PCIHostBus *host; | |
188 | ||
189 | QLIST_FOREACH(host, &host_buses, next) { | |
190 | if (host->domain == domain) { | |
191 | return host->bus; | |
192 | } | |
193 | } | |
194 | ||
195 | return NULL; | |
196 | } | |
197 | ||
e075e788 IY |
198 | int pci_find_domain(const PCIBus *bus) |
199 | { | |
200 | PCIDevice *d; | |
201 | struct PCIHostBus *host; | |
202 | ||
203 | /* obtain root bus */ | |
204 | while ((d = bus->parent_dev) != NULL) { | |
205 | bus = d->bus; | |
206 | } | |
207 | ||
208 | QLIST_FOREACH(host, &host_buses, next) { | |
209 | if (host->bus == bus) { | |
210 | return host->domain; | |
211 | } | |
212 | } | |
213 | ||
214 | abort(); /* should not be reached */ | |
215 | return -1; | |
216 | } | |
217 | ||
21eea4b3 GH |
218 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
219 | const char *name, int devfn_min) | |
30468f78 | 220 | { |
21eea4b3 | 221 | qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
6fa84913 | 222 | assert(PCI_FUNC(devfn_min) == 0); |
502a5395 | 223 | bus->devfn_min = devfn_min; |
e822a52a IY |
224 | |
225 | /* host bridge */ | |
226 | QLIST_INIT(&bus->child); | |
227 | pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ | |
228 | ||
0be71e32 | 229 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
a08d4367 | 230 | qemu_register_reset(pci_bus_reset, bus); |
21eea4b3 GH |
231 | } |
232 | ||
233 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) | |
234 | { | |
235 | PCIBus *bus; | |
236 | ||
237 | bus = qemu_mallocz(sizeof(*bus)); | |
238 | bus->qbus.qdev_allocated = 1; | |
239 | pci_bus_new_inplace(bus, parent, name, devfn_min); | |
240 | return bus; | |
241 | } | |
242 | ||
243 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
244 | void *irq_opaque, int nirq) | |
245 | { | |
246 | bus->set_irq = set_irq; | |
247 | bus->map_irq = map_irq; | |
248 | bus->irq_opaque = irq_opaque; | |
249 | bus->nirq = nirq; | |
250 | bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); | |
251 | } | |
252 | ||
87c30546 | 253 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) |
ee995ffb GH |
254 | { |
255 | bus->qbus.allow_hotplug = 1; | |
256 | bus->hotplug = hotplug; | |
87c30546 | 257 | bus->hotplug_qdev = qdev; |
ee995ffb GH |
258 | } |
259 | ||
2e01c8cf BS |
260 | void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base) |
261 | { | |
262 | bus->mem_base = base; | |
263 | } | |
264 | ||
21eea4b3 GH |
265 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
266 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
267 | void *irq_opaque, int devfn_min, int nirq) | |
268 | { | |
269 | PCIBus *bus; | |
270 | ||
271 | bus = pci_bus_new(parent, name, devfn_min); | |
272 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); | |
30468f78 FB |
273 | return bus; |
274 | } | |
69b91039 | 275 | |
502a5395 PB |
276 | int pci_bus_num(PCIBus *s) |
277 | { | |
e94ff650 IY |
278 | if (!s->parent_dev) |
279 | return 0; /* pci host bridge */ | |
280 | return s->parent_dev->config[PCI_SECONDARY_BUS]; | |
502a5395 PB |
281 | } |
282 | ||
73534f2f | 283 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
30ca2aab | 284 | { |
73534f2f | 285 | PCIDevice *s = container_of(pv, PCIDevice, config); |
a9f49946 | 286 | uint8_t *config; |
52fc1d83 AZ |
287 | int i; |
288 | ||
a9f49946 IY |
289 | assert(size == pci_config_size(s)); |
290 | config = qemu_malloc(size); | |
291 | ||
292 | qemu_get_buffer(f, config, size); | |
293 | for (i = 0; i < size; ++i) { | |
294 | if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) { | |
295 | qemu_free(config); | |
bd4b65ee | 296 | return -EINVAL; |
a9f49946 IY |
297 | } |
298 | } | |
299 | memcpy(s->config, config, size); | |
bd4b65ee | 300 | |
1941d19c | 301 | pci_update_mappings(s); |
52fc1d83 | 302 | |
a9f49946 | 303 | qemu_free(config); |
30ca2aab FB |
304 | return 0; |
305 | } | |
306 | ||
73534f2f | 307 | /* just put buffer */ |
84e2e3eb | 308 | static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
73534f2f | 309 | { |
dbe73d7f | 310 | const uint8_t **v = pv; |
a9f49946 | 311 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
dbe73d7f | 312 | qemu_put_buffer(f, *v, size); |
73534f2f JQ |
313 | } |
314 | ||
315 | static VMStateInfo vmstate_info_pci_config = { | |
316 | .name = "pci config", | |
317 | .get = get_pci_config_device, | |
318 | .put = put_pci_config_device, | |
319 | }; | |
320 | ||
d036bb21 MT |
321 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
322 | { | |
c3f8f611 | 323 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
324 | uint32_t irq_state[PCI_NUM_PINS]; |
325 | int i; | |
326 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
327 | irq_state[i] = qemu_get_be32(f); | |
328 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { | |
329 | fprintf(stderr, "irq state %d: must be 0 or 1.\n", | |
330 | irq_state[i]); | |
331 | return -EINVAL; | |
332 | } | |
333 | } | |
334 | ||
335 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
336 | pci_set_irq_state(s, i, irq_state[i]); | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) | |
343 | { | |
344 | int i; | |
c3f8f611 | 345 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
d036bb21 MT |
346 | |
347 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
348 | qemu_put_be32(f, pci_irq_state(s, i)); | |
349 | } | |
350 | } | |
351 | ||
352 | static VMStateInfo vmstate_info_pci_irq_state = { | |
353 | .name = "pci irq state", | |
354 | .get = get_pci_irq_state, | |
355 | .put = put_pci_irq_state, | |
356 | }; | |
357 | ||
73534f2f JQ |
358 | const VMStateDescription vmstate_pci_device = { |
359 | .name = "PCIDevice", | |
360 | .version_id = 2, | |
361 | .minimum_version_id = 1, | |
362 | .minimum_version_id_old = 1, | |
363 | .fields = (VMStateField []) { | |
364 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
a9f49946 IY |
365 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, |
366 | vmstate_info_pci_config, | |
367 | PCI_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
368 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
369 | vmstate_info_pci_irq_state, | |
370 | PCI_NUM_PINS * sizeof(int32_t)), | |
a9f49946 IY |
371 | VMSTATE_END_OF_LIST() |
372 | } | |
373 | }; | |
374 | ||
375 | const VMStateDescription vmstate_pcie_device = { | |
376 | .name = "PCIDevice", | |
377 | .version_id = 2, | |
378 | .minimum_version_id = 1, | |
379 | .minimum_version_id_old = 1, | |
380 | .fields = (VMStateField []) { | |
381 | VMSTATE_INT32_LE(version_id, PCIDevice), | |
382 | VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, | |
383 | vmstate_info_pci_config, | |
384 | PCIE_CONFIG_SPACE_SIZE), | |
d036bb21 MT |
385 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
386 | vmstate_info_pci_irq_state, | |
387 | PCI_NUM_PINS * sizeof(int32_t)), | |
73534f2f JQ |
388 | VMSTATE_END_OF_LIST() |
389 | } | |
390 | }; | |
391 | ||
a9f49946 IY |
392 | static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
393 | { | |
394 | return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; | |
395 | } | |
396 | ||
73534f2f JQ |
397 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
398 | { | |
f9bf77dd MT |
399 | /* Clear interrupt status bit: it is implicit |
400 | * in irq_state which we are saving. | |
401 | * This makes us compatible with old devices | |
402 | * which never set or clear this bit. */ | |
403 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; | |
a9f49946 | 404 | vmstate_save_state(f, pci_get_vmstate(s), s); |
f9bf77dd MT |
405 | /* Restore the interrupt status bit. */ |
406 | pci_update_irq_status(s); | |
73534f2f JQ |
407 | } |
408 | ||
409 | int pci_device_load(PCIDevice *s, QEMUFile *f) | |
410 | { | |
f9bf77dd MT |
411 | int ret; |
412 | ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); | |
413 | /* Restore the interrupt status bit. */ | |
414 | pci_update_irq_status(s); | |
415 | return ret; | |
73534f2f JQ |
416 | } |
417 | ||
5e434f4e | 418 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
d350d97d | 419 | { |
5e434f4e IY |
420 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
421 | pci_default_sub_vendor_id); | |
422 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
423 | pci_default_sub_device_id); | |
d350d97d AL |
424 | } |
425 | ||
880345c4 | 426 | /* |
43c945f1 IY |
427 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
428 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error | |
880345c4 | 429 | */ |
43c945f1 IY |
430 | int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
431 | unsigned int *slotp, unsigned int *funcp) | |
880345c4 AL |
432 | { |
433 | const char *p; | |
434 | char *e; | |
435 | unsigned long val; | |
436 | unsigned long dom = 0, bus = 0; | |
43c945f1 IY |
437 | unsigned int slot = 0; |
438 | unsigned int func = 0; | |
880345c4 AL |
439 | |
440 | p = addr; | |
441 | val = strtoul(p, &e, 16); | |
442 | if (e == p) | |
443 | return -1; | |
444 | if (*e == ':') { | |
445 | bus = val; | |
446 | p = e + 1; | |
447 | val = strtoul(p, &e, 16); | |
448 | if (e == p) | |
449 | return -1; | |
450 | if (*e == ':') { | |
451 | dom = bus; | |
452 | bus = val; | |
453 | p = e + 1; | |
454 | val = strtoul(p, &e, 16); | |
455 | if (e == p) | |
456 | return -1; | |
457 | } | |
458 | } | |
459 | ||
880345c4 AL |
460 | slot = val; |
461 | ||
43c945f1 IY |
462 | if (funcp != NULL) { |
463 | if (*e != '.') | |
464 | return -1; | |
465 | ||
466 | p = e + 1; | |
467 | val = strtoul(p, &e, 16); | |
468 | if (e == p) | |
469 | return -1; | |
470 | ||
471 | func = val; | |
472 | } | |
473 | ||
474 | /* if funcp == NULL func is 0 */ | |
475 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) | |
476 | return -1; | |
477 | ||
880345c4 AL |
478 | if (*e) |
479 | return -1; | |
480 | ||
481 | /* Note: QEMU doesn't implement domains other than 0 */ | |
c469e1dd | 482 | if (!pci_find_bus(pci_find_root_bus(dom), bus)) |
880345c4 AL |
483 | return -1; |
484 | ||
485 | *domp = dom; | |
486 | *busp = bus; | |
487 | *slotp = slot; | |
43c945f1 IY |
488 | if (funcp != NULL) |
489 | *funcp = func; | |
880345c4 AL |
490 | return 0; |
491 | } | |
492 | ||
e9283f8b JK |
493 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
494 | unsigned *slotp) | |
880345c4 | 495 | { |
e9283f8b JK |
496 | /* strip legacy tag */ |
497 | if (!strncmp(addr, "pci_addr=", 9)) { | |
498 | addr += 9; | |
499 | } | |
43c945f1 | 500 | if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { |
e9283f8b | 501 | monitor_printf(mon, "Invalid pci address\n"); |
880345c4 | 502 | return -1; |
e9283f8b JK |
503 | } |
504 | return 0; | |
880345c4 AL |
505 | } |
506 | ||
49bd1458 | 507 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
5607c388 MA |
508 | { |
509 | int dom, bus; | |
510 | unsigned slot; | |
511 | ||
512 | if (!devaddr) { | |
513 | *devfnp = -1; | |
c469e1dd | 514 | return pci_find_bus(pci_find_root_bus(0), 0); |
5607c388 MA |
515 | } |
516 | ||
43c945f1 | 517 | if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
5607c388 MA |
518 | return NULL; |
519 | } | |
520 | ||
521 | *devfnp = slot << 3; | |
e075e788 | 522 | return pci_find_bus(pci_find_root_bus(dom), bus); |
5607c388 MA |
523 | } |
524 | ||
bd4b65ee MT |
525 | static void pci_init_cmask(PCIDevice *dev) |
526 | { | |
527 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); | |
528 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); | |
529 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; | |
530 | dev->cmask[PCI_REVISION_ID] = 0xff; | |
531 | dev->cmask[PCI_CLASS_PROG] = 0xff; | |
532 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); | |
533 | dev->cmask[PCI_HEADER_TYPE] = 0xff; | |
534 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; | |
535 | } | |
536 | ||
b7ee1603 MT |
537 | static void pci_init_wmask(PCIDevice *dev) |
538 | { | |
a9f49946 IY |
539 | int config_size = pci_config_size(dev); |
540 | ||
b7ee1603 MT |
541 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
542 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; | |
67a51b48 | 543 | pci_set_word(dev->wmask + PCI_COMMAND, |
a7b15a5c MT |
544 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
545 | PCI_COMMAND_INTX_DISABLE); | |
3e21ffc9 IY |
546 | |
547 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, | |
548 | config_size - PCI_CONFIG_HEADER_SIZE); | |
b7ee1603 MT |
549 | } |
550 | ||
fb231628 IY |
551 | static void pci_init_wmask_bridge(PCIDevice *d) |
552 | { | |
553 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and | |
554 | PCI_SEC_LETENCY_TIMER */ | |
555 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); | |
556 | ||
557 | /* base and limit */ | |
558 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; | |
559 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; | |
560 | pci_set_word(d->wmask + PCI_MEMORY_BASE, | |
561 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
562 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, | |
563 | PCI_MEMORY_RANGE_MASK & 0xffff); | |
564 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, | |
565 | PCI_PREF_RANGE_MASK & 0xffff); | |
566 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, | |
567 | PCI_PREF_RANGE_MASK & 0xffff); | |
568 | ||
569 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ | |
570 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); | |
571 | ||
572 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); | |
573 | } | |
574 | ||
6eab3de1 IY |
575 | static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
576 | { | |
577 | uint8_t slot = PCI_SLOT(dev->devfn); | |
578 | uint8_t func; | |
579 | ||
580 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
581 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
582 | } | |
583 | ||
584 | /* | |
585 | * multifuction bit is interpreted in two ways as follows. | |
586 | * - all functions must set the bit to 1. | |
587 | * Example: Intel X53 | |
588 | * - function 0 must set the bit, but the rest function (> 0) | |
589 | * is allowed to leave the bit to 0. | |
590 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, | |
591 | * | |
592 | * So OS (at least Linux) checks the bit of only function 0, | |
593 | * and doesn't see the bit of function > 0. | |
594 | * | |
595 | * The below check allows both interpretation. | |
596 | */ | |
597 | if (PCI_FUNC(dev->devfn)) { | |
598 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; | |
599 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { | |
600 | /* function 0 should set multifunction bit */ | |
601 | error_report("PCI: single function device can't be populated " | |
602 | "in function %x.%x", slot, PCI_FUNC(dev->devfn)); | |
603 | return -1; | |
604 | } | |
605 | return 0; | |
606 | } | |
607 | ||
608 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
609 | return 0; | |
610 | } | |
611 | /* function 0 indicates single function, so function > 0 must be NULL */ | |
612 | for (func = 1; func < PCI_FUNC_MAX; ++func) { | |
613 | if (bus->devices[PCI_DEVFN(slot, func)]) { | |
614 | error_report("PCI: %x.0 indicates single function, " | |
615 | "but %x.%x is already populated.", | |
616 | slot, slot, func); | |
617 | return -1; | |
618 | } | |
619 | } | |
620 | return 0; | |
621 | } | |
622 | ||
a9f49946 IY |
623 | static void pci_config_alloc(PCIDevice *pci_dev) |
624 | { | |
625 | int config_size = pci_config_size(pci_dev); | |
626 | ||
627 | pci_dev->config = qemu_mallocz(config_size); | |
628 | pci_dev->cmask = qemu_mallocz(config_size); | |
629 | pci_dev->wmask = qemu_mallocz(config_size); | |
92ba5f51 | 630 | pci_dev->w1cmask = qemu_mallocz(config_size); |
a9f49946 IY |
631 | pci_dev->used = qemu_mallocz(config_size); |
632 | } | |
633 | ||
634 | static void pci_config_free(PCIDevice *pci_dev) | |
635 | { | |
636 | qemu_free(pci_dev->config); | |
637 | qemu_free(pci_dev->cmask); | |
638 | qemu_free(pci_dev->wmask); | |
92ba5f51 | 639 | qemu_free(pci_dev->w1cmask); |
a9f49946 IY |
640 | qemu_free(pci_dev->used); |
641 | } | |
642 | ||
69b91039 | 643 | /* -1 for devfn means auto assign */ |
6b1b92d3 PB |
644 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, |
645 | const char *name, int devfn, | |
646 | PCIConfigReadFunc *config_read, | |
fb231628 | 647 | PCIConfigWriteFunc *config_write, |
e327e323 | 648 | bool is_bridge) |
69b91039 | 649 | { |
69b91039 | 650 | if (devfn < 0) { |
b47b0706 | 651 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
6fa84913 | 652 | devfn += PCI_FUNC_MAX) { |
30468f78 | 653 | if (!bus->devices[devfn]) |
69b91039 FB |
654 | goto found; |
655 | } | |
3709c1b7 | 656 | error_report("PCI: no slot/function available for %s, all in use", name); |
09e3acc6 | 657 | return NULL; |
69b91039 | 658 | found: ; |
07b7d053 | 659 | } else if (bus->devices[devfn]) { |
3709c1b7 DB |
660 | error_report("PCI: slot %d function %d not available for %s, in use by %s", |
661 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); | |
09e3acc6 | 662 | return NULL; |
69b91039 | 663 | } |
30468f78 | 664 | pci_dev->bus = bus; |
69b91039 FB |
665 | pci_dev->devfn = devfn; |
666 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); | |
d036bb21 | 667 | pci_dev->irq_state = 0; |
a9f49946 | 668 | pci_config_alloc(pci_dev); |
fb231628 | 669 | |
e327e323 | 670 | if (!is_bridge) { |
fb231628 IY |
671 | pci_set_default_subsystem_id(pci_dev); |
672 | } | |
bd4b65ee | 673 | pci_init_cmask(pci_dev); |
b7ee1603 | 674 | pci_init_wmask(pci_dev); |
e327e323 | 675 | if (is_bridge) { |
fb231628 IY |
676 | pci_init_wmask_bridge(pci_dev); |
677 | } | |
6eab3de1 IY |
678 | if (pci_init_multifunction(bus, pci_dev)) { |
679 | pci_config_free(pci_dev); | |
680 | return NULL; | |
681 | } | |
0ac32c83 FB |
682 | |
683 | if (!config_read) | |
684 | config_read = pci_default_read_config; | |
685 | if (!config_write) | |
686 | config_write = pci_default_write_config; | |
69b91039 FB |
687 | pci_dev->config_read = config_read; |
688 | pci_dev->config_write = config_write; | |
30468f78 | 689 | bus->devices[devfn] = pci_dev; |
e369cad7 | 690 | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
f16c4abf | 691 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
69b91039 FB |
692 | return pci_dev; |
693 | } | |
694 | ||
925fe64a AW |
695 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
696 | { | |
697 | qemu_free_irqs(pci_dev->irq); | |
698 | pci_dev->bus->devices[pci_dev->devfn] = NULL; | |
699 | pci_config_free(pci_dev); | |
700 | } | |
701 | ||
6b1b92d3 PB |
702 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
703 | int instance_size, int devfn, | |
704 | PCIConfigReadFunc *config_read, | |
705 | PCIConfigWriteFunc *config_write) | |
706 | { | |
707 | PCIDevice *pci_dev; | |
708 | ||
709 | pci_dev = qemu_mallocz(instance_size); | |
710 | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, | |
fb231628 IY |
711 | config_read, config_write, |
712 | PCI_HEADER_TYPE_NORMAL); | |
09e3acc6 GH |
713 | if (pci_dev == NULL) { |
714 | hw_error("PCI: can't register device\n"); | |
715 | } | |
6b1b92d3 PB |
716 | return pci_dev; |
717 | } | |
2e01c8cf BS |
718 | |
719 | static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus, | |
720 | target_phys_addr_t addr) | |
5851e08c | 721 | { |
2e01c8cf | 722 | return addr + bus->mem_base; |
5851e08c AL |
723 | } |
724 | ||
725 | static void pci_unregister_io_regions(PCIDevice *pci_dev) | |
726 | { | |
727 | PCIIORegion *r; | |
728 | int i; | |
729 | ||
730 | for(i = 0; i < PCI_NUM_REGIONS; i++) { | |
731 | r = &pci_dev->io_regions[i]; | |
182f9c8a | 732 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
5851e08c | 733 | continue; |
0392a017 | 734 | if (r->type == PCI_BASE_ADDRESS_SPACE_IO) { |
a0c7a97e | 735 | isa_unassign_ioport(r->addr, r->filtered_size); |
5851e08c | 736 | } else { |
2e01c8cf BS |
737 | cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, |
738 | r->addr), | |
739 | r->filtered_size, | |
740 | IO_MEM_UNASSIGNED); | |
5851e08c AL |
741 | } |
742 | } | |
743 | } | |
744 | ||
a36a344d | 745 | static int pci_unregister_device(DeviceState *dev) |
5851e08c | 746 | { |
a36a344d | 747 | PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
e3936fa5 | 748 | PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
5851e08c AL |
749 | int ret = 0; |
750 | ||
e3936fa5 GH |
751 | if (info->exit) |
752 | ret = info->exit(pci_dev); | |
5851e08c AL |
753 | if (ret) |
754 | return ret; | |
755 | ||
756 | pci_unregister_io_regions(pci_dev); | |
230741dc | 757 | pci_del_option_rom(pci_dev); |
925fe64a | 758 | do_pci_unregister_device(pci_dev); |
5851e08c AL |
759 | return 0; |
760 | } | |
761 | ||
28c2c264 | 762 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
0bb750ef | 763 | pcibus_t size, uint8_t type, |
69b91039 FB |
764 | PCIMapIORegionFunc *map_func) |
765 | { | |
766 | PCIIORegion *r; | |
d7ce493a | 767 | uint32_t addr; |
5a9ff381 | 768 | uint64_t wmask; |
69b91039 | 769 | |
2bbb9c2f IY |
770 | assert(region_num >= 0); |
771 | assert(region_num < PCI_NUM_REGIONS); | |
a4c20c6a AL |
772 | if (size & (size-1)) { |
773 | fprintf(stderr, "ERROR: PCI region size must be pow2 " | |
89e8b13c | 774 | "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
a4c20c6a AL |
775 | exit(1); |
776 | } | |
777 | ||
69b91039 | 778 | r = &pci_dev->io_regions[region_num]; |
182f9c8a | 779 | r->addr = PCI_BAR_UNMAPPED; |
69b91039 | 780 | r->size = size; |
a0c7a97e | 781 | r->filtered_size = size; |
69b91039 FB |
782 | r->type = type; |
783 | r->map_func = map_func; | |
b7ee1603 MT |
784 | |
785 | wmask = ~(size - 1); | |
b3b11697 | 786 | addr = pci_bar(pci_dev, region_num); |
d7ce493a | 787 | if (region_num == PCI_ROM_SLOT) { |
b7ee1603 | 788 | /* ROM enable bit is writeable */ |
5330de09 | 789 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
d7ce493a | 790 | } |
b0ff8eb2 | 791 | pci_set_long(pci_dev->config + addr, type); |
14421258 IY |
792 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
793 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
794 | pci_set_quad(pci_dev->wmask + addr, wmask); | |
795 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); | |
796 | } else { | |
797 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); | |
798 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); | |
799 | } | |
69b91039 FB |
800 | } |
801 | ||
a0c7a97e IY |
802 | static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, |
803 | uint8_t type) | |
804 | { | |
805 | pcibus_t base = *addr; | |
806 | pcibus_t limit = *addr + *size - 1; | |
807 | PCIDevice *br; | |
808 | ||
809 | for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) { | |
810 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
811 | ||
812 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
813 | if (!(cmd & PCI_COMMAND_IO)) { | |
814 | goto no_map; | |
815 | } | |
816 | } else { | |
817 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
818 | goto no_map; | |
819 | } | |
820 | } | |
821 | ||
822 | base = MAX(base, pci_bridge_get_base(br, type)); | |
823 | limit = MIN(limit, pci_bridge_get_limit(br, type)); | |
824 | } | |
825 | ||
826 | if (base > limit) { | |
88a95564 | 827 | goto no_map; |
a0c7a97e | 828 | } |
88a95564 MT |
829 | *addr = base; |
830 | *size = limit - base + 1; | |
831 | return; | |
832 | no_map: | |
833 | *addr = PCI_BAR_UNMAPPED; | |
834 | *size = 0; | |
a0c7a97e IY |
835 | } |
836 | ||
876a350d MT |
837 | static pcibus_t pci_bar_address(PCIDevice *d, |
838 | int reg, uint8_t type, pcibus_t size) | |
839 | { | |
840 | pcibus_t new_addr, last_addr; | |
841 | int bar = pci_bar(d, reg); | |
842 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); | |
843 | ||
844 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { | |
845 | if (!(cmd & PCI_COMMAND_IO)) { | |
846 | return PCI_BAR_UNMAPPED; | |
847 | } | |
848 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); | |
849 | last_addr = new_addr + size - 1; | |
850 | /* NOTE: we have only 64K ioports on PC */ | |
851 | if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { | |
852 | return PCI_BAR_UNMAPPED; | |
853 | } | |
854 | return new_addr; | |
855 | } | |
856 | ||
857 | if (!(cmd & PCI_COMMAND_MEMORY)) { | |
858 | return PCI_BAR_UNMAPPED; | |
859 | } | |
860 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { | |
861 | new_addr = pci_get_quad(d->config + bar); | |
862 | } else { | |
863 | new_addr = pci_get_long(d->config + bar); | |
864 | } | |
865 | /* the ROM slot has a specific enable bit */ | |
866 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { | |
867 | return PCI_BAR_UNMAPPED; | |
868 | } | |
869 | new_addr &= ~(size - 1); | |
870 | last_addr = new_addr + size - 1; | |
871 | /* NOTE: we do not support wrapping */ | |
872 | /* XXX: as we cannot support really dynamic | |
873 | mappings, we handle specific values as invalid | |
874 | mappings. */ | |
875 | if (last_addr <= new_addr || new_addr == 0 || | |
876 | last_addr == PCI_BAR_UNMAPPED) { | |
877 | return PCI_BAR_UNMAPPED; | |
878 | } | |
879 | ||
880 | /* Now pcibus_t is 64bit. | |
881 | * Check if 32 bit BAR wraps around explicitly. | |
882 | * Without this, PC ide doesn't work well. | |
883 | * TODO: remove this work around. | |
884 | */ | |
885 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { | |
886 | return PCI_BAR_UNMAPPED; | |
887 | } | |
888 | ||
889 | /* | |
890 | * OS is allowed to set BAR beyond its addressable | |
891 | * bits. For example, 32 bit OS can set 64bit bar | |
892 | * to >4G. Check it. TODO: we might need to support | |
893 | * it in the future for e.g. PAE. | |
894 | */ | |
895 | if (last_addr >= TARGET_PHYS_ADDR_MAX) { | |
896 | return PCI_BAR_UNMAPPED; | |
897 | } | |
898 | ||
899 | return new_addr; | |
900 | } | |
901 | ||
0ac32c83 FB |
902 | static void pci_update_mappings(PCIDevice *d) |
903 | { | |
904 | PCIIORegion *r; | |
876a350d | 905 | int i; |
c71b5b4a | 906 | pcibus_t new_addr, filtered_size; |
3b46e624 | 907 | |
8a8696a3 | 908 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
0ac32c83 | 909 | r = &d->io_regions[i]; |
a9688570 IY |
910 | |
911 | /* this region isn't registered */ | |
ec503442 | 912 | if (!r->size) |
a9688570 IY |
913 | continue; |
914 | ||
876a350d | 915 | new_addr = pci_bar_address(d, i, r->type, r->size); |
a9688570 | 916 | |
a0c7a97e IY |
917 | /* bridge filtering */ |
918 | filtered_size = r->size; | |
919 | if (new_addr != PCI_BAR_UNMAPPED) { | |
920 | pci_bridge_filter(d, &new_addr, &filtered_size, r->type); | |
921 | } | |
922 | ||
a9688570 | 923 | /* This bar isn't changed */ |
a0c7a97e | 924 | if (new_addr == r->addr && filtered_size == r->filtered_size) |
a9688570 IY |
925 | continue; |
926 | ||
927 | /* now do the real mapping */ | |
928 | if (r->addr != PCI_BAR_UNMAPPED) { | |
929 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
930 | int class; | |
931 | /* NOTE: specific hack for IDE in PC case: | |
932 | only one byte must be mapped. */ | |
933 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); | |
934 | if (class == 0x0101 && r->size == 4) { | |
935 | isa_unassign_ioport(r->addr + 2, 1); | |
936 | } else { | |
a0c7a97e | 937 | isa_unassign_ioport(r->addr, r->filtered_size); |
0ac32c83 | 938 | } |
a9688570 | 939 | } else { |
c71b5b4a | 940 | cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), |
a0c7a97e | 941 | r->filtered_size, |
a9688570 | 942 | IO_MEM_UNASSIGNED); |
a0c7a97e | 943 | qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
0ac32c83 FB |
944 | } |
945 | } | |
a9688570 | 946 | r->addr = new_addr; |
a0c7a97e | 947 | r->filtered_size = filtered_size; |
a9688570 | 948 | if (r->addr != PCI_BAR_UNMAPPED) { |
a0c7a97e IY |
949 | /* |
950 | * TODO: currently almost all the map funcions assumes | |
951 | * filtered_size == size and addr & ~(size - 1) == addr. | |
952 | * However with bridge filtering, they aren't always true. | |
953 | * Teach them such cases, such that filtered_size < size and | |
954 | * addr & (size - 1) != 0. | |
955 | */ | |
cf616802 BS |
956 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
957 | r->map_func(d, i, r->addr, r->filtered_size, r->type); | |
958 | } else { | |
959 | r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr), | |
960 | r->filtered_size, r->type); | |
961 | } | |
a9688570 | 962 | } |
0ac32c83 FB |
963 | } |
964 | } | |
965 | ||
a7b15a5c MT |
966 | static inline int pci_irq_disabled(PCIDevice *d) |
967 | { | |
968 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; | |
969 | } | |
970 | ||
971 | /* Called after interrupt disabled field update in config space, | |
972 | * assert/deassert interrupts if necessary. | |
973 | * Gets original interrupt disable bit value (before update). */ | |
974 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) | |
975 | { | |
976 | int i, disabled = pci_irq_disabled(d); | |
977 | if (disabled == was_irq_disabled) | |
978 | return; | |
979 | for (i = 0; i < PCI_NUM_PINS; ++i) { | |
980 | int state = pci_irq_state(d, i); | |
981 | pci_change_irq_level(d, i, disabled ? -state : state); | |
982 | } | |
983 | } | |
984 | ||
5fafdf24 | 985 | uint32_t pci_default_read_config(PCIDevice *d, |
0ac32c83 | 986 | uint32_t address, int len) |
69b91039 | 987 | { |
5029fe12 IY |
988 | uint32_t val = 0; |
989 | assert(len == 1 || len == 2 || len == 4); | |
a9f49946 | 990 | len = MIN(len, pci_config_size(d) - address); |
5029fe12 IY |
991 | memcpy(&val, d->config + address, len); |
992 | return le32_to_cpu(val); | |
0ac32c83 FB |
993 | } |
994 | ||
b7ee1603 | 995 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
0ac32c83 | 996 | { |
a7b15a5c | 997 | int i, was_irq_disabled = pci_irq_disabled(d); |
a9f49946 | 998 | uint32_t config_size = pci_config_size(d); |
0ac32c83 | 999 | |
91011d4f SW |
1000 | for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
1001 | uint8_t wmask = d->wmask[addr + i]; | |
92ba5f51 IY |
1002 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1003 | assert(!(wmask & w1cmask)); | |
91011d4f | 1004 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
92ba5f51 | 1005 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
0ac32c83 | 1006 | } |
260c0cd3 | 1007 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
edb00035 IY |
1008 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1009 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || | |
260c0cd3 | 1010 | range_covers_byte(addr, l, PCI_COMMAND)) |
0ac32c83 | 1011 | pci_update_mappings(d); |
a7b15a5c MT |
1012 | |
1013 | if (range_covers_byte(addr, l, PCI_COMMAND)) | |
1014 | pci_update_irq_disabled(d, was_irq_disabled); | |
69b91039 FB |
1015 | } |
1016 | ||
502a5395 PB |
1017 | /***********************************************************/ |
1018 | /* generic PCI irq support */ | |
30468f78 | 1019 | |
502a5395 | 1020 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
d537cf6c | 1021 | static void pci_set_irq(void *opaque, int irq_num, int level) |
69b91039 | 1022 | { |
a60380a5 | 1023 | PCIDevice *pci_dev = opaque; |
80b3ada7 | 1024 | int change; |
3b46e624 | 1025 | |
d036bb21 | 1026 | change = level - pci_irq_state(pci_dev, irq_num); |
80b3ada7 PB |
1027 | if (!change) |
1028 | return; | |
d2b59317 | 1029 | |
d036bb21 | 1030 | pci_set_irq_state(pci_dev, irq_num, level); |
f9bf77dd | 1031 | pci_update_irq_status(pci_dev); |
a7b15a5c MT |
1032 | if (pci_irq_disabled(pci_dev)) |
1033 | return; | |
d036bb21 | 1034 | pci_change_irq_level(pci_dev, irq_num, change); |
69b91039 FB |
1035 | } |
1036 | ||
502a5395 PB |
1037 | /***********************************************************/ |
1038 | /* monitor info on PCI */ | |
0ac32c83 | 1039 | |
6650ee6d PB |
1040 | typedef struct { |
1041 | uint16_t class; | |
1042 | const char *desc; | |
1043 | } pci_class_desc; | |
1044 | ||
09bc878a | 1045 | static const pci_class_desc pci_class_descriptions[] = |
6650ee6d | 1046 | { |
4ca9c76f | 1047 | { 0x0100, "SCSI controller"}, |
6650ee6d | 1048 | { 0x0101, "IDE controller"}, |
dcb5b19a TS |
1049 | { 0x0102, "Floppy controller"}, |
1050 | { 0x0103, "IPI controller"}, | |
1051 | { 0x0104, "RAID controller"}, | |
1052 | { 0x0106, "SATA controller"}, | |
1053 | { 0x0107, "SAS controller"}, | |
1054 | { 0x0180, "Storage controller"}, | |
6650ee6d | 1055 | { 0x0200, "Ethernet controller"}, |
dcb5b19a TS |
1056 | { 0x0201, "Token Ring controller"}, |
1057 | { 0x0202, "FDDI controller"}, | |
1058 | { 0x0203, "ATM controller"}, | |
1059 | { 0x0280, "Network controller"}, | |
6650ee6d | 1060 | { 0x0300, "VGA controller"}, |
dcb5b19a TS |
1061 | { 0x0301, "XGA controller"}, |
1062 | { 0x0302, "3D controller"}, | |
1063 | { 0x0380, "Display controller"}, | |
1064 | { 0x0400, "Video controller"}, | |
1065 | { 0x0401, "Audio controller"}, | |
1066 | { 0x0402, "Phone"}, | |
1067 | { 0x0480, "Multimedia controller"}, | |
1068 | { 0x0500, "RAM controller"}, | |
1069 | { 0x0501, "Flash controller"}, | |
1070 | { 0x0580, "Memory controller"}, | |
6650ee6d PB |
1071 | { 0x0600, "Host bridge"}, |
1072 | { 0x0601, "ISA bridge"}, | |
dcb5b19a TS |
1073 | { 0x0602, "EISA bridge"}, |
1074 | { 0x0603, "MC bridge"}, | |
6650ee6d | 1075 | { 0x0604, "PCI bridge"}, |
dcb5b19a TS |
1076 | { 0x0605, "PCMCIA bridge"}, |
1077 | { 0x0606, "NUBUS bridge"}, | |
1078 | { 0x0607, "CARDBUS bridge"}, | |
1079 | { 0x0608, "RACEWAY bridge"}, | |
1080 | { 0x0680, "Bridge"}, | |
6650ee6d PB |
1081 | { 0x0c03, "USB controller"}, |
1082 | { 0, NULL} | |
1083 | }; | |
1084 | ||
163c8a59 LC |
1085 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1086 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
30468f78 | 1087 | { |
163c8a59 LC |
1088 | PCIDevice *d; |
1089 | int devfn; | |
30468f78 | 1090 | |
163c8a59 LC |
1091 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1092 | d = bus->devices[devfn]; | |
1093 | if (d) { | |
1094 | fn(bus, d); | |
1095 | } | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | void pci_for_each_device(PCIBus *bus, int bus_num, | |
1100 | void (*fn)(PCIBus *b, PCIDevice *d)) | |
1101 | { | |
1102 | bus = pci_find_bus(bus, bus_num); | |
1103 | ||
1104 | if (bus) { | |
1105 | pci_for_each_device_under_bus(bus, fn); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static void pci_device_print(Monitor *mon, QDict *device) | |
1110 | { | |
1111 | QDict *qdict; | |
1112 | QListEntry *entry; | |
1113 | uint64_t addr, size; | |
1114 | ||
1115 | monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus")); | |
1116 | monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n", | |
1117 | qdict_get_int(device, "slot"), | |
1118 | qdict_get_int(device, "function")); | |
376253ec | 1119 | monitor_printf(mon, " "); |
163c8a59 LC |
1120 | |
1121 | qdict = qdict_get_qdict(device, "class_info"); | |
1122 | if (qdict_haskey(qdict, "desc")) { | |
1123 | monitor_printf(mon, "%s", qdict_get_str(qdict, "desc")); | |
6650ee6d | 1124 | } else { |
163c8a59 | 1125 | monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class")); |
72cc6cfe | 1126 | } |
30468f78 | 1127 | |
163c8a59 LC |
1128 | qdict = qdict_get_qdict(device, "id"); |
1129 | monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", | |
1130 | qdict_get_int(qdict, "device"), | |
1131 | qdict_get_int(qdict, "vendor")); | |
1132 | ||
1133 | if (qdict_haskey(device, "irq")) { | |
1134 | monitor_printf(mon, " IRQ %" PRId64 ".\n", | |
1135 | qdict_get_int(device, "irq")); | |
30468f78 | 1136 | } |
b4dccd8d | 1137 | |
163c8a59 LC |
1138 | if (qdict_haskey(device, "pci_bridge")) { |
1139 | QDict *info; | |
1140 | ||
1141 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1142 | ||
1143 | info = qdict_get_qdict(qdict, "bus"); | |
1144 | monitor_printf(mon, " BUS %" PRId64 ".\n", | |
1145 | qdict_get_int(info, "number")); | |
1146 | monitor_printf(mon, " secondary bus %" PRId64 ".\n", | |
1147 | qdict_get_int(info, "secondary")); | |
1148 | monitor_printf(mon, " subordinate bus %" PRId64 ".\n", | |
1149 | qdict_get_int(info, "subordinate")); | |
b4dccd8d | 1150 | |
163c8a59 | 1151 | info = qdict_get_qdict(qdict, "io_range"); |
b4dccd8d | 1152 | monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
163c8a59 LC |
1153 | qdict_get_int(info, "base"), |
1154 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1155 | |
163c8a59 | 1156 | info = qdict_get_qdict(qdict, "memory_range"); |
b4dccd8d IY |
1157 | monitor_printf(mon, |
1158 | " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", | |
163c8a59 LC |
1159 | qdict_get_int(info, "base"), |
1160 | qdict_get_int(info, "limit")); | |
b4dccd8d | 1161 | |
163c8a59 | 1162 | info = qdict_get_qdict(qdict, "prefetchable_range"); |
b4dccd8d | 1163 | monitor_printf(mon, " prefetchable memory range " |
163c8a59 LC |
1164 | "[0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1165 | qdict_get_int(info, "base"), | |
1166 | qdict_get_int(info, "limit")); | |
80b3ada7 | 1167 | } |
14421258 | 1168 | |
163c8a59 LC |
1169 | QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) { |
1170 | qdict = qobject_to_qdict(qlist_entry_obj(entry)); | |
1171 | monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar")); | |
1172 | ||
1173 | addr = qdict_get_int(qdict, "address"); | |
1174 | size = qdict_get_int(qdict, "size"); | |
1175 | ||
1176 | if (!strcmp(qdict_get_str(qdict, "type"), "io")) { | |
1177 | monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS | |
1178 | " [0x%04"FMT_PCIBUS"].\n", | |
1179 | addr, addr + size - 1); | |
1180 | } else { | |
1181 | monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS | |
89e8b13c | 1182 | " [0x%08"FMT_PCIBUS"].\n", |
163c8a59 LC |
1183 | qdict_get_bool(qdict, "mem_type_64") ? 64 : 32, |
1184 | qdict_get_bool(qdict, "prefetch") ? | |
1185 | " prefetchable" : "", addr, addr + size - 1); | |
502a5395 | 1186 | } |
77d4bc34 | 1187 | } |
163c8a59 LC |
1188 | |
1189 | monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id")); | |
1190 | ||
d5e4acf7 LC |
1191 | if (qdict_haskey(device, "pci_bridge")) { |
1192 | qdict = qdict_get_qdict(device, "pci_bridge"); | |
1193 | if (qdict_haskey(qdict, "devices")) { | |
1194 | QListEntry *dev; | |
1195 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1196 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1197 | } | |
1198 | } | |
1199 | } | |
163c8a59 LC |
1200 | } |
1201 | ||
1202 | void do_pci_info_print(Monitor *mon, const QObject *data) | |
1203 | { | |
1204 | QListEntry *bus, *dev; | |
1205 | ||
1206 | QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) { | |
1207 | QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus)); | |
1208 | QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) { | |
1209 | pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); | |
1210 | } | |
80b3ada7 | 1211 | } |
384d8876 FB |
1212 | } |
1213 | ||
163c8a59 LC |
1214 | static QObject *pci_get_dev_class(const PCIDevice *dev) |
1215 | { | |
1216 | int class; | |
1217 | const pci_class_desc *desc; | |
1218 | ||
1219 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); | |
1220 | desc = pci_class_descriptions; | |
1221 | while (desc->desc && class != desc->class) | |
1222 | desc++; | |
1223 | ||
1224 | if (desc->desc) { | |
1225 | return qobject_from_jsonf("{ 'desc': %s, 'class': %d }", | |
1226 | desc->desc, class); | |
1227 | } else { | |
1228 | return qobject_from_jsonf("{ 'class': %d }", class); | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | static QObject *pci_get_dev_id(const PCIDevice *dev) | |
1233 | { | |
1234 | return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }", | |
1235 | pci_get_word(dev->config + PCI_VENDOR_ID), | |
1236 | pci_get_word(dev->config + PCI_DEVICE_ID)); | |
1237 | } | |
1238 | ||
1239 | static QObject *pci_get_regions_list(const PCIDevice *dev) | |
1240 | { | |
1241 | int i; | |
1242 | QList *regions_list; | |
1243 | ||
1244 | regions_list = qlist_new(); | |
1245 | ||
1246 | for (i = 0; i < PCI_NUM_REGIONS; i++) { | |
1247 | QObject *obj; | |
1248 | const PCIIORegion *r = &dev->io_regions[i]; | |
1249 | ||
1250 | if (!r->size) { | |
1251 | continue; | |
1252 | } | |
1253 | ||
1254 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { | |
1255 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', " | |
1256 | "'address': %" PRId64 ", " | |
1257 | "'size': %" PRId64 " }", | |
1258 | i, r->addr, r->size); | |
1259 | } else { | |
1260 | int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
1261 | ||
1262 | obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', " | |
1263 | "'mem_type_64': %i, 'prefetch': %i, " | |
1264 | "'address': %" PRId64 ", " | |
1265 | "'size': %" PRId64 " }", | |
1266 | i, mem_type_64, | |
1267 | r->type & PCI_BASE_ADDRESS_MEM_PREFETCH, | |
1268 | r->addr, r->size); | |
1269 | } | |
1270 | ||
1271 | qlist_append_obj(regions_list, obj); | |
1272 | } | |
1273 | ||
1274 | return QOBJECT(regions_list); | |
1275 | } | |
1276 | ||
d5e4acf7 LC |
1277 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num); |
1278 | ||
1279 | static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num) | |
163c8a59 | 1280 | { |
b5937f29 | 1281 | uint8_t type; |
163c8a59 LC |
1282 | QObject *obj; |
1283 | ||
1284 | obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p," | |
1285 | " 'qdev_id': %s }", | |
1286 | bus_num, | |
1287 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
1288 | pci_get_dev_class(dev), pci_get_dev_id(dev), | |
1289 | pci_get_regions_list(dev), | |
1290 | dev->qdev.id ? dev->qdev.id : ""); | |
1291 | ||
1292 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { | |
1293 | QDict *qdict = qobject_to_qdict(obj); | |
1294 | qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE])); | |
1295 | } | |
1296 | ||
b5937f29 IY |
1297 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1298 | if (type == PCI_HEADER_TYPE_BRIDGE) { | |
163c8a59 LC |
1299 | QDict *qdict; |
1300 | QObject *pci_bridge; | |
1301 | ||
1302 | pci_bridge = qobject_from_jsonf("{ 'bus': " | |
1303 | "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, " | |
1304 | "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1305 | "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " | |
1306 | "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }", | |
c021f8e6 | 1307 | dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS], |
163c8a59 LC |
1308 | dev->config[PCI_SUBORDINATE_BUS], |
1309 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1310 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO), | |
1311 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1312 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), | |
1313 | pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1314 | PCI_BASE_ADDRESS_MEM_PREFETCH), | |
1315 | pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1316 | PCI_BASE_ADDRESS_MEM_PREFETCH)); | |
1317 | ||
c021f8e6 BS |
1318 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1319 | PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); | |
d5e4acf7 | 1320 | |
c021f8e6 BS |
1321 | if (child_bus) { |
1322 | qdict = qobject_to_qdict(pci_bridge); | |
1323 | qdict_put_obj(qdict, "devices", | |
1324 | pci_get_devices_list(child_bus, | |
1325 | dev->config[PCI_SECONDARY_BUS])); | |
1326 | } | |
1327 | } | |
163c8a59 LC |
1328 | qdict = qobject_to_qdict(obj); |
1329 | qdict_put_obj(qdict, "pci_bridge", pci_bridge); | |
1330 | } | |
1331 | ||
1332 | return obj; | |
1333 | } | |
1334 | ||
1335 | static QObject *pci_get_devices_list(PCIBus *bus, int bus_num) | |
384d8876 | 1336 | { |
502a5395 | 1337 | int devfn; |
163c8a59 LC |
1338 | PCIDevice *dev; |
1339 | QList *dev_list; | |
3b46e624 | 1340 | |
163c8a59 LC |
1341 | dev_list = qlist_new(); |
1342 | ||
1343 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { | |
1344 | dev = bus->devices[devfn]; | |
1345 | if (dev) { | |
d5e4acf7 | 1346 | qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num)); |
163c8a59 | 1347 | } |
1074df4f | 1348 | } |
163c8a59 LC |
1349 | |
1350 | return QOBJECT(dev_list); | |
1074df4f IY |
1351 | } |
1352 | ||
163c8a59 | 1353 | static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num) |
1074df4f | 1354 | { |
e822a52a | 1355 | bus = pci_find_bus(bus, bus_num); |
502a5395 | 1356 | if (bus) { |
163c8a59 LC |
1357 | return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }", |
1358 | bus_num, pci_get_devices_list(bus, bus_num)); | |
f2aa58c6 | 1359 | } |
163c8a59 LC |
1360 | |
1361 | return NULL; | |
f2aa58c6 FB |
1362 | } |
1363 | ||
163c8a59 | 1364 | void do_pci_info(Monitor *mon, QObject **ret_data) |
f2aa58c6 | 1365 | { |
163c8a59 | 1366 | QList *bus_list; |
e822a52a | 1367 | struct PCIHostBus *host; |
163c8a59 LC |
1368 | |
1369 | bus_list = qlist_new(); | |
1370 | ||
e822a52a | 1371 | QLIST_FOREACH(host, &host_buses, next) { |
163c8a59 LC |
1372 | QObject *obj = pci_get_bus_dict(host->bus, 0); |
1373 | if (obj) { | |
1374 | qlist_append_obj(bus_list, obj); | |
1375 | } | |
e822a52a | 1376 | } |
163c8a59 LC |
1377 | |
1378 | *ret_data = QOBJECT(bus_list); | |
77d4bc34 | 1379 | } |
a41b2ff2 | 1380 | |
cb457d76 AL |
1381 | static const char * const pci_nic_models[] = { |
1382 | "ne2k_pci", | |
1383 | "i82551", | |
1384 | "i82557b", | |
1385 | "i82559er", | |
1386 | "rtl8139", | |
1387 | "e1000", | |
1388 | "pcnet", | |
1389 | "virtio", | |
1390 | NULL | |
1391 | }; | |
1392 | ||
9d07d757 PB |
1393 | static const char * const pci_nic_names[] = { |
1394 | "ne2k_pci", | |
1395 | "i82551", | |
1396 | "i82557b", | |
1397 | "i82559er", | |
1398 | "rtl8139", | |
1399 | "e1000", | |
1400 | "pcnet", | |
53c25cea | 1401 | "virtio-net-pci", |
cb457d76 AL |
1402 | NULL |
1403 | }; | |
1404 | ||
a41b2ff2 | 1405 | /* Initialize a PCI NIC. */ |
33e66b86 | 1406 | /* FIXME callers should check for failure, but don't */ |
5607c388 MA |
1407 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1408 | const char *default_devaddr) | |
a41b2ff2 | 1409 | { |
5607c388 | 1410 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
07caea31 MA |
1411 | PCIBus *bus; |
1412 | int devfn; | |
5607c388 | 1413 | PCIDevice *pci_dev; |
9d07d757 | 1414 | DeviceState *dev; |
cb457d76 AL |
1415 | int i; |
1416 | ||
07caea31 MA |
1417 | i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1418 | if (i < 0) | |
1419 | return NULL; | |
1420 | ||
1421 | bus = pci_get_bus_devfn(&devfn, devaddr); | |
1422 | if (!bus) { | |
1ecda02b MA |
1423 | error_report("Invalid PCI device address %s for device %s", |
1424 | devaddr, pci_nic_names[i]); | |
07caea31 MA |
1425 | return NULL; |
1426 | } | |
1427 | ||
499cf102 | 1428 | pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
9ee05825 | 1429 | dev = &pci_dev->qdev; |
1cc33683 | 1430 | qdev_set_nic_properties(dev, nd); |
07caea31 MA |
1431 | if (qdev_init(dev) < 0) |
1432 | return NULL; | |
9ee05825 | 1433 | return pci_dev; |
a41b2ff2 PB |
1434 | } |
1435 | ||
07caea31 MA |
1436 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1437 | const char *default_devaddr) | |
1438 | { | |
1439 | PCIDevice *res; | |
1440 | ||
1441 | if (qemu_show_nic_models(nd->model, pci_nic_models)) | |
1442 | exit(0); | |
1443 | ||
1444 | res = pci_nic_init(nd, default_model, default_devaddr); | |
1445 | if (!res) | |
1446 | exit(1); | |
1447 | return res; | |
1448 | } | |
1449 | ||
a0c7a97e IY |
1450 | static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) |
1451 | { | |
1452 | pci_update_mappings(d); | |
1453 | } | |
1454 | ||
783753fd | 1455 | void pci_bridge_update_mappings(PCIBus *b) |
a0c7a97e IY |
1456 | { |
1457 | PCIBus *child; | |
1458 | ||
1459 | pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); | |
1460 | ||
1461 | QLIST_FOREACH(child, &b->child, sibling) { | |
1462 | pci_bridge_update_mappings(child); | |
1463 | } | |
1464 | } | |
1465 | ||
e822a52a | 1466 | PCIBus *pci_find_bus(PCIBus *bus, int bus_num) |
3ae80618 | 1467 | { |
470e6363 | 1468 | PCIBus *sec; |
3ae80618 | 1469 | |
470e6363 | 1470 | if (!bus) { |
e822a52a | 1471 | return NULL; |
470e6363 | 1472 | } |
3ae80618 | 1473 | |
e822a52a IY |
1474 | if (pci_bus_num(bus) == bus_num) { |
1475 | return bus; | |
1476 | } | |
1477 | ||
1478 | /* try child bus */ | |
470e6363 IY |
1479 | if (!bus->parent_dev /* host pci bridge */ || |
1480 | (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1481 | bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { | |
1482 | for (; bus; bus = sec) { | |
1483 | QLIST_FOREACH(sec, &bus->child, sibling) { | |
1484 | assert(sec->parent_dev); | |
1485 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { | |
1486 | return sec; | |
1487 | } | |
1488 | if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && | |
1489 | bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) { | |
1490 | break; | |
1491 | } | |
c021f8e6 | 1492 | } |
e822a52a IY |
1493 | } |
1494 | } | |
1495 | ||
1496 | return NULL; | |
3ae80618 AL |
1497 | } |
1498 | ||
e822a52a | 1499 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
3ae80618 | 1500 | { |
e822a52a | 1501 | bus = pci_find_bus(bus, bus_num); |
3ae80618 AL |
1502 | |
1503 | if (!bus) | |
1504 | return NULL; | |
1505 | ||
1506 | return bus->devices[PCI_DEVFN(slot, function)]; | |
1507 | } | |
1508 | ||
81a322d4 | 1509 | static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
6b1b92d3 PB |
1510 | { |
1511 | PCIDevice *pci_dev = (PCIDevice *)qdev; | |
02e2da45 | 1512 | PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
6b1b92d3 | 1513 | PCIBus *bus; |
ee995ffb | 1514 | int devfn, rc; |
6b1b92d3 | 1515 | |
a9f49946 IY |
1516 | /* initialize cap_present for pci_is_express() and pci_config_size() */ |
1517 | if (info->is_express) { | |
1518 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1519 | } | |
1520 | ||
02e2da45 | 1521 | bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
ee6847d1 | 1522 | devfn = pci_dev->devfn; |
16eaedf2 | 1523 | pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
fb231628 | 1524 | info->config_read, info->config_write, |
e327e323 | 1525 | info->is_bridge); |
09e3acc6 GH |
1526 | if (pci_dev == NULL) |
1527 | return -1; | |
ee995ffb | 1528 | rc = info->init(pci_dev); |
925fe64a AW |
1529 | if (rc != 0) { |
1530 | do_pci_unregister_device(pci_dev); | |
ee995ffb | 1531 | return rc; |
925fe64a | 1532 | } |
8c52c8f3 GH |
1533 | |
1534 | /* rom loading */ | |
1535 | if (pci_dev->romfile == NULL && info->romfile != NULL) | |
1536 | pci_dev->romfile = qemu_strdup(info->romfile); | |
1537 | pci_add_option_rom(pci_dev); | |
1538 | ||
5beb8ad5 IY |
1539 | if (bus->hotplug) { |
1540 | /* lower layer must check qdev->hotplugged */ | |
a213ff63 IY |
1541 | rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1); |
1542 | if (rc != 0) { | |
1543 | int r = pci_unregister_device(&pci_dev->qdev); | |
1544 | assert(!r); | |
1545 | return rc; | |
1546 | } | |
1547 | } | |
ee995ffb GH |
1548 | return 0; |
1549 | } | |
1550 | ||
1551 | static int pci_unplug_device(DeviceState *qdev) | |
1552 | { | |
1553 | PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); | |
1554 | ||
a213ff63 | 1555 | return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0); |
6b1b92d3 PB |
1556 | } |
1557 | ||
0aab0d3a | 1558 | void pci_qdev_register(PCIDeviceInfo *info) |
6b1b92d3 | 1559 | { |
02e2da45 | 1560 | info->qdev.init = pci_qdev_init; |
ee995ffb | 1561 | info->qdev.unplug = pci_unplug_device; |
a36a344d | 1562 | info->qdev.exit = pci_unregister_device; |
10c4c98a | 1563 | info->qdev.bus_info = &pci_bus_info; |
074f2fff | 1564 | qdev_register(&info->qdev); |
6b1b92d3 PB |
1565 | } |
1566 | ||
0aab0d3a GH |
1567 | void pci_qdev_register_many(PCIDeviceInfo *info) |
1568 | { | |
1569 | while (info->qdev.name) { | |
1570 | pci_qdev_register(info); | |
1571 | info++; | |
1572 | } | |
1573 | } | |
1574 | ||
49823868 IY |
1575 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1576 | const char *name) | |
6b1b92d3 PB |
1577 | { |
1578 | DeviceState *dev; | |
1579 | ||
02e2da45 | 1580 | dev = qdev_create(&bus->qbus, name); |
a6307b08 | 1581 | qdev_prop_set_uint32(dev, "addr", devfn); |
49823868 | 1582 | qdev_prop_set_bit(dev, "multifunction", multifunction); |
71077c1c GH |
1583 | return DO_UPCAST(PCIDevice, qdev, dev); |
1584 | } | |
6b1b92d3 | 1585 | |
49823868 IY |
1586 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
1587 | bool multifunction, | |
1588 | const char *name) | |
71077c1c | 1589 | { |
49823868 | 1590 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
e23a1b33 | 1591 | qdev_init_nofail(&dev->qdev); |
71077c1c | 1592 | return dev; |
6b1b92d3 | 1593 | } |
6f4cbd39 | 1594 | |
49823868 IY |
1595 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1596 | { | |
1597 | return pci_create_multifunction(bus, devfn, false, name); | |
1598 | } | |
1599 | ||
1600 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) | |
1601 | { | |
1602 | return pci_create_simple_multifunction(bus, devfn, false, name); | |
1603 | } | |
1604 | ||
6f4cbd39 MT |
1605 | static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1606 | { | |
a9f49946 | 1607 | int config_size = pci_config_size(pdev); |
6f4cbd39 MT |
1608 | int offset = PCI_CONFIG_HEADER_SIZE; |
1609 | int i; | |
a9f49946 | 1610 | for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i) |
6f4cbd39 MT |
1611 | if (pdev->used[i]) |
1612 | offset = i + 1; | |
1613 | else if (i - offset + 1 == size) | |
1614 | return offset; | |
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, | |
1619 | uint8_t *prev_p) | |
1620 | { | |
1621 | uint8_t next, prev; | |
1622 | ||
1623 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) | |
1624 | return 0; | |
1625 | ||
1626 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); | |
1627 | prev = next + PCI_CAP_LIST_NEXT) | |
1628 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) | |
1629 | break; | |
1630 | ||
1631 | if (prev_p) | |
1632 | *prev_p = prev; | |
1633 | return next; | |
1634 | } | |
1635 | ||
c2039bd0 AL |
1636 | static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1637 | { | |
1638 | cpu_register_physical_memory(addr, size, pdev->rom_offset); | |
1639 | } | |
1640 | ||
1641 | /* Add an option rom for the device */ | |
8c52c8f3 | 1642 | static int pci_add_option_rom(PCIDevice *pdev) |
c2039bd0 AL |
1643 | { |
1644 | int size; | |
1645 | char *path; | |
1646 | void *ptr; | |
1724f049 | 1647 | char name[32]; |
c2039bd0 | 1648 | |
8c52c8f3 GH |
1649 | if (!pdev->romfile) |
1650 | return 0; | |
1651 | if (strlen(pdev->romfile) == 0) | |
1652 | return 0; | |
1653 | ||
88169ddf GH |
1654 | if (!pdev->rom_bar) { |
1655 | /* | |
1656 | * Load rom via fw_cfg instead of creating a rom bar, | |
1657 | * for 0.11 compatibility. | |
1658 | */ | |
1659 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1660 | if (class == 0x0300) { | |
1661 | rom_add_vga(pdev->romfile); | |
1662 | } else { | |
1663 | rom_add_option(pdev->romfile); | |
1664 | } | |
1665 | return 0; | |
1666 | } | |
1667 | ||
8c52c8f3 | 1668 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
c2039bd0 | 1669 | if (path == NULL) { |
8c52c8f3 | 1670 | path = qemu_strdup(pdev->romfile); |
c2039bd0 AL |
1671 | } |
1672 | ||
1673 | size = get_image_size(path); | |
8c52c8f3 | 1674 | if (size < 0) { |
1ecda02b MA |
1675 | error_report("%s: failed to find romfile \"%s\"", |
1676 | __FUNCTION__, pdev->romfile); | |
8c52c8f3 GH |
1677 | return -1; |
1678 | } | |
c2039bd0 AL |
1679 | if (size & (size - 1)) { |
1680 | size = 1 << qemu_fls(size); | |
1681 | } | |
1682 | ||
1724f049 AW |
1683 | if (pdev->qdev.info->vmsd) |
1684 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name); | |
1685 | else | |
1686 | snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name); | |
1687 | pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size); | |
c2039bd0 AL |
1688 | |
1689 | ptr = qemu_get_ram_ptr(pdev->rom_offset); | |
1690 | load_image(path, ptr); | |
1691 | qemu_free(path); | |
1692 | ||
1693 | pci_register_bar(pdev, PCI_ROM_SLOT, size, | |
1694 | 0, pci_map_option_rom); | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | ||
230741dc AW |
1699 | static void pci_del_option_rom(PCIDevice *pdev) |
1700 | { | |
1701 | if (!pdev->rom_offset) | |
1702 | return; | |
1703 | ||
1704 | qemu_ram_free(pdev->rom_offset); | |
1705 | pdev->rom_offset = 0; | |
1706 | } | |
1707 | ||
ca77089d IY |
1708 | /* |
1709 | * if !offset | |
1710 | * Reserve space and add capability to the linked list in pci config space | |
1711 | * | |
1712 | * if offset = 0, | |
1713 | * Find and reserve space and add capability to the linked list | |
1714 | * in pci config space */ | |
1715 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, | |
1716 | uint8_t offset, uint8_t size) | |
6f4cbd39 | 1717 | { |
ca77089d IY |
1718 | uint8_t *config; |
1719 | if (!offset) { | |
1720 | offset = pci_find_space(pdev, size); | |
1721 | if (!offset) { | |
1722 | return -ENOSPC; | |
1723 | } | |
1724 | } | |
1725 | ||
1726 | config = pdev->config + offset; | |
6f4cbd39 MT |
1727 | config[PCI_CAP_LIST_ID] = cap_id; |
1728 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; | |
1729 | pdev->config[PCI_CAPABILITY_LIST] = offset; | |
1730 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
1731 | memset(pdev->used + offset, 0xFF, size); | |
1732 | /* Make capability read-only by default */ | |
1733 | memset(pdev->wmask + offset, 0, size); | |
bd4b65ee MT |
1734 | /* Check capability by default */ |
1735 | memset(pdev->cmask + offset, 0xFF, size); | |
6f4cbd39 MT |
1736 | return offset; |
1737 | } | |
1738 | ||
1739 | /* Unlink capability from the pci config space. */ | |
1740 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) | |
1741 | { | |
1742 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); | |
1743 | if (!offset) | |
1744 | return; | |
1745 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; | |
1746 | /* Make capability writeable again */ | |
1747 | memset(pdev->wmask + offset, 0xff, size); | |
1a4f5971 | 1748 | memset(pdev->w1cmask + offset, 0, size); |
bd4b65ee MT |
1749 | /* Clear cmask as device-specific registers can't be checked */ |
1750 | memset(pdev->cmask + offset, 0, size); | |
6f4cbd39 MT |
1751 | memset(pdev->used + offset, 0, size); |
1752 | ||
1753 | if (!pdev->config[PCI_CAPABILITY_LIST]) | |
1754 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; | |
1755 | } | |
1756 | ||
1757 | /* Reserve space for capability at a known offset (to call after load). */ | |
1758 | void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) | |
1759 | { | |
1760 | memset(pdev->used + offset, 0xff, size); | |
1761 | } | |
1762 | ||
1763 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) | |
1764 | { | |
1765 | return pci_find_capability_list(pdev, cap_id, NULL); | |
1766 | } | |
10c4c98a GH |
1767 | |
1768 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) | |
1769 | { | |
1770 | PCIDevice *d = (PCIDevice *)dev; | |
1771 | const pci_class_desc *desc; | |
1772 | char ctxt[64]; | |
1773 | PCIIORegion *r; | |
1774 | int i, class; | |
1775 | ||
b0ff8eb2 | 1776 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
10c4c98a GH |
1777 | desc = pci_class_descriptions; |
1778 | while (desc->desc && class != desc->class) | |
1779 | desc++; | |
1780 | if (desc->desc) { | |
1781 | snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); | |
1782 | } else { | |
1783 | snprintf(ctxt, sizeof(ctxt), "Class %04x", class); | |
1784 | } | |
1785 | ||
1786 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " | |
1787 | "pci id %04x:%04x (sub %04x:%04x)\n", | |
1788 | indent, "", ctxt, | |
e822a52a IY |
1789 | d->config[PCI_SECONDARY_BUS], |
1790 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), | |
b0ff8eb2 IY |
1791 | pci_get_word(d->config + PCI_VENDOR_ID), |
1792 | pci_get_word(d->config + PCI_DEVICE_ID), | |
1793 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), | |
1794 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); | |
10c4c98a GH |
1795 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1796 | r = &d->io_regions[i]; | |
1797 | if (!r->size) | |
1798 | continue; | |
89e8b13c IY |
1799 | monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS |
1800 | " [0x%"FMT_PCIBUS"]\n", | |
1801 | indent, "", | |
0392a017 | 1802 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
10c4c98a GH |
1803 | r->addr, r->addr + r->size - 1); |
1804 | } | |
1805 | } | |
03587182 | 1806 | |
4f43c1ff AW |
1807 | static char *pcibus_get_dev_path(DeviceState *dev) |
1808 | { | |
1809 | PCIDevice *d = (PCIDevice *)dev; | |
1810 | char path[16]; | |
1811 | ||
1812 | snprintf(path, sizeof(path), "%04x:%02x:%02x.%x", | |
1813 | pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS], | |
1814 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); | |
1815 | ||
1816 | return strdup(path); | |
1817 | } | |
1818 |