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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
376253ec AL |
4 | #include "qemu-common.h" |
5 | ||
6b1b92d3 | 6 | #include "qdev.h" |
1e39101c | 7 | #include "memory.h" |
ec174575 | 8 | #include "dma.h" |
6b1b92d3 | 9 | |
87ecb68b PB |
10 | /* PCI includes legacy ISA access. */ |
11 | #include "isa.h" | |
12 | ||
0428527c IY |
13 | #include "pcie.h" |
14 | ||
87ecb68b PB |
15 | /* PCI bus */ |
16 | ||
3ae80618 AL |
17 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
19 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
90a20dbb | 20 | #define PCI_SLOT_MAX 32 |
6fa84913 | 21 | #define PCI_FUNC_MAX 8 |
3ae80618 | 22 | |
a770dc7e AL |
23 | /* Class, Vendor and Device IDs from Linux's pci_ids.h */ |
24 | #include "pci_ids.h" | |
173a543b | 25 | |
a770dc7e | 26 | /* QEMU-specific Vendor and Device ID definitions */ |
6f338c34 | 27 | |
a770dc7e AL |
28 | /* IBM (0x1014) */ |
29 | #define PCI_DEVICE_ID_IBM_440GX 0x027f | |
4ebcf884 | 30 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 | 31 | |
a770dc7e | 32 | /* Hitachi (0x1054) */ |
deb54399 | 33 | #define PCI_VENDOR_ID_HITACHI 0x1054 |
a770dc7e | 34 | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
deb54399 | 35 | |
a770dc7e | 36 | /* Apple (0x106b) */ |
4ebcf884 BS |
37 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
39 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
4ebcf884 | 40 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
a770dc7e | 41 | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
deb54399 | 42 | |
a770dc7e AL |
43 | /* Realtek (0x10ec) */ |
44 | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 | |
deb54399 | 45 | |
a770dc7e AL |
46 | /* Xilinx (0x10ee) */ |
47 | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 | |
deb54399 | 48 | |
a770dc7e AL |
49 | /* Marvell (0x11ab) */ |
50 | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 | |
deb54399 | 51 | |
a770dc7e | 52 | /* QEMU/Bochs VGA (0x1234) */ |
4ebcf884 BS |
53 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
55 | ||
a770dc7e | 56 | /* VMWare (0x15ad) */ |
deb54399 AL |
57 | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
59 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
60 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
61 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
62 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
63 | ||
cef3017c | 64 | /* Intel (0x8086) */ |
a770dc7e | 65 | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
d6fd1e66 | 66 | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
1a5a86fb | 67 | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
74c62ba8 | 68 | |
deb54399 | 69 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
70 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
71 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
72 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
73 | ||
74 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
75 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
76 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 77 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
973abc7f | 78 | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
d350d97d | 79 | |
4f8589e1 | 80 | #define FMT_PCIBUS PRIx64 |
6e355d90 | 81 | |
87ecb68b PB |
82 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
83 | uint32_t address, uint32_t data, int len); | |
84 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
85 | uint32_t address, int len); | |
86 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 87 | pcibus_t addr, pcibus_t size, int type); |
5851e08c | 88 | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b | 89 | |
87ecb68b | 90 | typedef struct PCIIORegion { |
6e355d90 IY |
91 | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */ |
92 | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) | |
93 | pcibus_t size; | |
87ecb68b | 94 | uint8_t type; |
79ff8cb0 | 95 | MemoryRegion *memory; |
5968eca3 | 96 | MemoryRegion *address_space; |
87ecb68b PB |
97 | } PCIIORegion; |
98 | ||
99 | #define PCI_ROM_SLOT 6 | |
100 | #define PCI_NUM_REGIONS 7 | |
101 | ||
fb58a897 IY |
102 | #include "pci_regs.h" |
103 | ||
104 | /* PCI HEADER_TYPE */ | |
6407f373 | 105 | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
8098ed41 | 106 | |
b7ee1603 MT |
107 | /* Size of the standard PCI config header */ |
108 | #define PCI_CONFIG_HEADER_SIZE 0x40 | |
109 | /* Size of the standard PCI config space */ | |
110 | #define PCI_CONFIG_SPACE_SIZE 0x100 | |
a9f49946 IY |
111 | /* Size of the standart PCIe config space: 4KB */ |
112 | #define PCIE_CONFIG_SPACE_SIZE 0x1000 | |
b7ee1603 | 113 | |
e369cad7 IY |
114 | #define PCI_NUM_PINS 4 /* A-D */ |
115 | ||
02eb84d0 MT |
116 | /* Bits in cap_present field. */ |
117 | enum { | |
e4c7d2ae IY |
118 | QEMU_PCI_CAP_MSI = 0x1, |
119 | QEMU_PCI_CAP_MSIX = 0x2, | |
120 | QEMU_PCI_CAP_EXPRESS = 0x4, | |
49823868 IY |
121 | |
122 | /* multifunction capable device */ | |
e4c7d2ae | 123 | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
49823868 | 124 | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), |
b1aeb926 IY |
125 | |
126 | /* command register SERR bit enabled */ | |
127 | #define QEMU_PCI_CAP_SERR_BITNR 4 | |
128 | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), | |
1dc324d2 MT |
129 | /* Standard hot plug controller. */ |
130 | #define QEMU_PCI_SHPC_BITNR 5 | |
131 | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), | |
762833b3 MT |
132 | #define QEMU_PCI_SLOTID_BITNR 6 |
133 | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), | |
02eb84d0 MT |
134 | }; |
135 | ||
40021f08 AL |
136 | #define TYPE_PCI_DEVICE "pci-device" |
137 | #define PCI_DEVICE(obj) \ | |
138 | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) | |
139 | #define PCI_DEVICE_CLASS(klass) \ | |
140 | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) | |
141 | #define PCI_DEVICE_GET_CLASS(obj) \ | |
142 | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) | |
143 | ||
144 | typedef struct PCIDeviceClass { | |
145 | DeviceClass parent_class; | |
146 | ||
147 | int (*init)(PCIDevice *dev); | |
148 | PCIUnregisterFunc *exit; | |
149 | PCIConfigReadFunc *config_read; | |
150 | PCIConfigWriteFunc *config_write; | |
151 | ||
152 | uint16_t vendor_id; | |
153 | uint16_t device_id; | |
154 | uint8_t revision; | |
155 | uint16_t class_id; | |
156 | uint16_t subsystem_vendor_id; /* only for header type = 0 */ | |
157 | uint16_t subsystem_id; /* only for header type = 0 */ | |
158 | ||
159 | /* | |
160 | * pci-to-pci bridge or normal device. | |
161 | * This doesn't mean pci host switch. | |
162 | * When card bus bridge is supported, this would be enhanced. | |
163 | */ | |
164 | int is_bridge; | |
165 | ||
166 | /* pcie stuff */ | |
167 | int is_express; /* is this device pci express? */ | |
168 | ||
169 | /* device isn't hot-pluggable */ | |
170 | int no_hotplug; | |
171 | ||
172 | /* rom bar */ | |
173 | const char *romfile; | |
174 | } PCIDeviceClass; | |
175 | ||
2cdfe53c JK |
176 | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
177 | MSIMessage msg); | |
178 | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); | |
179 | ||
87ecb68b | 180 | struct PCIDevice { |
6b1b92d3 | 181 | DeviceState qdev; |
87ecb68b | 182 | /* PCI config space */ |
a9f49946 | 183 | uint8_t *config; |
b7ee1603 | 184 | |
ebabb67a | 185 | /* Used to enable config checks on load. Note that writable bits are |
bd4b65ee | 186 | * never checked even if set in cmask. */ |
a9f49946 | 187 | uint8_t *cmask; |
bd4b65ee | 188 | |
b7ee1603 | 189 | /* Used to implement R/W bytes */ |
a9f49946 | 190 | uint8_t *wmask; |
87ecb68b | 191 | |
92ba5f51 IY |
192 | /* Used to implement RW1C(Write 1 to Clear) bytes */ |
193 | uint8_t *w1cmask; | |
194 | ||
6f4cbd39 | 195 | /* Used to allocate config space for capabilities. */ |
a9f49946 | 196 | uint8_t *used; |
6f4cbd39 | 197 | |
87ecb68b PB |
198 | /* the following fields are read only */ |
199 | PCIBus *bus; | |
54586bd1 | 200 | uint32_t devfn; |
87ecb68b PB |
201 | char name[64]; |
202 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
203 | ||
204 | /* do not access the following fields */ | |
205 | PCIConfigReadFunc *config_read; | |
206 | PCIConfigWriteFunc *config_write; | |
87ecb68b PB |
207 | |
208 | /* IRQ objects for the INTA-INTD pins. */ | |
209 | qemu_irq *irq; | |
210 | ||
211 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
d036bb21 | 212 | uint8_t irq_state; |
02eb84d0 MT |
213 | |
214 | /* Capability bits */ | |
215 | uint32_t cap_present; | |
216 | ||
217 | /* Offset of MSI-X capability in config space */ | |
218 | uint8_t msix_cap; | |
219 | ||
220 | /* MSI-X entries */ | |
221 | int msix_entries_nr; | |
222 | ||
223 | /* Space to store MSIX table */ | |
224 | uint8_t *msix_table_page; | |
225 | /* MMIO index used to map MSIX table and pending bit entries. */ | |
95524ae8 | 226 | MemoryRegion msix_mmio; |
02eb84d0 MT |
227 | /* Reference-count for entries actually in use by driver. */ |
228 | unsigned *msix_entry_used; | |
229 | /* Region including the MSI-X table */ | |
230 | uint32_t msix_bar_size; | |
50322249 MT |
231 | /* MSIX function mask set or MSIX disabled */ |
232 | bool msix_function_masked; | |
f16c4abf JQ |
233 | /* Version id needed for VMState */ |
234 | int32_t version_id; | |
c2039bd0 | 235 | |
e4c7d2ae IY |
236 | /* Offset of MSI capability in config space */ |
237 | uint8_t msi_cap; | |
238 | ||
0428527c IY |
239 | /* PCI Express */ |
240 | PCIExpressDevice exp; | |
241 | ||
1dc324d2 MT |
242 | /* SHPC */ |
243 | SHPCDevice *shpc; | |
244 | ||
c2039bd0 | 245 | /* Location of option rom */ |
8c52c8f3 | 246 | char *romfile; |
14caaf7f AK |
247 | bool has_rom; |
248 | MemoryRegion rom; | |
88169ddf | 249 | uint32_t rom_bar; |
2cdfe53c JK |
250 | |
251 | /* MSI-X notifiers */ | |
252 | MSIVectorUseNotifier msix_vector_use_notifier; | |
253 | MSIVectorReleaseNotifier msix_vector_release_notifier; | |
87ecb68b PB |
254 | }; |
255 | ||
e824b2cc AK |
256 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
257 | uint8_t attr, MemoryRegion *memory); | |
16a96f28 | 258 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); |
87ecb68b | 259 | |
ca77089d IY |
260 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
261 | uint8_t offset, uint8_t size); | |
6f4cbd39 MT |
262 | |
263 | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); | |
264 | ||
6f4cbd39 MT |
265 | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
266 | ||
267 | ||
87ecb68b PB |
268 | uint32_t pci_default_read_config(PCIDevice *d, |
269 | uint32_t address, int len); | |
270 | void pci_default_write_config(PCIDevice *d, | |
271 | uint32_t address, uint32_t val, int len); | |
272 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
273 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
f5e6fed8 | 274 | MemoryRegion *pci_address_space(PCIDevice *dev); |
e11d6439 | 275 | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
87ecb68b | 276 | |
5d4e84c8 | 277 | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
87ecb68b | 278 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
e927d487 MT |
279 | |
280 | typedef enum { | |
281 | PCI_HOTPLUG_DISABLED, | |
282 | PCI_HOTPLUG_ENABLED, | |
283 | PCI_COLDPLUG_ENABLED, | |
284 | } PCIHotplugState; | |
285 | ||
286 | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, | |
287 | PCIHotplugState state); | |
21eea4b3 | 288 | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, |
1e39101c | 289 | const char *name, |
aee97b84 AK |
290 | MemoryRegion *address_space_mem, |
291 | MemoryRegion *address_space_io, | |
1e39101c AK |
292 | uint8_t devfn_min); |
293 | PCIBus *pci_bus_new(DeviceState *parent, const char *name, | |
aee97b84 AK |
294 | MemoryRegion *address_space_mem, |
295 | MemoryRegion *address_space_io, | |
296 | uint8_t devfn_min); | |
21eea4b3 GH |
297 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
298 | void *irq_opaque, int nirq); | |
9ddf8437 | 299 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
87c30546 | 300 | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); |
02e2da45 PB |
301 | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
302 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
1e39101c | 303 | void *irq_opaque, |
aee97b84 AK |
304 | MemoryRegion *address_space_mem, |
305 | MemoryRegion *address_space_io, | |
1e39101c | 306 | uint8_t devfn_min, int nirq); |
0ead87c8 | 307 | void pci_device_reset(PCIDevice *dev); |
9bb33586 | 308 | void pci_bus_reset(PCIBus *bus); |
87ecb68b | 309 | |
5607c388 MA |
310 | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
311 | const char *default_devaddr); | |
07caea31 MA |
312 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
313 | const char *default_devaddr); | |
87ecb68b | 314 | int pci_bus_num(PCIBus *s); |
e822a52a | 315 | void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
c469e1dd | 316 | PCIBus *pci_find_root_bus(int domain); |
e075e788 | 317 | int pci_find_domain(const PCIBus *bus); |
5256d8bf | 318 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); |
f3006dd1 | 319 | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
49bd1458 | 320 | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
87ecb68b | 321 | |
e9283f8b JK |
322 | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
323 | unsigned *slotp); | |
880345c4 | 324 | |
4c92325b IY |
325 | void pci_device_deassert_intx(PCIDevice *dev); |
326 | ||
64d50b8b MT |
327 | static inline void |
328 | pci_set_byte(uint8_t *config, uint8_t val) | |
329 | { | |
330 | *config = val; | |
331 | } | |
332 | ||
333 | static inline uint8_t | |
cb95c2e4 | 334 | pci_get_byte(const uint8_t *config) |
64d50b8b MT |
335 | { |
336 | return *config; | |
337 | } | |
338 | ||
14e12559 MT |
339 | static inline void |
340 | pci_set_word(uint8_t *config, uint16_t val) | |
341 | { | |
342 | cpu_to_le16wu((uint16_t *)config, val); | |
343 | } | |
344 | ||
345 | static inline uint16_t | |
cb95c2e4 | 346 | pci_get_word(const uint8_t *config) |
14e12559 | 347 | { |
cb95c2e4 | 348 | return le16_to_cpupu((const uint16_t *)config); |
14e12559 MT |
349 | } |
350 | ||
351 | static inline void | |
352 | pci_set_long(uint8_t *config, uint32_t val) | |
353 | { | |
354 | cpu_to_le32wu((uint32_t *)config, val); | |
355 | } | |
356 | ||
357 | static inline uint32_t | |
cb95c2e4 | 358 | pci_get_long(const uint8_t *config) |
14e12559 | 359 | { |
cb95c2e4 | 360 | return le32_to_cpupu((const uint32_t *)config); |
14e12559 MT |
361 | } |
362 | ||
fb5ce7d2 IY |
363 | static inline void |
364 | pci_set_quad(uint8_t *config, uint64_t val) | |
365 | { | |
366 | cpu_to_le64w((uint64_t *)config, val); | |
367 | } | |
368 | ||
369 | static inline uint64_t | |
cb95c2e4 | 370 | pci_get_quad(const uint8_t *config) |
fb5ce7d2 | 371 | { |
cb95c2e4 | 372 | return le64_to_cpup((const uint64_t *)config); |
fb5ce7d2 IY |
373 | } |
374 | ||
deb54399 AL |
375 | static inline void |
376 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
377 | { | |
14e12559 | 378 | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
deb54399 AL |
379 | } |
380 | ||
381 | static inline void | |
382 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
383 | { | |
14e12559 | 384 | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
deb54399 AL |
385 | } |
386 | ||
cf602c7b IE |
387 | static inline void |
388 | pci_config_set_revision(uint8_t *pci_config, uint8_t val) | |
389 | { | |
390 | pci_set_byte(&pci_config[PCI_REVISION_ID], val); | |
391 | } | |
392 | ||
173a543b BS |
393 | static inline void |
394 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
395 | { | |
14e12559 | 396 | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
173a543b BS |
397 | } |
398 | ||
cf602c7b IE |
399 | static inline void |
400 | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) | |
401 | { | |
402 | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); | |
403 | } | |
404 | ||
405 | static inline void | |
406 | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) | |
407 | { | |
408 | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); | |
409 | } | |
410 | ||
aabcf526 IY |
411 | /* |
412 | * helper functions to do bit mask operation on configuration space. | |
413 | * Just to set bit, use test-and-set and discard returned value. | |
414 | * Just to clear bit, use test-and-clear and discard returned value. | |
415 | * NOTE: They aren't atomic. | |
416 | */ | |
417 | static inline uint8_t | |
418 | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) | |
419 | { | |
420 | uint8_t val = pci_get_byte(config); | |
421 | pci_set_byte(config, val & ~mask); | |
422 | return val & mask; | |
423 | } | |
424 | ||
425 | static inline uint8_t | |
426 | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) | |
427 | { | |
428 | uint8_t val = pci_get_byte(config); | |
429 | pci_set_byte(config, val | mask); | |
430 | return val & mask; | |
431 | } | |
432 | ||
433 | static inline uint16_t | |
434 | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) | |
435 | { | |
436 | uint16_t val = pci_get_word(config); | |
437 | pci_set_word(config, val & ~mask); | |
438 | return val & mask; | |
439 | } | |
440 | ||
441 | static inline uint16_t | |
442 | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) | |
443 | { | |
444 | uint16_t val = pci_get_word(config); | |
445 | pci_set_word(config, val | mask); | |
446 | return val & mask; | |
447 | } | |
448 | ||
449 | static inline uint32_t | |
450 | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) | |
451 | { | |
452 | uint32_t val = pci_get_long(config); | |
453 | pci_set_long(config, val & ~mask); | |
454 | return val & mask; | |
455 | } | |
456 | ||
457 | static inline uint32_t | |
458 | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) | |
459 | { | |
460 | uint32_t val = pci_get_long(config); | |
461 | pci_set_long(config, val | mask); | |
462 | return val & mask; | |
463 | } | |
464 | ||
465 | static inline uint64_t | |
466 | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) | |
467 | { | |
468 | uint64_t val = pci_get_quad(config); | |
469 | pci_set_quad(config, val & ~mask); | |
470 | return val & mask; | |
471 | } | |
472 | ||
473 | static inline uint64_t | |
474 | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) | |
475 | { | |
476 | uint64_t val = pci_get_quad(config); | |
477 | pci_set_quad(config, val | mask); | |
478 | return val & mask; | |
479 | } | |
480 | ||
c9f50cea MT |
481 | /* Access a register specified by a mask */ |
482 | static inline void | |
483 | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) | |
484 | { | |
485 | uint8_t val = pci_get_byte(config); | |
486 | uint8_t rval = reg << (ffs(mask) - 1); | |
487 | pci_set_byte(config, (~mask & val) | (mask & rval)); | |
488 | } | |
489 | ||
490 | static inline uint8_t | |
491 | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) | |
492 | { | |
493 | uint8_t val = pci_get_byte(config); | |
494 | return (val & mask) >> (ffs(mask) - 1); | |
495 | } | |
496 | ||
497 | static inline void | |
498 | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) | |
499 | { | |
500 | uint16_t val = pci_get_word(config); | |
501 | uint16_t rval = reg << (ffs(mask) - 1); | |
502 | pci_set_word(config, (~mask & val) | (mask & rval)); | |
503 | } | |
504 | ||
505 | static inline uint16_t | |
506 | pci_get_word_by_mask(uint8_t *config, uint16_t mask) | |
507 | { | |
508 | uint16_t val = pci_get_word(config); | |
509 | return (val & mask) >> (ffs(mask) - 1); | |
510 | } | |
511 | ||
512 | static inline void | |
513 | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) | |
514 | { | |
515 | uint32_t val = pci_get_long(config); | |
516 | uint32_t rval = reg << (ffs(mask) - 1); | |
517 | pci_set_long(config, (~mask & val) | (mask & rval)); | |
518 | } | |
519 | ||
520 | static inline uint32_t | |
521 | pci_get_long_by_mask(uint8_t *config, uint32_t mask) | |
522 | { | |
523 | uint32_t val = pci_get_long(config); | |
524 | return (val & mask) >> (ffs(mask) - 1); | |
525 | } | |
526 | ||
527 | static inline void | |
528 | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) | |
529 | { | |
530 | uint64_t val = pci_get_quad(config); | |
531 | uint64_t rval = reg << (ffs(mask) - 1); | |
532 | pci_set_quad(config, (~mask & val) | (mask & rval)); | |
533 | } | |
534 | ||
535 | static inline uint64_t | |
536 | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) | |
537 | { | |
538 | uint64_t val = pci_get_quad(config); | |
539 | return (val & mask) >> (ffs(mask) - 1); | |
540 | } | |
541 | ||
49823868 IY |
542 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
543 | const char *name); | |
544 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, | |
545 | bool multifunction, | |
546 | const char *name); | |
499cf102 | 547 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
6b1b92d3 PB |
548 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
549 | ||
3c18685f | 550 | static inline int pci_is_express(const PCIDevice *d) |
a9f49946 IY |
551 | { |
552 | return d->cap_present & QEMU_PCI_CAP_EXPRESS; | |
553 | } | |
554 | ||
3c18685f | 555 | static inline uint32_t pci_config_size(const PCIDevice *d) |
a9f49946 IY |
556 | { |
557 | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; | |
558 | } | |
559 | ||
ec174575 DG |
560 | /* DMA access functions */ |
561 | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, | |
562 | void *buf, dma_addr_t len, DMADirection dir) | |
563 | { | |
564 | cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, | |
569 | void *buf, dma_addr_t len) | |
570 | { | |
571 | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE); | |
572 | } | |
573 | ||
574 | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, | |
575 | const void *buf, dma_addr_t len) | |
576 | { | |
577 | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); | |
578 | } | |
579 | ||
580 | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \ | |
581 | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ | |
582 | dma_addr_t addr) \ | |
583 | { \ | |
584 | return ld##_l##_phys(addr); \ | |
585 | } \ | |
586 | static inline void st##_s##_pci_dma(PCIDevice *dev, \ | |
587 | dma_addr_t addr, uint##_bits##_t val) \ | |
588 | { \ | |
589 | st##_s##_phys(addr, val); \ | |
590 | } | |
591 | ||
592 | PCI_DMA_DEFINE_LDST(ub, b, 8); | |
593 | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) | |
594 | PCI_DMA_DEFINE_LDST(l_le, l_le, 32); | |
595 | PCI_DMA_DEFINE_LDST(q_le, q_le, 64); | |
596 | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) | |
597 | PCI_DMA_DEFINE_LDST(l_be, l_be, 32); | |
598 | PCI_DMA_DEFINE_LDST(q_be, q_be, 64); | |
599 | ||
600 | #undef PCI_DMA_DEFINE_LDST | |
601 | ||
602 | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, | |
603 | dma_addr_t *plen, DMADirection dir) | |
604 | { | |
605 | target_phys_addr_t len = *plen; | |
606 | void *buf; | |
607 | ||
608 | buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE); | |
609 | *plen = len; | |
610 | return buf; | |
611 | } | |
612 | ||
613 | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, | |
614 | DMADirection dir, dma_addr_t access_len) | |
615 | { | |
616 | cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE, | |
617 | access_len); | |
618 | } | |
619 | ||
620 | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, | |
621 | int alloc_hint) | |
622 | { | |
623 | qemu_sglist_init(qsg, alloc_hint); | |
624 | } | |
625 | ||
701a8f76 PB |
626 | extern const VMStateDescription vmstate_pci_device; |
627 | ||
628 | #define VMSTATE_PCI_DEVICE(_field, _state) { \ | |
629 | .name = (stringify(_field)), \ | |
630 | .size = sizeof(PCIDevice), \ | |
631 | .vmsd = &vmstate_pci_device, \ | |
632 | .flags = VMS_STRUCT, \ | |
633 | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ | |
634 | } | |
635 | ||
636 | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \ | |
637 | .name = (stringify(_field)), \ | |
638 | .size = sizeof(PCIDevice), \ | |
639 | .vmsd = &vmstate_pci_device, \ | |
640 | .flags = VMS_STRUCT|VMS_POINTER, \ | |
641 | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ | |
642 | } | |
643 | ||
87ecb68b | 644 | #endif |