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87ecb68b PB |
1 | #ifndef QEMU_PCI_H |
2 | #define QEMU_PCI_H | |
3 | ||
4 | /* PCI includes legacy ISA access. */ | |
5 | #include "isa.h" | |
6 | ||
7 | /* PCI bus */ | |
8 | ||
9 | extern target_phys_addr_t pci_mem_base; | |
10 | ||
3ae80618 AL |
11 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
12 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
13 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
14 | ||
173a543b BS |
15 | /* Device classes and subclasses */ |
16 | ||
6f338c34 AL |
17 | #define PCI_BASE_CLASS_STORAGE 0x01 |
18 | #define PCI_BASE_CLASS_NETWORK 0x02 | |
19 | ||
173a543b BS |
20 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
21 | #define PCI_CLASS_STORAGE_IDE 0x0101 | |
22 | #define PCI_CLASS_STORAGE_OTHER 0x0180 | |
23 | ||
24 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 | |
25 | ||
26 | #define PCI_CLASS_DISPLAY_VGA 0x0300 | |
27 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 | |
28 | ||
29 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 | |
30 | ||
31 | #define PCI_CLASS_MEMORY_RAM 0x0500 | |
32 | ||
33 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 | |
34 | ||
35 | #define PCI_CLASS_SERIAL_USB 0x0c03 | |
36 | ||
37 | #define PCI_CLASS_BRIDGE_HOST 0x0600 | |
38 | #define PCI_CLASS_BRIDGE_ISA 0x0601 | |
39 | #define PCI_CLASS_BRIDGE_PCI 0x0604 | |
40 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 | |
41 | ||
42 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 | |
74c62ba8 | 43 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
173a543b BS |
44 | |
45 | #define PCI_CLASS_OTHERS 0xff | |
46 | ||
47 | /* Vendors and devices. */ | |
48 | ||
deb54399 AL |
49 | #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 |
50 | #define PCI_DEVICE_ID_LSI_53C895A 0x0012 | |
51 | ||
52 | #define PCI_VENDOR_ID_DEC 0x1011 | |
4ebcf884 | 53 | #define PCI_DEVICE_ID_DEC_21154 0x0026 |
deb54399 AL |
54 | |
55 | #define PCI_VENDOR_ID_CIRRUS 0x1013 | |
56 | ||
57 | #define PCI_VENDOR_ID_IBM 0x1014 | |
4ebcf884 | 58 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
deb54399 AL |
59 | |
60 | #define PCI_VENDOR_ID_AMD 0x1022 | |
61 | #define PCI_DEVICE_ID_AMD_LANCE 0x2000 | |
62 | ||
63 | #define PCI_VENDOR_ID_HITACHI 0x1054 | |
64 | ||
65 | #define PCI_VENDOR_ID_MOTOROLA 0x1057 | |
66 | #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 | |
67 | #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 | |
68 | ||
69 | #define PCI_VENDOR_ID_APPLE 0x106b | |
4ebcf884 BS |
70 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
71 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e | |
72 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f | |
deb54399 | 73 | #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 |
4ebcf884 | 74 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
deb54399 AL |
75 | |
76 | #define PCI_VENDOR_ID_SUN 0x108e | |
77 | #define PCI_DEVICE_ID_SUN_EBUS 0x1000 | |
480b9f24 | 78 | #define PCI_DEVICE_ID_SUN_SIMBA 0x5000 |
deb54399 AL |
79 | #define PCI_DEVICE_ID_SUN_SABRE 0xa000 |
80 | ||
81 | #define PCI_VENDOR_ID_CMD 0x1095 | |
82 | #define PCI_DEVICE_ID_CMD_646 0x0646 | |
83 | ||
84 | #define PCI_VENDOR_ID_REALTEK 0x10ec | |
4ebcf884 | 85 | #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029 |
deb54399 AL |
86 | #define PCI_DEVICE_ID_REALTEK_8139 0x8139 |
87 | ||
88 | #define PCI_VENDOR_ID_XILINX 0x10ee | |
89 | ||
90 | #define PCI_VENDOR_ID_MARVELL 0x11ab | |
91 | ||
4ebcf884 BS |
92 | #define PCI_VENDOR_ID_QEMU 0x1234 |
93 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 | |
94 | ||
deb54399 AL |
95 | #define PCI_VENDOR_ID_ENSONIQ 0x1274 |
96 | #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 | |
97 | ||
98 | #define PCI_VENDOR_ID_VMWARE 0x15ad | |
99 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | |
100 | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 | |
101 | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 | |
102 | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 | |
103 | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 | |
104 | ||
105 | #define PCI_VENDOR_ID_INTEL 0x8086 | |
106 | #define PCI_DEVICE_ID_INTEL_82441 0x1237 | |
107 | #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 | |
108 | #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 | |
109 | #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 | |
110 | #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 | |
111 | #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 | |
112 | #define PCI_DEVICE_ID_INTEL_82371AB 0x7111 | |
113 | #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 | |
114 | #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 | |
115 | ||
74c62ba8 AJ |
116 | #define PCI_VENDOR_ID_FSL 0x1957 |
117 | #define PCI_DEVICE_ID_FSL_E500 0x0030 | |
118 | ||
deb54399 | 119 | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
d350d97d AL |
120 | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
121 | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 | |
122 | #define PCI_SUBDEVICE_ID_QEMU 0x1100 | |
123 | ||
124 | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 | |
125 | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 | |
126 | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 | |
14d50bef | 127 | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
d350d97d | 128 | |
87ecb68b PB |
129 | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
130 | uint32_t address, uint32_t data, int len); | |
131 | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev, | |
132 | uint32_t address, int len); | |
133 | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, | |
134 | uint32_t addr, uint32_t size, int type); | |
5851e08c | 135 | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
87ecb68b PB |
136 | |
137 | #define PCI_ADDRESS_SPACE_MEM 0x00 | |
138 | #define PCI_ADDRESS_SPACE_IO 0x01 | |
139 | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 | |
140 | ||
141 | typedef struct PCIIORegion { | |
142 | uint32_t addr; /* current PCI mapping address. -1 means not mapped */ | |
143 | uint32_t size; | |
144 | uint8_t type; | |
145 | PCIMapIORegionFunc *map_func; | |
146 | } PCIIORegion; | |
147 | ||
148 | #define PCI_ROM_SLOT 6 | |
149 | #define PCI_NUM_REGIONS 7 | |
150 | ||
151 | #define PCI_DEVICES_MAX 64 | |
152 | ||
153 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ | |
154 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
155 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
156 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
157 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
d350d97d | 158 | #define PCI_REVISION 0x08 |
87ecb68b | 159 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
d350d97d AL |
160 | #define PCI_SUBVENDOR_ID 0x2c /* 16 bits */ |
161 | #define PCI_SUBDEVICE_ID 0x2e /* 16 bits */ | |
87ecb68b PB |
162 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
163 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
164 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
165 | #define PCI_MAX_LAT 0x3f /* 8 bits */ | |
166 | ||
8098ed41 AJ |
167 | /* Bits in the PCI Status Register (PCI 2.3 spec) */ |
168 | #define PCI_STATUS_RESERVED1 0x007 | |
169 | #define PCI_STATUS_INT_STATUS 0x008 | |
170 | #define PCI_STATUS_CAPABILITIES 0x010 | |
171 | #define PCI_STATUS_66MHZ 0x020 | |
172 | #define PCI_STATUS_RESERVED2 0x040 | |
173 | #define PCI_STATUS_FAST_BACK 0x080 | |
174 | #define PCI_STATUS_DEVSEL 0x600 | |
175 | ||
176 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \ | |
177 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ | |
178 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) | |
179 | ||
180 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) | |
181 | ||
475dc65f AJ |
182 | /* Bits in the PCI Command Register (PCI 2.3 spec) */ |
183 | #define PCI_COMMAND_RESERVED 0xf800 | |
184 | ||
185 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) | |
186 | ||
87ecb68b PB |
187 | struct PCIDevice { |
188 | /* PCI config space */ | |
189 | uint8_t config[256]; | |
190 | ||
191 | /* the following fields are read only */ | |
192 | PCIBus *bus; | |
193 | int devfn; | |
194 | char name[64]; | |
195 | PCIIORegion io_regions[PCI_NUM_REGIONS]; | |
196 | ||
197 | /* do not access the following fields */ | |
198 | PCIConfigReadFunc *config_read; | |
199 | PCIConfigWriteFunc *config_write; | |
5851e08c | 200 | PCIUnregisterFunc *unregister; |
87ecb68b PB |
201 | /* ??? This is a PC-specific hack, and should be removed. */ |
202 | int irq_index; | |
203 | ||
204 | /* IRQ objects for the INTA-INTD pins. */ | |
205 | qemu_irq *irq; | |
206 | ||
207 | /* Current IRQ levels. Used internally by the generic PCI code. */ | |
208 | int irq_state[4]; | |
209 | }; | |
210 | ||
211 | PCIDevice *pci_register_device(PCIBus *bus, const char *name, | |
212 | int instance_size, int devfn, | |
213 | PCIConfigReadFunc *config_read, | |
214 | PCIConfigWriteFunc *config_write); | |
5851e08c | 215 | int pci_unregister_device(PCIDevice *pci_dev); |
87ecb68b PB |
216 | |
217 | void pci_register_io_region(PCIDevice *pci_dev, int region_num, | |
218 | uint32_t size, int type, | |
219 | PCIMapIORegionFunc *map_func); | |
220 | ||
221 | uint32_t pci_default_read_config(PCIDevice *d, | |
222 | uint32_t address, int len); | |
223 | void pci_default_write_config(PCIDevice *d, | |
224 | uint32_t address, uint32_t val, int len); | |
225 | void pci_device_save(PCIDevice *s, QEMUFile *f); | |
226 | int pci_device_load(PCIDevice *s, QEMUFile *f); | |
227 | ||
228 | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); | |
229 | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); | |
230 | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
231 | qemu_irq *pic, int devfn_min, int nirq); | |
232 | ||
72da4208 | 233 | PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, |
cb457d76 | 234 | const char *default_model); |
87ecb68b PB |
235 | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
236 | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); | |
237 | int pci_bus_num(PCIBus *s); | |
238 | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); | |
3ae80618 AL |
239 | PCIBus *pci_find_bus(int bus_num); |
240 | PCIDevice *pci_find_device(int bus_num, int slot, int function); | |
87ecb68b | 241 | |
880345c4 AL |
242 | int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp); |
243 | int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp); | |
244 | ||
87ecb68b | 245 | void pci_info(void); |
480b9f24 | 246 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, |
87ecb68b PB |
247 | pci_map_irq_fn map_irq, const char *name); |
248 | ||
deb54399 AL |
249 | static inline void |
250 | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) | |
251 | { | |
252 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val); | |
253 | } | |
254 | ||
255 | static inline void | |
256 | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) | |
257 | { | |
258 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val); | |
259 | } | |
260 | ||
173a543b BS |
261 | static inline void |
262 | pci_config_set_class(uint8_t *pci_config, uint16_t val) | |
263 | { | |
264 | cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val); | |
265 | } | |
266 | ||
87ecb68b | 267 | /* lsi53c895a.c */ |
e4bcb14c | 268 | #define LSI_MAX_DEVS 7 |
87ecb68b PB |
269 | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
270 | void *lsi_scsi_init(PCIBus *bus, int devfn); | |
271 | ||
272 | /* vmware_vga.c */ | |
3023f332 | 273 | void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base, |
87ecb68b PB |
274 | unsigned long vga_ram_offset, int vga_ram_size); |
275 | ||
276 | /* usb-uhci.c */ | |
277 | void usb_uhci_piix3_init(PCIBus *bus, int devfn); | |
278 | void usb_uhci_piix4_init(PCIBus *bus, int devfn); | |
279 | ||
280 | /* usb-ohci.c */ | |
281 | void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn); | |
282 | ||
283 | /* eepro100.c */ | |
284 | ||
72da4208 AL |
285 | PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
286 | PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); | |
287 | PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); | |
87ecb68b PB |
288 | |
289 | /* ne2000.c */ | |
290 | ||
72da4208 | 291 | PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
87ecb68b PB |
292 | |
293 | /* rtl8139.c */ | |
294 | ||
72da4208 | 295 | PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
87ecb68b | 296 | |
7c23b892 | 297 | /* e1000.c */ |
72da4208 | 298 | PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn); |
7c23b892 | 299 | |
87ecb68b | 300 | /* pcnet.c */ |
72da4208 | 301 | PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
87ecb68b PB |
302 | |
303 | /* prep_pci.c */ | |
304 | PCIBus *pci_prep_init(qemu_irq *pic); | |
305 | ||
306 | /* apb_pci.c */ | |
c190ea07 BS |
307 | PCIBus *pci_apb_init(target_phys_addr_t special_base, |
308 | target_phys_addr_t mem_base, | |
309 | qemu_irq *pic, PCIBus **bus2, PCIBus **bus3); | |
87ecb68b | 310 | |
b79e1752 AJ |
311 | /* sh_pci.c */ |
312 | PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, | |
313 | qemu_irq *pic, int devfn_min, int nirq); | |
314 | ||
87ecb68b | 315 | #endif |