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1/*
2 * pci_host.c
3 *
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
70539e18 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 */
20
21#include "pci.h"
22#include "pci_host.h"
23
24/* debug PCI */
25//#define DEBUG_PCI
26
27#ifdef DEBUG_PCI
28#define PCI_DPRINTF(fmt, ...) \
29do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
30#else
31#define PCI_DPRINTF(fmt, ...)
32#endif
33
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34/*
35 * PCI address
36 * bit 16 - 24: bus number
37 * bit 8 - 15: devfun number
38 * bit 0 - 7: offset in configuration space of a given pci device
39 */
40
41/* the helper functio to get a PCIDeice* for a given pci address */
8d6514f8 42static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
766347cc 43{
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44 uint8_t bus_num = addr >> 16;
45 uint8_t devfn = addr >> 8;
46
5256d8bf 47 return pci_find_device(bus, bus_num, devfn);
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48}
49
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50void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
51 uint32_t limit, uint32_t val, uint32_t len)
52{
53 assert(len <= 4);
54 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
55}
56
57uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
58 uint32_t limit, uint32_t len)
59{
60 assert(len <= 4);
61 return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
62}
63
ce195fb5 64void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
766347cc 65{
8d6514f8 66 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
7ac901cd 67 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
766347cc 68
42e4126b 69 if (!pci_dev) {
766347cc 70 return;
42e4126b 71 }
766347cc 72
0b987f19 73 PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
766347cc 74 __func__, pci_dev->name, config_addr, val, len);
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75 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
76 val, len);
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77}
78
ce195fb5 79uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
766347cc 80{
8d6514f8 81 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
7ac901cd 82 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
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83 uint32_t val;
84
85 if (!pci_dev) {
4677d8ed 86 return ~0x0;
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87 }
88
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89 val = pci_host_config_read_common(pci_dev, config_addr,
90 PCI_CONFIG_SPACE_SIZE, len);
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91 PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
92 __func__, pci_dev->name, config_addr, val, len);
93
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94 return val;
95}
96
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97static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
98 uint64_t val, unsigned len)
a455783b 99{
d0ed8076 100 PCIHostState *s = opaque;
a455783b 101
d0ed8076 102 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
9f6f0423 103 __func__, addr, len, val);
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104 s->config_reg = val;
105}
106
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107static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
108 unsigned len)
a455783b 109{
d0ed8076 110 PCIHostState *s = opaque;
a455783b 111 uint32_t val = s->config_reg;
952760bb 112
d0ed8076 113 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
9f6f0423 114 __func__, addr, len, val);
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115 return val;
116}
117
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118static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
119 uint64_t val, unsigned len)
a455783b 120{
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121 PCIHostState *s = opaque;
122 PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
123 addr, len, (unsigned)val);
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124 if (s->config_reg & (1u << 31))
125 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
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126}
127
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128static uint64_t pci_host_data_read(void *opaque,
129 target_phys_addr_t addr, unsigned len)
a455783b 130{
d0ed8076 131 PCIHostState *s = opaque;
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132 uint32_t val;
133 if (!(s->config_reg & (1 << 31)))
134 return 0xffffffff;
135 val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
d0ed8076 136 PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
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137 addr, len, val);
138 return val;
9f6f0423 139}
a455783b 140
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141const MemoryRegionOps pci_host_conf_le_ops = {
142 .read = pci_host_config_read,
143 .write = pci_host_config_write,
144 .endianness = DEVICE_LITTLE_ENDIAN,
145};
a455783b 146
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147const MemoryRegionOps pci_host_conf_be_ops = {
148 .read = pci_host_config_read,
149 .write = pci_host_config_write,
150 .endianness = DEVICE_BIG_ENDIAN,
151};
d2c33733 152
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153const MemoryRegionOps pci_host_data_le_ops = {
154 .read = pci_host_data_read,
155 .write = pci_host_data_write,
156 .endianness = DEVICE_LITTLE_ENDIAN,
157};
158
159const MemoryRegionOps pci_host_data_be_ops = {
160 .read = pci_host_data_read,
161 .write = pci_host_data_write,
162 .endianness = DEVICE_BIG_ENDIAN,
163};
a455783b 164
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