[mirror_qemu.git] / hw / pci_host.c

/*
 * pci_host.c
 *
 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include "pci.h"
#include "pci_host.h"

/* debug PCI */
//#define DEBUG_PCI

#ifdef DEBUG_PCI
#define PCI_DPRINTF(fmt, ...) \
do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
#else
#define PCI_DPRINTF(fmt, ...)
#endif

/*
 * PCI address
 * bit 16 - 24: bus number
 * bit  8 - 15: devfun number
 * bit  0 -  7: offset in configuration space of a given pci device
 */

/* the helper functio to get a PCIDeice* for a given pci address */
static inline PCIDevice *pci_addr_to_dev(PCIBus *bus, uint32_t addr)
{
    uint8_t bus_num = (addr >> 16) & 0xff;
    uint8_t devfn = (addr >> 8) & 0xff;
    return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
}

static inline uint32_t pci_addr_to_config(uint32_t addr)
{
    return addr & (PCI_CONFIG_SPACE_SIZE - 1);
}

void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
{
    PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
    uint32_t config_addr = pci_addr_to_config(addr);

    if (!pci_dev)
        return;

    PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRI32x" len=%d\n",
                __func__, pci_dev->name, config_addr, val, len);
    pci_dev->config_write(pci_dev, config_addr, val, len);
}

uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
{
    PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
    uint32_t config_addr = pci_addr_to_config(addr);
    uint32_t val;

    assert(len == 1 || len == 2 || len == 4);
    if (!pci_dev) {
        return ~0x0;
    }

    val = pci_dev->config_read(pci_dev, config_addr, len);
    PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
                __func__, pci_dev->name, config_addr, val, len);

    return val;
}

static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    PCIHostState *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
                __func__, addr, val);
    s->config_reg = val;
}

static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr)
{
    PCIHostState *s = opaque;
    uint32_t val = s->config_reg;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
                __func__, addr, val);
    return val;
}

static CPUWriteMemoryFunc * const pci_host_config_write[] = {
    &pci_host_config_writel,
    &pci_host_config_writel,
    &pci_host_config_writel,
};

static CPUReadMemoryFunc * const pci_host_config_read[] = {
    &pci_host_config_readl,
    &pci_host_config_readl,
    &pci_host_config_readl,
};

int pci_host_config_register_io_memory(PCIHostState *s)
{
    return cpu_register_io_memory(pci_host_config_read,
                                  pci_host_config_write, s);
}

static void pci_host_config_writel_noswap(void *opaque,
                                          target_phys_addr_t addr,
                                          uint32_t val)
{
    PCIHostState *s = opaque;

    PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
                __func__, addr, val);
    s->config_reg = val;
}

static uint32_t pci_host_config_readl_noswap(void *opaque,
                                             target_phys_addr_t addr)
{
    PCIHostState *s = opaque;
    uint32_t val = s->config_reg;

    PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
                __func__, addr, val);
    return val;
}

static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
    &pci_host_config_writel_noswap,
    &pci_host_config_writel_noswap,
    &pci_host_config_writel_noswap,
};

static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
    &pci_host_config_readl_noswap,
    &pci_host_config_readl_noswap,
    &pci_host_config_readl_noswap,
};

int pci_host_config_register_io_memory_noswap(PCIHostState *s)
{
    return cpu_register_io_memory(pci_host_config_read_noswap,
                                  pci_host_config_write_noswap, s);
}

static void pci_host_config_writel_ioport(void *opaque,
                                          uint32_t addr, uint32_t val)
{
    PCIHostState *s = opaque;

    PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
    s->config_reg = val;
}

static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
{
    PCIHostState *s = opaque;
    uint32_t val = s->config_reg;

    PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
    return val;
}

void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
    register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
    register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
}

#define PCI_ADDR_T      target_phys_addr_t
#define PCI_HOST_SUFFIX _mmio

#include "pci_host_template.h"

static CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = {
    pci_host_data_writeb_mmio,
    pci_host_data_writew_mmio,
    pci_host_data_writel_mmio,
};

static CPUReadMemoryFunc * const pci_host_data_read_mmio[] = {
    pci_host_data_readb_mmio,
    pci_host_data_readw_mmio,
    pci_host_data_readl_mmio,
};

int pci_host_data_register_io_memory(PCIHostState *s)
{
    return cpu_register_io_memory(pci_host_data_read_mmio,
                                  pci_host_data_write_mmio,
                                  s);
}

#undef PCI_ADDR_T
#undef PCI_HOST_SUFFIX

#define PCI_ADDR_T      uint32_t
#define PCI_HOST_SUFFIX _ioport

#include "pci_host_template.h"

void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
    register_ioport_write(ioport, 4, 1, pci_host_data_writeb_ioport, s);
    register_ioport_write(ioport, 4, 2, pci_host_data_writew_ioport, s);
    register_ioport_write(ioport, 4, 4, pci_host_data_writel_ioport, s);
    register_ioport_read(ioport, 4, 1, pci_host_data_readb_ioport, s);
    register_ioport_read(ioport, 4, 2, pci_host_data_readw_ioport, s);
    register_ioport_read(ioport, 4, 4, pci_host_data_readl_ioport, s);
}
Commit	Line	Data
4f5e19e6 IY	1	/*
	2	* pci_host.c
	3	*
	4	* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
	5	* VA Linux Systems Japan K.K.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, write to the Free Software Foundation, Inc.,
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	20	*/
	21
	22	#include "pci.h"
	23	#include "pci_host.h"
	24
	25	/* debug PCI */
	26	//#define DEBUG_PCI
	27
	28	#ifdef DEBUG_PCI
	29	#define PCI_DPRINTF(fmt, ...) \
	30	do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
	31	#else
	32	#define PCI_DPRINTF(fmt, ...)
	33	#endif
	34
766347cc IY	35	/*
	36	* PCI address
	37	* bit 16 - 24: bus number
	38	* bit 8 - 15: devfun number
	39	* bit 0 - 7: offset in configuration space of a given pci device
	40	*/
	41
	42	/* the helper functio to get a PCIDeice* for a given pci address */
	43	static inline PCIDevice pci_addr_to_dev(PCIBus bus, uint32_t addr)
	44	{
	45	uint8_t bus_num = (addr >> 16) & 0xff;
	46	uint8_t devfn = (addr >> 8) & 0xff;
	47	return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
	48	}
	49
	50	static inline uint32_t pci_addr_to_config(uint32_t addr)
	51	{
	52	return addr & (PCI_CONFIG_SPACE_SIZE - 1);
	53	}
	54
ce195fb5	55	void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
766347cc	56	{
766347cc IY	57	PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
	58	uint32_t config_addr = pci_addr_to_config(addr);
	59
	60	if (!pci_dev)
	61	return;
	62
	63	PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRI32x" len=%d\n",
	64	__func__, pci_dev->name, config_addr, val, len);
	65	pci_dev->config_write(pci_dev, config_addr, val, len);
	66	}
	67
ce195fb5	68	uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
766347cc	69	{
766347cc IY	70	PCIDevice *pci_dev = pci_addr_to_dev(s, addr);
	71	uint32_t config_addr = pci_addr_to_config(addr);
	72	uint32_t val;
	73
4677d8ed	74	assert(len == 1 \|\| len == 2 \|\| len == 4);
766347cc	75	if (!pci_dev) {
4677d8ed	76	return ~0x0;
766347cc IY	77	}
766347cc IY	78
4677d8ed MT	79	val = pci_dev->config_read(pci_dev, config_addr, len);
	80	PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
	81	__func__, pci_dev->name, config_addr, val, len);
	82
766347cc IY	83	return val;
	84	}
	85
a455783b IY	86	static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
	87	uint32_t val)
	88	{
	89	PCIHostState *s = opaque;
	90
	91	#ifdef TARGET_WORDS_BIGENDIAN
	92	val = bswap32(val);
	93	#endif
	94	PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
	95	__func__, addr, val);
	96	s->config_reg = val;
	97	}
	98
	99	static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr)
	100	{
	101	PCIHostState *s = opaque;
	102	uint32_t val = s->config_reg;
	103
	104	#ifdef TARGET_WORDS_BIGENDIAN
	105	val = bswap32(val);
	106	#endif
	107	PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
	108	__func__, addr, val);
	109	return val;
	110	}
	111
	112	static CPUWriteMemoryFunc * const pci_host_config_write[] = {
	113	&pci_host_config_writel,
	114	&pci_host_config_writel,
	115	&pci_host_config_writel,
	116	};
	117
	118	static CPUReadMemoryFunc * const pci_host_config_read[] = {
	119	&pci_host_config_readl,
	120	&pci_host_config_readl,
	121	&pci_host_config_readl,
	122	};
	123
	124	int pci_host_config_register_io_memory(PCIHostState *s)
	125	{
	126	return cpu_register_io_memory(pci_host_config_read,
	127	pci_host_config_write, s);
	128	}
	129
	130	static void pci_host_config_writel_noswap(void *opaque,
	131	target_phys_addr_t addr,
	132	uint32_t val)
	133	{
	134	PCIHostState *s = opaque;
	135
	136	PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
	137	__func__, addr, val);
	138	s->config_reg = val;
	139	}
	140
	141	static uint32_t pci_host_config_readl_noswap(void *opaque,
	142	target_phys_addr_t addr)
	143	{
	144	PCIHostState *s = opaque;
	145	uint32_t val = s->config_reg;
	146
	147	PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
	148	__func__, addr, val);
	149	return val;
150	}
151
152	static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
153	&pci_host_config_writel_noswap,
154	&pci_host_config_writel_noswap,
155	&pci_host_config_writel_noswap,
156	};
157
158	static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
159	&pci_host_config_readl_noswap,
160	&pci_host_config_readl_noswap,
161	&pci_host_config_readl_noswap,
162	};
163
164	int pci_host_config_register_io_memory_noswap(PCIHostState *s)
165	{
166	return cpu_register_io_memory(pci_host_config_read_noswap,
167	pci_host_config_write_noswap, s);
168	}
169
170	static void pci_host_config_writel_ioport(void *opaque,
171	uint32_t addr, uint32_t val)
172	{
173	PCIHostState *s = opaque;
174
175	PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
176	s->config_reg = val;
177	}
178
179	static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
180	{
181	PCIHostState *s = opaque;
182	uint32_t val = s->config_reg;
183
184	PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
185	return val;
186	}
187
188	void pci_host_config_register_ioport(pio_addr_t ioport, PCIHostState *s)
189	{
190	register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
191	register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
192	}
193
4f5e19e6 IY	194	#define PCI_ADDR_T target_phys_addr_t
	195	#define PCI_HOST_SUFFIX _mmio
	196
	197	#include "pci_host_template.h"
	198
	199	static CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = {
	200	pci_host_data_writeb_mmio,
	201	pci_host_data_writew_mmio,
	202	pci_host_data_writel_mmio,
	203	};
	204
	205	static CPUReadMemoryFunc * const pci_host_data_read_mmio[] = {
	206	pci_host_data_readb_mmio,
	207	pci_host_data_readw_mmio,
	208	pci_host_data_readl_mmio,
	209	};
	210
	211	int pci_host_data_register_io_memory(PCIHostState *s)
	212	{
	213	return cpu_register_io_memory(pci_host_data_read_mmio,
	214	pci_host_data_write_mmio,
	215	s);
	216	}
	217
	218	#undef PCI_ADDR_T
	219	#undef PCI_HOST_SUFFIX
	220
	221	#define PCI_ADDR_T uint32_t
	222	#define PCI_HOST_SUFFIX _ioport
	223
	224	#include "pci_host_template.h"
	225
	226	void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
	227	{
	228	register_ioport_write(ioport, 4, 1, pci_host_data_writeb_ioport, s);
	229	register_ioport_write(ioport, 4, 2, pci_host_data_writew_ioport, s);
	230	register_ioport_write(ioport, 4, 4, pci_host_data_writel_ioport, s);
	231	register_ioport_read(ioport, 4, 1, pci_host_data_readb_ioport, s);
	232	register_ioport_read(ioport, 4, 2, pci_host_data_readw_ioport, s);
	233	register_ioport_read(ioport, 4, 4, pci_host_data_readl_ioport, s);
	234	}