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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
32 | * It does not implement boot blocs with reduced size | |
33 | * It does not implement software data protection as found in many real chips | |
34 | * It does not implement erase suspend/resume commands | |
35 | * It does not implement multiple sectors erase | |
36 | */ | |
37 | ||
87ecb68b PB |
38 | #include "hw.h" |
39 | #include "flash.h" | |
40 | #include "qemu-timer.h" | |
41 | #include "block.h" | |
cfe5f011 | 42 | #include "exec-memory.h" |
eb99c9a9 | 43 | #include "host-utils.h" |
29133e9a FB |
44 | |
45 | //#define PFLASH_DEBUG | |
46 | #ifdef PFLASH_DEBUG | |
001faf32 | 47 | #define DPRINTF(fmt, ...) \ |
29133e9a | 48 | do { \ |
001faf32 | 49 | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
29133e9a FB |
50 | } while (0) |
51 | #else | |
001faf32 | 52 | #define DPRINTF(fmt, ...) do { } while (0) |
29133e9a FB |
53 | #endif |
54 | ||
661bfc80 JK |
55 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
56 | ||
c227f099 | 57 | struct pflash_t { |
29133e9a | 58 | BlockDriverState *bs; |
c227f099 | 59 | target_phys_addr_t base; |
71db710f | 60 | uint32_t sector_len; |
4fbd24ba AZ |
61 | uint32_t chip_len; |
62 | int mappings; | |
29133e9a FB |
63 | int width; |
64 | int wcycle; /* if 0, the flash is read normally */ | |
65 | int bypass; | |
66 | int ro; | |
67 | uint8_t cmd; | |
68 | uint8_t status; | |
69 | uint16_t ident[4]; | |
6725070d | 70 | uint16_t unlock_addr[2]; |
29133e9a FB |
71 | uint8_t cfi_len; |
72 | uint8_t cfi_table[0x52]; | |
73 | QEMUTimer *timer; | |
cfe5f011 AK |
74 | /* The device replicates the flash memory across its memory space. Emulate |
75 | * that by having a container (.mem) filled with an array of aliases | |
76 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
77 | */ | |
78 | MemoryRegion mem; | |
79 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
80 | MemoryRegion orig_mem; | |
9c9bb6c8 | 81 | int rom_mode; |
661bfc80 | 82 | int read_counter; /* used for lazy switch-back to rom mode */ |
29133e9a FB |
83 | void *storage; |
84 | }; | |
85 | ||
cfe5f011 AK |
86 | /* |
87 | * Set up replicated mappings of the same region. | |
88 | */ | |
89 | static void pflash_setup_mappings(pflash_t *pfl) | |
c8a50e59 | 90 | { |
cfe5f011 AK |
91 | unsigned i; |
92 | target_phys_addr_t size = memory_region_size(&pfl->orig_mem); | |
93 | ||
94 | memory_region_init(&pfl->mem, "pflash", pfl->mappings * size); | |
95 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); | |
96 | for (i = 0; i < pfl->mappings; ++i) { | |
97 | memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", | |
98 | &pfl->orig_mem, 0, size); | |
99 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); | |
100 | } | |
101 | } | |
01e0451a | 102 | |
cfe5f011 AK |
103 | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
104 | { | |
105 | memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode); | |
bda254da | 106 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
107 | } |
108 | ||
29133e9a FB |
109 | static void pflash_timer (void *opaque) |
110 | { | |
c227f099 | 111 | pflash_t *pfl = opaque; |
29133e9a FB |
112 | |
113 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
114 | /* Reset flash */ | |
115 | pfl->status ^= 0x80; | |
116 | if (pfl->bypass) { | |
117 | pfl->wcycle = 2; | |
118 | } else { | |
4fbd24ba | 119 | pflash_register_memory(pfl, 1); |
29133e9a FB |
120 | pfl->wcycle = 0; |
121 | } | |
122 | pfl->cmd = 0; | |
123 | } | |
124 | ||
5f9fc5ad BS |
125 | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset, |
126 | int width, int be) | |
29133e9a | 127 | { |
f8be67ee | 128 | target_phys_addr_t boff; |
29133e9a FB |
129 | uint32_t ret; |
130 | uint8_t *p; | |
131 | ||
f8be67ee | 132 | DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset); |
29133e9a | 133 | ret = -1; |
661bfc80 JK |
134 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
135 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
136 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
137 | pflash_register_memory(pfl, 1); | |
0f459d16 | 138 | } |
4fbd24ba | 139 | offset &= pfl->chip_len - 1; |
29133e9a FB |
140 | boff = offset & 0xFF; |
141 | if (pfl->width == 2) | |
142 | boff = boff >> 1; | |
143 | else if (pfl->width == 4) | |
144 | boff = boff >> 2; | |
145 | switch (pfl->cmd) { | |
146 | default: | |
147 | /* This should never happen : reset state & treat it as a read*/ | |
148 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
149 | pfl->wcycle = 0; | |
150 | pfl->cmd = 0; | |
151 | case 0x80: | |
152 | /* We accept reads during second unlock sequence... */ | |
153 | case 0x00: | |
154 | flash_read: | |
155 | /* Flash area read */ | |
156 | p = pfl->storage; | |
157 | switch (width) { | |
158 | case 1: | |
159 | ret = p[offset]; | |
160 | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); | |
161 | break; | |
162 | case 2: | |
5f9fc5ad BS |
163 | if (be) { |
164 | ret = p[offset] << 8; | |
165 | ret |= p[offset + 1]; | |
166 | } else { | |
167 | ret = p[offset]; | |
168 | ret |= p[offset + 1] << 8; | |
169 | } | |
29133e9a FB |
170 | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); |
171 | break; | |
172 | case 4: | |
5f9fc5ad BS |
173 | if (be) { |
174 | ret = p[offset] << 24; | |
175 | ret |= p[offset + 1] << 16; | |
176 | ret |= p[offset + 2] << 8; | |
177 | ret |= p[offset + 3]; | |
178 | } else { | |
179 | ret = p[offset]; | |
180 | ret |= p[offset + 1] << 8; | |
181 | ret |= p[offset + 2] << 16; | |
182 | ret |= p[offset + 3] << 24; | |
183 | } | |
29133e9a FB |
184 | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); |
185 | break; | |
186 | } | |
187 | break; | |
188 | case 0x90: | |
189 | /* flash ID read */ | |
190 | switch (boff) { | |
191 | case 0x00: | |
192 | case 0x01: | |
193 | ret = pfl->ident[boff & 0x01]; | |
194 | break; | |
195 | case 0x02: | |
196 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
197 | break; | |
198 | case 0x0E: | |
199 | case 0x0F: | |
200 | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) | |
201 | goto flash_read; | |
202 | ret = pfl->ident[2 + (boff & 0x01)]; | |
203 | break; | |
204 | default: | |
205 | goto flash_read; | |
206 | } | |
b9055c3c | 207 | DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); |
29133e9a FB |
208 | break; |
209 | case 0xA0: | |
210 | case 0x10: | |
211 | case 0x30: | |
212 | /* Status register read */ | |
213 | ret = pfl->status; | |
214 | DPRINTF("%s: status %x\n", __func__, ret); | |
215 | /* Toggle bit 6 */ | |
216 | pfl->status ^= 0x40; | |
217 | break; | |
218 | case 0x98: | |
219 | /* CFI query mode */ | |
220 | if (boff > pfl->cfi_len) | |
221 | ret = 0; | |
222 | else | |
223 | ret = pfl->cfi_table[boff]; | |
224 | break; | |
225 | } | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
230 | /* update flash content on disk */ | |
c227f099 | 231 | static void pflash_update(pflash_t *pfl, int offset, |
29133e9a FB |
232 | int size) |
233 | { | |
234 | int offset_end; | |
235 | if (pfl->bs) { | |
236 | offset_end = offset + size; | |
237 | /* round to sectors */ | |
238 | offset = offset >> 9; | |
239 | offset_end = (offset_end + 511) >> 9; | |
5fafdf24 | 240 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), |
29133e9a FB |
241 | offset_end - offset); |
242 | } | |
243 | } | |
244 | ||
f8be67ee | 245 | static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, |
5f9fc5ad | 246 | uint32_t value, int width, int be) |
29133e9a | 247 | { |
f8be67ee | 248 | target_phys_addr_t boff; |
29133e9a FB |
249 | uint8_t *p; |
250 | uint8_t cmd; | |
251 | ||
95d1f3ed JM |
252 | cmd = value; |
253 | if (pfl->cmd != 0xA0 && cmd == 0xF0) { | |
254 | #if 0 | |
255 | DPRINTF("%s: flash reset asked (%02x %02x)\n", | |
256 | __func__, pfl->cmd, cmd); | |
257 | #endif | |
258 | goto reset_flash; | |
259 | } | |
f8be67ee | 260 | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__, |
95d1f3ed | 261 | offset, value, width, pfl->wcycle); |
4fbd24ba | 262 | offset &= pfl->chip_len - 1; |
3b46e624 | 263 | |
f8be67ee | 264 | DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, |
e96efcfc | 265 | offset, value, width); |
29133e9a FB |
266 | boff = offset & (pfl->sector_len - 1); |
267 | if (pfl->width == 2) | |
268 | boff = boff >> 1; | |
269 | else if (pfl->width == 4) | |
270 | boff = boff >> 2; | |
271 | switch (pfl->wcycle) { | |
272 | case 0: | |
9c9bb6c8 AZ |
273 | /* Set the device in I/O access mode if required */ |
274 | if (pfl->rom_mode) | |
275 | pflash_register_memory(pfl, 0); | |
661bfc80 | 276 | pfl->read_counter = 0; |
29133e9a FB |
277 | /* We're in read mode */ |
278 | check_unlock0: | |
279 | if (boff == 0x55 && cmd == 0x98) { | |
280 | enter_CFI_mode: | |
281 | /* Enter CFI query mode */ | |
282 | pfl->wcycle = 7; | |
283 | pfl->cmd = 0x98; | |
284 | return; | |
285 | } | |
6725070d | 286 | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
f8be67ee | 287 | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
6725070d | 288 | __func__, boff, cmd, pfl->unlock_addr[0]); |
29133e9a FB |
289 | goto reset_flash; |
290 | } | |
291 | DPRINTF("%s: unlock sequence started\n", __func__); | |
292 | break; | |
293 | case 1: | |
294 | /* We started an unlock sequence */ | |
295 | check_unlock1: | |
6725070d | 296 | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
f8be67ee | 297 | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 298 | boff, cmd); |
29133e9a FB |
299 | goto reset_flash; |
300 | } | |
301 | DPRINTF("%s: unlock sequence done\n", __func__); | |
302 | break; | |
303 | case 2: | |
304 | /* We finished an unlock sequence */ | |
6725070d | 305 | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
f8be67ee | 306 | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 307 | boff, cmd); |
29133e9a FB |
308 | goto reset_flash; |
309 | } | |
310 | switch (cmd) { | |
311 | case 0x20: | |
312 | pfl->bypass = 1; | |
313 | goto do_bypass; | |
314 | case 0x80: | |
315 | case 0x90: | |
316 | case 0xA0: | |
317 | pfl->cmd = cmd; | |
318 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
319 | break; | |
320 | default: | |
321 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
322 | goto reset_flash; | |
323 | } | |
324 | break; | |
325 | case 3: | |
326 | switch (pfl->cmd) { | |
327 | case 0x80: | |
328 | /* We need another unlock sequence */ | |
329 | goto check_unlock0; | |
330 | case 0xA0: | |
f8be67ee | 331 | DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", |
29133e9a FB |
332 | __func__, offset, value, width); |
333 | p = pfl->storage; | |
de8efe8f JJ |
334 | if (!pfl->ro) { |
335 | switch (width) { | |
336 | case 1: | |
5f9fc5ad | 337 | p[offset] &= value; |
de8efe8f JJ |
338 | pflash_update(pfl, offset, 1); |
339 | break; | |
340 | case 2: | |
341 | if (be) { | |
342 | p[offset] &= value >> 8; | |
343 | p[offset + 1] &= value; | |
344 | } else { | |
345 | p[offset] &= value; | |
346 | p[offset + 1] &= value >> 8; | |
347 | } | |
348 | pflash_update(pfl, offset, 2); | |
349 | break; | |
350 | case 4: | |
351 | if (be) { | |
352 | p[offset] &= value >> 24; | |
353 | p[offset + 1] &= value >> 16; | |
354 | p[offset + 2] &= value >> 8; | |
355 | p[offset + 3] &= value; | |
356 | } else { | |
357 | p[offset] &= value; | |
358 | p[offset + 1] &= value >> 8; | |
359 | p[offset + 2] &= value >> 16; | |
360 | p[offset + 3] &= value >> 24; | |
361 | } | |
362 | pflash_update(pfl, offset, 4); | |
363 | break; | |
5f9fc5ad | 364 | } |
29133e9a FB |
365 | } |
366 | pfl->status = 0x00 | ~(value & 0x80); | |
367 | /* Let's pretend write is immediate */ | |
368 | if (pfl->bypass) | |
369 | goto do_bypass; | |
370 | goto reset_flash; | |
371 | case 0x90: | |
372 | if (pfl->bypass && cmd == 0x00) { | |
373 | /* Unlock bypass reset */ | |
374 | goto reset_flash; | |
375 | } | |
376 | /* We can enter CFI query mode from autoselect mode */ | |
377 | if (boff == 0x55 && cmd == 0x98) | |
378 | goto enter_CFI_mode; | |
379 | /* No break here */ | |
380 | default: | |
381 | DPRINTF("%s: invalid write for command %02x\n", | |
382 | __func__, pfl->cmd); | |
383 | goto reset_flash; | |
384 | } | |
385 | case 4: | |
386 | switch (pfl->cmd) { | |
387 | case 0xA0: | |
a1c7273b | 388 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
389 | /* As we suppose write is immediate, this should never happen */ |
390 | return; | |
391 | case 0x80: | |
392 | goto check_unlock1; | |
393 | default: | |
394 | /* Should never happen */ | |
395 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
396 | __func__, pfl->cmd); | |
397 | goto reset_flash; | |
398 | } | |
399 | break; | |
400 | case 5: | |
401 | switch (cmd) { | |
402 | case 0x10: | |
6725070d | 403 | if (boff != pfl->unlock_addr[0]) { |
f8be67ee | 404 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
29133e9a FB |
405 | __func__, offset); |
406 | goto reset_flash; | |
407 | } | |
408 | /* Chip erase */ | |
409 | DPRINTF("%s: start chip erase\n", __func__); | |
de8efe8f JJ |
410 | if (!pfl->ro) { |
411 | memset(pfl->storage, 0xFF, pfl->chip_len); | |
412 | pflash_update(pfl, 0, pfl->chip_len); | |
413 | } | |
29133e9a | 414 | pfl->status = 0x00; |
29133e9a | 415 | /* Let's wait 5 seconds before chip erase is done */ |
5fafdf24 | 416 | qemu_mod_timer(pfl->timer, |
74475455 | 417 | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5)); |
29133e9a FB |
418 | break; |
419 | case 0x30: | |
420 | /* Sector erase */ | |
421 | p = pfl->storage; | |
422 | offset &= ~(pfl->sector_len - 1); | |
f8be67ee | 423 | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
e96efcfc | 424 | offset); |
de8efe8f JJ |
425 | if (!pfl->ro) { |
426 | memset(p + offset, 0xFF, pfl->sector_len); | |
427 | pflash_update(pfl, offset, pfl->sector_len); | |
428 | } | |
29133e9a FB |
429 | pfl->status = 0x00; |
430 | /* Let's wait 1/2 second before sector erase is done */ | |
5fafdf24 | 431 | qemu_mod_timer(pfl->timer, |
74475455 | 432 | qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2)); |
29133e9a FB |
433 | break; |
434 | default: | |
435 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
436 | goto reset_flash; | |
437 | } | |
438 | pfl->cmd = cmd; | |
439 | break; | |
440 | case 6: | |
441 | switch (pfl->cmd) { | |
442 | case 0x10: | |
443 | /* Ignore writes during chip erase */ | |
444 | return; | |
445 | case 0x30: | |
446 | /* Ignore writes during sector erase */ | |
447 | return; | |
448 | default: | |
449 | /* Should never happen */ | |
450 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
451 | __func__, pfl->cmd); | |
452 | goto reset_flash; | |
453 | } | |
454 | break; | |
455 | case 7: /* Special value for CFI queries */ | |
456 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); | |
457 | goto reset_flash; | |
458 | default: | |
459 | /* Should never happen */ | |
460 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
461 | goto reset_flash; | |
462 | } | |
463 | pfl->wcycle++; | |
464 | ||
465 | return; | |
466 | ||
467 | /* Reset flash */ | |
468 | reset_flash: | |
29133e9a FB |
469 | pfl->bypass = 0; |
470 | pfl->wcycle = 0; | |
471 | pfl->cmd = 0; | |
472 | return; | |
473 | ||
474 | do_bypass: | |
475 | pfl->wcycle = 2; | |
476 | pfl->cmd = 0; | |
29133e9a FB |
477 | } |
478 | ||
479 | ||
5f9fc5ad BS |
480 | static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr) |
481 | { | |
482 | return pflash_read(opaque, addr, 1, 1); | |
483 | } | |
484 | ||
485 | static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr) | |
486 | { | |
487 | return pflash_read(opaque, addr, 1, 0); | |
488 | } | |
489 | ||
490 | static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr) | |
491 | { | |
492 | pflash_t *pfl = opaque; | |
493 | ||
494 | return pflash_read(pfl, addr, 2, 1); | |
495 | } | |
496 | ||
497 | static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr) | |
498 | { | |
499 | pflash_t *pfl = opaque; | |
500 | ||
501 | return pflash_read(pfl, addr, 2, 0); | |
502 | } | |
503 | ||
504 | static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr) | |
29133e9a | 505 | { |
5f9fc5ad BS |
506 | pflash_t *pfl = opaque; |
507 | ||
508 | return pflash_read(pfl, addr, 4, 1); | |
29133e9a FB |
509 | } |
510 | ||
5f9fc5ad | 511 | static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr) |
29133e9a | 512 | { |
c227f099 | 513 | pflash_t *pfl = opaque; |
29133e9a | 514 | |
5f9fc5ad BS |
515 | return pflash_read(pfl, addr, 4, 0); |
516 | } | |
517 | ||
518 | static void pflash_writeb_be(void *opaque, target_phys_addr_t addr, | |
519 | uint32_t value) | |
520 | { | |
521 | pflash_write(opaque, addr, value, 1, 1); | |
29133e9a FB |
522 | } |
523 | ||
5f9fc5ad BS |
524 | static void pflash_writeb_le(void *opaque, target_phys_addr_t addr, |
525 | uint32_t value) | |
526 | { | |
527 | pflash_write(opaque, addr, value, 1, 0); | |
528 | } | |
529 | ||
530 | static void pflash_writew_be(void *opaque, target_phys_addr_t addr, | |
531 | uint32_t value) | |
29133e9a | 532 | { |
c227f099 | 533 | pflash_t *pfl = opaque; |
29133e9a | 534 | |
5f9fc5ad | 535 | pflash_write(pfl, addr, value, 2, 1); |
29133e9a FB |
536 | } |
537 | ||
5f9fc5ad BS |
538 | static void pflash_writew_le(void *opaque, target_phys_addr_t addr, |
539 | uint32_t value) | |
29133e9a | 540 | { |
5f9fc5ad BS |
541 | pflash_t *pfl = opaque; |
542 | ||
543 | pflash_write(pfl, addr, value, 2, 0); | |
29133e9a FB |
544 | } |
545 | ||
5f9fc5ad BS |
546 | static void pflash_writel_be(void *opaque, target_phys_addr_t addr, |
547 | uint32_t value) | |
29133e9a | 548 | { |
c227f099 | 549 | pflash_t *pfl = opaque; |
29133e9a | 550 | |
5f9fc5ad | 551 | pflash_write(pfl, addr, value, 4, 1); |
29133e9a FB |
552 | } |
553 | ||
5f9fc5ad BS |
554 | static void pflash_writel_le(void *opaque, target_phys_addr_t addr, |
555 | uint32_t value) | |
29133e9a | 556 | { |
c227f099 | 557 | pflash_t *pfl = opaque; |
29133e9a | 558 | |
5f9fc5ad | 559 | pflash_write(pfl, addr, value, 4, 0); |
29133e9a FB |
560 | } |
561 | ||
cfe5f011 AK |
562 | static const MemoryRegionOps pflash_cfi02_ops_be = { |
563 | .old_mmio = { | |
564 | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | |
565 | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | |
566 | }, | |
567 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5f9fc5ad BS |
568 | }; |
569 | ||
cfe5f011 AK |
570 | static const MemoryRegionOps pflash_cfi02_ops_le = { |
571 | .old_mmio = { | |
572 | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | |
573 | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | |
574 | }, | |
575 | .endianness = DEVICE_NATIVE_ENDIAN, | |
29133e9a FB |
576 | }; |
577 | ||
cfe5f011 AK |
578 | pflash_t *pflash_cfi02_register(target_phys_addr_t base, |
579 | DeviceState *qdev, const char *name, | |
580 | target_phys_addr_t size, | |
cf6d9118 | 581 | BlockDriverState *bs, uint32_t sector_len, |
4fbd24ba | 582 | int nb_blocs, int nb_mappings, int width, |
88eeee0a | 583 | uint16_t id0, uint16_t id1, |
6725070d | 584 | uint16_t id2, uint16_t id3, |
01e0451a AL |
585 | uint16_t unlock_addr0, uint16_t unlock_addr1, |
586 | int be) | |
29133e9a | 587 | { |
c227f099 | 588 | pflash_t *pfl; |
4fbd24ba | 589 | int32_t chip_len; |
d0e7605e | 590 | int ret; |
29133e9a | 591 | |
4fbd24ba | 592 | chip_len = sector_len * nb_blocs; |
29133e9a | 593 | /* XXX: to be fixed */ |
95d1f3ed | 594 | #if 0 |
29133e9a FB |
595 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
596 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
597 | return NULL; | |
95d1f3ed | 598 | #endif |
7267c094 | 599 | pfl = g_malloc0(sizeof(pflash_t)); |
cfe5f011 AK |
600 | memory_region_init_rom_device( |
601 | &pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl, | |
c5705a77 AK |
602 | name, size); |
603 | vmstate_register_ram(&pfl->orig_mem, qdev); | |
cfe5f011 | 604 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
4fbd24ba AZ |
605 | pfl->base = base; |
606 | pfl->chip_len = chip_len; | |
607 | pfl->mappings = nb_mappings; | |
29133e9a FB |
608 | pfl->bs = bs; |
609 | if (pfl->bs) { | |
610 | /* read the initial flash content */ | |
d0e7605e VK |
611 | ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
612 | if (ret < 0) { | |
7267c094 | 613 | g_free(pfl); |
d0e7605e VK |
614 | return NULL; |
615 | } | |
fa879d62 | 616 | bdrv_attach_dev_nofail(pfl->bs, pfl); |
29133e9a | 617 | } |
de8efe8f | 618 | |
cfe5f011 AK |
619 | pflash_setup_mappings(pfl); |
620 | pfl->rom_mode = 1; | |
621 | memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem); | |
de8efe8f JJ |
622 | |
623 | if (pfl->bs) { | |
624 | pfl->ro = bdrv_is_read_only(pfl->bs); | |
625 | } else { | |
626 | pfl->ro = 0; | |
627 | } | |
628 | ||
74475455 | 629 | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
29133e9a | 630 | pfl->sector_len = sector_len; |
29133e9a FB |
631 | pfl->width = width; |
632 | pfl->wcycle = 0; | |
633 | pfl->cmd = 0; | |
634 | pfl->status = 0; | |
635 | pfl->ident[0] = id0; | |
636 | pfl->ident[1] = id1; | |
637 | pfl->ident[2] = id2; | |
638 | pfl->ident[3] = id3; | |
6725070d AZ |
639 | pfl->unlock_addr[0] = unlock_addr0; |
640 | pfl->unlock_addr[1] = unlock_addr1; | |
29133e9a FB |
641 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
642 | pfl->cfi_len = 0x52; | |
643 | /* Standard "QRY" string */ | |
644 | pfl->cfi_table[0x10] = 'Q'; | |
645 | pfl->cfi_table[0x11] = 'R'; | |
646 | pfl->cfi_table[0x12] = 'Y'; | |
647 | /* Command set (AMD/Fujitsu) */ | |
648 | pfl->cfi_table[0x13] = 0x02; | |
649 | pfl->cfi_table[0x14] = 0x00; | |
78556820 EI |
650 | /* Primary extended table address */ |
651 | pfl->cfi_table[0x15] = 0x31; | |
29133e9a FB |
652 | pfl->cfi_table[0x16] = 0x00; |
653 | /* Alternate command set (none) */ | |
654 | pfl->cfi_table[0x17] = 0x00; | |
655 | pfl->cfi_table[0x18] = 0x00; | |
656 | /* Alternate extended table (none) */ | |
657 | pfl->cfi_table[0x19] = 0x00; | |
658 | pfl->cfi_table[0x1A] = 0x00; | |
659 | /* Vcc min */ | |
660 | pfl->cfi_table[0x1B] = 0x27; | |
661 | /* Vcc max */ | |
662 | pfl->cfi_table[0x1C] = 0x36; | |
663 | /* Vpp min (no Vpp pin) */ | |
664 | pfl->cfi_table[0x1D] = 0x00; | |
665 | /* Vpp max (no Vpp pin) */ | |
666 | pfl->cfi_table[0x1E] = 0x00; | |
667 | /* Reserved */ | |
668 | pfl->cfi_table[0x1F] = 0x07; | |
78556820 EI |
669 | /* Timeout for min size buffer write (NA) */ |
670 | pfl->cfi_table[0x20] = 0x00; | |
29133e9a FB |
671 | /* Typical timeout for block erase (512 ms) */ |
672 | pfl->cfi_table[0x21] = 0x09; | |
673 | /* Typical timeout for full chip erase (4096 ms) */ | |
674 | pfl->cfi_table[0x22] = 0x0C; | |
675 | /* Reserved */ | |
676 | pfl->cfi_table[0x23] = 0x01; | |
78556820 EI |
677 | /* Max timeout for buffer write (NA) */ |
678 | pfl->cfi_table[0x24] = 0x00; | |
29133e9a FB |
679 | /* Max timeout for block erase */ |
680 | pfl->cfi_table[0x25] = 0x0A; | |
681 | /* Max timeout for chip erase */ | |
682 | pfl->cfi_table[0x26] = 0x0D; | |
683 | /* Device size */ | |
78556820 | 684 | pfl->cfi_table[0x27] = ctz32(chip_len); |
29133e9a FB |
685 | /* Flash device interface (8 & 16 bits) */ |
686 | pfl->cfi_table[0x28] = 0x02; | |
687 | pfl->cfi_table[0x29] = 0x00; | |
688 | /* Max number of bytes in multi-bytes write */ | |
95d1f3ed JM |
689 | /* XXX: disable buffered write as it's not supported */ |
690 | // pfl->cfi_table[0x2A] = 0x05; | |
691 | pfl->cfi_table[0x2A] = 0x00; | |
29133e9a FB |
692 | pfl->cfi_table[0x2B] = 0x00; |
693 | /* Number of erase block regions (uniform) */ | |
694 | pfl->cfi_table[0x2C] = 0x01; | |
695 | /* Erase block region 1 */ | |
696 | pfl->cfi_table[0x2D] = nb_blocs - 1; | |
697 | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; | |
698 | pfl->cfi_table[0x2F] = sector_len >> 8; | |
699 | pfl->cfi_table[0x30] = sector_len >> 16; | |
700 | ||
78556820 EI |
701 | /* Extended */ |
702 | pfl->cfi_table[0x31] = 'P'; | |
703 | pfl->cfi_table[0x32] = 'R'; | |
704 | pfl->cfi_table[0x33] = 'I'; | |
705 | ||
706 | pfl->cfi_table[0x34] = '1'; | |
707 | pfl->cfi_table[0x35] = '0'; | |
708 | ||
709 | pfl->cfi_table[0x36] = 0x00; | |
710 | pfl->cfi_table[0x37] = 0x00; | |
711 | pfl->cfi_table[0x38] = 0x00; | |
712 | pfl->cfi_table[0x39] = 0x00; | |
713 | ||
714 | pfl->cfi_table[0x3a] = 0x00; | |
715 | ||
716 | pfl->cfi_table[0x3b] = 0x00; | |
717 | pfl->cfi_table[0x3c] = 0x00; | |
718 | ||
29133e9a FB |
719 | return pfl; |
720 | } |