[mirror_qemu.git] / hw / pflash_cfi02.c

/*
 *  CFI parallel flash with AMD command set emulation
 *
 *  Copyright (c) 2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*
 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
 * Supported commands/modes are:
 * - flash read
 * - flash write
 * - flash ID read
 * - sector erase
 * - chip erase
 * - unlock bypass command
 * - CFI queries
 *
 * It does not support flash interleaving.
 * It does not implement boot blocs with reduced size
 * It does not implement software data protection as found in many real chips
 * It does not implement erase suspend/resume commands
 * It does not implement multiple sectors erase
 */

#include "vl.h"

//#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG
#define DPRINTF(fmt, args...)                      \
do {                                               \
        printf("PFLASH: " fmt , ##args);           \
} while (0)
#else
#define DPRINTF(fmt, args...) do { } while (0)
#endif

struct pflash_t {
    BlockDriverState *bs;
    target_phys_addr_t base;
    uint32_t sector_len;
    uint32_t total_len;
    int width;
    int wcycle; /* if 0, the flash is read normally */
    int bypass;
    int ro;
    uint8_t cmd;
    uint8_t status;
    uint16_t ident[4];
    uint8_t cfi_len;
    uint8_t cfi_table[0x52];
    QEMUTimer *timer;
    ram_addr_t off;
    int fl_mem;
    void *storage;
};

static void pflash_timer (void *opaque)
{
    pflash_t *pfl = opaque;

    DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
    /* Reset flash */
    pfl->status ^= 0x80;
    if (pfl->bypass) {
        pfl->wcycle = 2;
    } else {
        cpu_register_physical_memory(pfl->base, pfl->total_len,
                                     pfl->off | IO_MEM_ROMD | pfl->fl_mem);
        pfl->wcycle = 0;
    }
    pfl->cmd = 0;
}

static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
{
    uint32_t boff;
    uint32_t ret;
    uint8_t *p;

    DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
    ret = -1;
    offset -= pfl->base;
    boff = offset & 0xFF;
    if (pfl->width == 2)
        boff = boff >> 1;
    else if (pfl->width == 4)
        boff = boff >> 2;
    switch (pfl->cmd) {
    default:
        /* This should never happen : reset state & treat it as a read*/
        DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
        pfl->wcycle = 0;
        pfl->cmd = 0;
    case 0x80:
        /* We accept reads during second unlock sequence... */
    case 0x00:
    flash_read:
        /* Flash area read */
        p = pfl->storage;
        switch (width) {
        case 1:
            ret = p[offset];
//            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
            break;
        case 2:
#if defined(TARGET_WORDS_BIGENDIAN)
            ret = p[offset] << 8;
            ret |= p[offset + 1];
#else
            ret = p[offset];
            ret |= p[offset + 1] << 8;
#endif
//            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
            break;
        case 4:
#if defined(TARGET_WORDS_BIGENDIAN)
            ret = p[offset] << 24;
            ret |= p[offset + 1] << 16;
            ret |= p[offset + 2] << 8;
            ret |= p[offset + 3];
#else
            ret = p[offset];
            ret |= p[offset + 1] << 8;
            ret |= p[offset + 2] << 16;
            ret |= p[offset + 3] << 24;
#endif
//            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
            break;
        }
        break;
    case 0x90:
        /* flash ID read */
        switch (boff) {
        case 0x00:
        case 0x01:
            ret = pfl->ident[boff & 0x01];
            break;
        case 0x02:
            ret = 0x00; /* Pretend all sectors are unprotected */
            break;
        case 0x0E:
        case 0x0F:
            if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
                goto flash_read;
            ret = pfl->ident[2 + (boff & 0x01)];
            break;
        default:
            goto flash_read;
        }
        DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
        break;
    case 0xA0:
    case 0x10:
    case 0x30:
        /* Status register read */
        ret = pfl->status;
        DPRINTF("%s: status %x\n", __func__, ret);
        /* Toggle bit 6 */
        pfl->status ^= 0x40;
        break;
    case 0x98:
        /* CFI query mode */
        if (boff > pfl->cfi_len)
            ret = 0;
        else
            ret = pfl->cfi_table[boff];
        break;
    }

    return ret;
}

/* update flash content on disk */
static void pflash_update(pflash_t *pfl, int offset,
                          int size)
{
    int offset_end;
    if (pfl->bs) {
        offset_end = offset + size;
        /* round to sectors */
        offset = offset >> 9;
        offset_end = (offset_end + 511) >> 9;
        bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
                   offset_end - offset);
    }
}

static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
                          int width)
{
    uint32_t boff;
    uint8_t *p;
    uint8_t cmd;

    /* WARNING: when the memory area is in ROMD mode, the offset is a
       ram offset, not a physical address */
    cmd = value;
    if (pfl->cmd != 0xA0 && cmd == 0xF0) {
#if 0
        DPRINTF("%s: flash reset asked (%02x %02x)\n",
                __func__, pfl->cmd, cmd);
#endif
        goto reset_flash;
    }
    DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
            offset, value, width, pfl->wcycle);
    if (pfl->wcycle == 0)
        offset -= (uint32_t)(long)pfl->storage;
    else
        offset -= pfl->base;
       
    DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
            offset, value, width);
    /* Set the device in I/O access mode */
    cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
    boff = offset & (pfl->sector_len - 1);
    if (pfl->width == 2)
        boff = boff >> 1;
    else if (pfl->width == 4)
        boff = boff >> 2;
    switch (pfl->wcycle) {
    case 0:
        /* We're in read mode */
    check_unlock0:
        if (boff == 0x55 && cmd == 0x98) {
        enter_CFI_mode:
            /* Enter CFI query mode */
            pfl->wcycle = 7;
            pfl->cmd = 0x98;
            return;
        }
        if (boff != 0x555 || cmd != 0xAA) {
            DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
                    __func__, boff, cmd, 0x555);
            goto reset_flash;
        }
        DPRINTF("%s: unlock sequence started\n", __func__);
        break;
    case 1:
        /* We started an unlock sequence */
    check_unlock1:
        if (boff != 0x2AA || cmd != 0x55) {
            DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
                    boff, cmd);
            goto reset_flash;
        }
        DPRINTF("%s: unlock sequence done\n", __func__);
        break;
    case 2:
        /* We finished an unlock sequence */
        if (!pfl->bypass && boff != 0x555) {
            DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
                    boff, cmd);
            goto reset_flash;
        }
        switch (cmd) {
        case 0x20:
            pfl->bypass = 1;
            goto do_bypass;
        case 0x80:
        case 0x90:
        case 0xA0:
            pfl->cmd = cmd;
            DPRINTF("%s: starting command %02x\n", __func__, cmd);
            break;
        default:
            DPRINTF("%s: unknown command %02x\n", __func__, cmd);
            goto reset_flash;
        }
        break;
    case 3:
        switch (pfl->cmd) {
        case 0x80:
            /* We need another unlock sequence */
            goto check_unlock0;
        case 0xA0:
            DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
                    __func__, offset, value, width);
            p = pfl->storage;
            switch (width) {
            case 1:
                p[offset] &= value;
                pflash_update(pfl, offset, 1);
                break;
            case 2:
#if defined(TARGET_WORDS_BIGENDIAN)
                p[offset] &= value >> 8;
                p[offset + 1] &= value;
#else
                p[offset] &= value;
                p[offset + 1] &= value >> 8;
#endif
                pflash_update(pfl, offset, 2);
                break;
            case 4:
#if defined(TARGET_WORDS_BIGENDIAN)
                p[offset] &= value >> 24;
                p[offset + 1] &= value >> 16;
                p[offset + 2] &= value >> 8;
                p[offset + 3] &= value;
#else
                p[offset] &= value;
                p[offset + 1] &= value >> 8;
                p[offset + 2] &= value >> 16;
                p[offset + 3] &= value >> 24;
#endif
                pflash_update(pfl, offset, 4);
                break;
            }
            pfl->status = 0x00 | ~(value & 0x80);
            /* Let's pretend write is immediate */
            if (pfl->bypass)
                goto do_bypass;
            goto reset_flash;
        case 0x90:
            if (pfl->bypass && cmd == 0x00) {
                /* Unlock bypass reset */
                goto reset_flash;
            }
            /* We can enter CFI query mode from autoselect mode */
            if (boff == 0x55 && cmd == 0x98)
                goto enter_CFI_mode;
            /* No break here */
        default:
            DPRINTF("%s: invalid write for command %02x\n",
                    __func__, pfl->cmd);
            goto reset_flash;
        }
    case 4:
        switch (pfl->cmd) {
        case 0xA0:
            /* Ignore writes while flash data write is occuring */
            /* As we suppose write is immediate, this should never happen */
            return;
        case 0x80:
            goto check_unlock1;
        default:
            /* Should never happen */
            DPRINTF("%s: invalid command state %02x (wc 4)\n",
                    __func__, pfl->cmd);
            goto reset_flash;
        }
        break;
    case 5:
        switch (cmd) {
        case 0x10:
            if (boff != 0x555) {
                DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
                        __func__, offset);
                goto reset_flash;
            }
            /* Chip erase */
            DPRINTF("%s: start chip erase\n", __func__);
            memset(pfl->storage, 0xFF, pfl->total_len);
            pfl->status = 0x00;
            pflash_update(pfl, 0, pfl->total_len);
            /* Let's wait 5 seconds before chip erase is done */
            qemu_mod_timer(pfl->timer,
                           qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
            break;
        case 0x30:
            /* Sector erase */
            p = pfl->storage;
            offset &= ~(pfl->sector_len - 1);
            DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
                    offset);
            memset(p + offset, 0xFF, pfl->sector_len);
            pflash_update(pfl, offset, pfl->sector_len);
            pfl->status = 0x00;
            /* Let's wait 1/2 second before sector erase is done */
            qemu_mod_timer(pfl->timer,
                           qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
            break;
        default:
            DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
            goto reset_flash;
        }
        pfl->cmd = cmd;
        break;
    case 6:
        switch (pfl->cmd) {
        case 0x10:
            /* Ignore writes during chip erase */
            return;
        case 0x30:
            /* Ignore writes during sector erase */
            return;
        default:
            /* Should never happen */
            DPRINTF("%s: invalid command state %02x (wc 6)\n",
                    __func__, pfl->cmd);
            goto reset_flash;
        }
        break;
    case 7: /* Special value for CFI queries */
        DPRINTF("%s: invalid write in CFI query mode\n", __func__);
        goto reset_flash;
    default:
        /* Should never happen */
        DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
        goto reset_flash;
    }
    pfl->wcycle++;

    return;

    /* Reset flash */
 reset_flash:
    cpu_register_physical_memory(pfl->base, pfl->total_len,
                                 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
    pfl->bypass = 0;
    pfl->wcycle = 0;
    pfl->cmd = 0;
    return;

 do_bypass:
    pfl->wcycle = 2;
    pfl->cmd = 0;
    return;
}


static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
{
    return pflash_read(opaque, addr, 1);
}

static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
{
    pflash_t *pfl = opaque;

    return pflash_read(pfl, addr, 2);
}

static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
{
    pflash_t *pfl = opaque;

    return pflash_read(pfl, addr, 4);
}

static void pflash_writeb (void *opaque, target_phys_addr_t addr,
                           uint32_t value)
{
    pflash_write(opaque, addr, value, 1);
}

static void pflash_writew (void *opaque, target_phys_addr_t addr,
                           uint32_t value)
{
    pflash_t *pfl = opaque;

    pflash_write(pfl, addr, value, 2);
}

static void pflash_writel (void *opaque, target_phys_addr_t addr,
                           uint32_t value)
{
    pflash_t *pfl = opaque;

    pflash_write(pfl, addr, value, 4);
}

static CPUWriteMemoryFunc *pflash_write_ops[] = {
    &pflash_writeb,
    &pflash_writew,
    &pflash_writel,
};

static CPUReadMemoryFunc *pflash_read_ops[] = {
    &pflash_readb,
    &pflash_readw,
    &pflash_readl,
};

/* Count trailing zeroes of a 32 bits quantity */
static int ctz32 (uint32_t n)
{
    int ret;

    ret = 0;
    if (!(n & 0xFFFF)) {
        ret += 16;
        n = n >> 16;
    }
    if (!(n & 0xFF)) {
        ret += 8;
        n = n >> 8;
    }
    if (!(n & 0xF)) {
        ret += 4;
        n = n >> 4;
    }
    if (!(n & 0x3)) {
        ret += 2;
        n = n >> 2;
    }
    if (!(n & 0x1)) {
        ret++;
        n = n >> 1;
    }
#if 0 /* This is not necessary as n is never 0 */
    if (!n)
        ret++;
#endif

    return ret;
}

pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
                           BlockDriverState *bs,
                           uint32_t sector_len, int nb_blocs, int width,
                           uint16_t id0, uint16_t id1,
                           uint16_t id2, uint16_t id3)
{
    pflash_t *pfl;
    int32_t total_len;

    total_len = sector_len * nb_blocs;
    /* XXX: to be fixed */
#if 0
    if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
        total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
        return NULL;
#endif
    pfl = qemu_mallocz(sizeof(pflash_t));
    if (pfl == NULL)
        return NULL;
    pfl->storage = phys_ram_base + off;
    pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
                                         pfl);
    pfl->off = off;
    cpu_register_physical_memory(base, total_len,
                                 off | pfl->fl_mem | IO_MEM_ROMD);
    pfl->bs = bs;
    if (pfl->bs) {
        /* read the initial flash content */
        bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
    }
#if 0 /* XXX: there should be a bit to set up read-only,
       *      the same way the hardware does (with WP pin).
       */
    pfl->ro = 1;
#else
    pfl->ro = 0;
#endif
    pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
    pfl->base = base;
    pfl->sector_len = sector_len;
    pfl->total_len = total_len;
    pfl->width = width;
    pfl->wcycle = 0;
    pfl->cmd = 0;
    pfl->status = 0;
    pfl->ident[0] = id0;
    pfl->ident[1] = id1;
    pfl->ident[2] = id2;
    pfl->ident[3] = id3;
    /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
    pfl->cfi_len = 0x52;
    /* Standard "QRY" string */
    pfl->cfi_table[0x10] = 'Q';
    pfl->cfi_table[0x11] = 'R';
    pfl->cfi_table[0x12] = 'Y';
    /* Command set (AMD/Fujitsu) */
    pfl->cfi_table[0x13] = 0x02;
    pfl->cfi_table[0x14] = 0x00;
    /* Primary extended table address (none) */
    pfl->cfi_table[0x15] = 0x00;
    pfl->cfi_table[0x16] = 0x00;
    /* Alternate command set (none) */
    pfl->cfi_table[0x17] = 0x00;
    pfl->cfi_table[0x18] = 0x00;
    /* Alternate extended table (none) */
    pfl->cfi_table[0x19] = 0x00;
    pfl->cfi_table[0x1A] = 0x00;
    /* Vcc min */
    pfl->cfi_table[0x1B] = 0x27;
    /* Vcc max */
    pfl->cfi_table[0x1C] = 0x36;
    /* Vpp min (no Vpp pin) */
    pfl->cfi_table[0x1D] = 0x00;
    /* Vpp max (no Vpp pin) */
    pfl->cfi_table[0x1E] = 0x00;
    /* Reserved */
    pfl->cfi_table[0x1F] = 0x07;
Commit	Line	Data
29133e9a FB	1	/*
29133e9a FB	2	* CFI parallel flash with AMD command set emulation
5fafdf24	3	*
29133e9a FB	4	* Copyright (c) 2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	/*
	22	* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
	23	* Supported commands/modes are:
	24	* - flash read
	25	* - flash write
	26	* - flash ID read
	27	* - sector erase
	28	* - chip erase
	29	* - unlock bypass command
	30	* - CFI queries
	31	*
	32	* It does not support flash interleaving.
	33	* It does not implement boot blocs with reduced size
	34	* It does not implement software data protection as found in many real chips
	35	* It does not implement erase suspend/resume commands
	36	* It does not implement multiple sectors erase
	37	*/
	38
	39	#include "vl.h"
	40
	41	//#define PFLASH_DEBUG
	42	#ifdef PFLASH_DEBUG
	43	#define DPRINTF(fmt, args...) \
	44	do { \
29133e9a FB	45	printf("PFLASH: " fmt , ##args); \
	46	} while (0)
	47	#else
	48	#define DPRINTF(fmt, args...) do { } while (0)
	49	#endif
	50
	51	struct pflash_t {
	52	BlockDriverState *bs;
71db710f BS	53	target_phys_addr_t base;
	54	uint32_t sector_len;
	55	uint32_t total_len;
29133e9a FB	56	int width;
	57	int wcycle; /* if 0, the flash is read normally */
	58	int bypass;
	59	int ro;
	60	uint8_t cmd;
	61	uint8_t status;
	62	uint16_t ident[4];
	63	uint8_t cfi_len;
	64	uint8_t cfi_table[0x52];
	65	QEMUTimer *timer;
	66	ram_addr_t off;
	67	int fl_mem;
	68	void *storage;
	69	};
	70
	71	static void pflash_timer (void *opaque)
	72	{
	73	pflash_t *pfl = opaque;
	74
	75	DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
	76	/* Reset flash */
	77	pfl->status ^= 0x80;
	78	if (pfl->bypass) {
	79	pfl->wcycle = 2;
	80	} else {
	81	cpu_register_physical_memory(pfl->base, pfl->total_len,
	82	pfl->off \| IO_MEM_ROMD \| pfl->fl_mem);
	83	pfl->wcycle = 0;
	84	}
	85	pfl->cmd = 0;
	86	}
	87
71db710f	88	static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
29133e9a	89	{
71db710f	90	uint32_t boff;
29133e9a FB	91	uint32_t ret;
	92	uint8_t *p;
	93
e96efcfc	94	DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
29133e9a FB	95	ret = -1;
	96	offset -= pfl->base;
	97	boff = offset & 0xFF;
	98	if (pfl->width == 2)
	99	boff = boff >> 1;
	100	else if (pfl->width == 4)
	101	boff = boff >> 2;
	102	switch (pfl->cmd) {
	103	default:
	104	/* This should never happen : reset state & treat it as a read*/
	105	DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
	106	pfl->wcycle = 0;
	107	pfl->cmd = 0;
	108	case 0x80:
	109	/* We accept reads during second unlock sequence... */
	110	case 0x00:
	111	flash_read:
	112	/* Flash area read */
	113	p = pfl->storage;
	114	switch (width) {
	115	case 1:
	116	ret = p[offset];
	117	// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
	118	break;
	119	case 2:
	120	#if defined(TARGET_WORDS_BIGENDIAN)
	121	ret = p[offset] << 8;
	122	ret \|= p[offset + 1];
	123	#else
	124	ret = p[offset];
	125	ret \|= p[offset + 1] << 8;
	126	#endif
	127	// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
	128	break;
	129	case 4:
	130	#if defined(TARGET_WORDS_BIGENDIAN)
	131	ret = p[offset] << 24;
	132	ret \|= p[offset + 1] << 16;
	133	ret \|= p[offset + 2] << 8;
	134	ret \|= p[offset + 3];
	135	#else
	136	ret = p[offset];
	137	ret \|= p[offset + 1] << 8;
29133e9a FB	138	ret \|= p[offset + 2] << 16;
	139	ret \|= p[offset + 3] << 24;
	140	#endif
	141	// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
	142	break;
	143	}
	144	break;
	145	case 0x90:
	146	/* flash ID read */
	147	switch (boff) {
	148	case 0x00:
	149	case 0x01:
	150	ret = pfl->ident[boff & 0x01];
	151	break;
	152	case 0x02:
	153	ret = 0x00; /* Pretend all sectors are unprotected */
	154	break;
	155	case 0x0E:
	156	case 0x0F:
	157	if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
	158	goto flash_read;
	159	ret = pfl->ident[2 + (boff & 0x01)];
	160	break;
	161	default:
	162	goto flash_read;
	163	}
e96efcfc	164	DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
29133e9a FB	165	break;
	166	case 0xA0:
	167	case 0x10:
	168	case 0x30:
	169	/* Status register read */
	170	ret = pfl->status;
	171	DPRINTF("%s: status %x\n", __func__, ret);
	172	/* Toggle bit 6 */
	173	pfl->status ^= 0x40;
	174	break;
	175	case 0x98:
	176	/* CFI query mode */
	177	if (boff > pfl->cfi_len)
	178	ret = 0;
	179	else
	180	ret = pfl->cfi_table[boff];
	181	break;
	182	}
	183
	184	return ret;
	185	}
	186
	187	/* update flash content on disk */
5fafdf24	188	static void pflash_update(pflash_t *pfl, int offset,
29133e9a FB	189	int size)
	190	{
	191	int offset_end;
	192	if (pfl->bs) {
	193	offset_end = offset + size;
	194	/* round to sectors */
	195	offset = offset >> 9;
	196	offset_end = (offset_end + 511) >> 9;
5fafdf24	197	bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
29133e9a FB	198	offset_end - offset);
	199	}
	200	}
	201
71db710f	202	static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
29133e9a FB	203	int width)
29133e9a FB	204	{
71db710f	205	uint32_t boff;
29133e9a FB	206	uint8_t *p;
	207	uint8_t cmd;
	208
	209	/* WARNING: when the memory area is in ROMD mode, the offset is a
	210	ram offset, not a physical address */
95d1f3ed JM	211	cmd = value;
	212	if (pfl->cmd != 0xA0 && cmd == 0xF0) {
	213	#if 0
	214	DPRINTF("%s: flash reset asked (%02x %02x)\n",
	215	__func__, pfl->cmd, cmd);
	216	#endif
	217	goto reset_flash;
	218	}
	219	DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
	220	offset, value, width, pfl->wcycle);
29133e9a	221	if (pfl->wcycle == 0)
71db710f	222	offset -= (uint32_t)(long)pfl->storage;
29133e9a FB	223	else
29133e9a FB	224	offset -= pfl->base;
5fafdf24	225
e96efcfc JM	226	DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
e96efcfc JM	227	offset, value, width);
29133e9a FB	228	/* Set the device in I/O access mode */
	229	cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
	230	boff = offset & (pfl->sector_len - 1);
	231	if (pfl->width == 2)
	232	boff = boff >> 1;
	233	else if (pfl->width == 4)
	234	boff = boff >> 2;
	235	switch (pfl->wcycle) {
	236	case 0:
	237	/* We're in read mode */
	238	check_unlock0:
	239	if (boff == 0x55 && cmd == 0x98) {
	240	enter_CFI_mode:
	241	/* Enter CFI query mode */
	242	pfl->wcycle = 7;
	243	pfl->cmd = 0x98;
	244	return;
	245	}
	246	if (boff != 0x555 \|\| cmd != 0xAA) {
e96efcfc	247	DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
29133e9a FB	248	__func__, boff, cmd, 0x555);
	249	goto reset_flash;
	250	}
	251	DPRINTF("%s: unlock sequence started\n", __func__);
	252	break;
	253	case 1:
	254	/* We started an unlock sequence */
	255	check_unlock1:
	256	if (boff != 0x2AA \|\| cmd != 0x55) {
e96efcfc JM	257	DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
e96efcfc JM	258	boff, cmd);
29133e9a FB	259	goto reset_flash;
	260	}
	261	DPRINTF("%s: unlock sequence done\n", __func__);
	262	break;
	263	case 2:
	264	/* We finished an unlock sequence */
	265	if (!pfl->bypass && boff != 0x555) {
e96efcfc JM	266	DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
e96efcfc JM	267	boff, cmd);
29133e9a FB	268	goto reset_flash;
	269	}
	270	switch (cmd) {
	271	case 0x20:
	272	pfl->bypass = 1;
	273	goto do_bypass;
	274	case 0x80:
	275	case 0x90:
	276	case 0xA0:
	277	pfl->cmd = cmd;
	278	DPRINTF("%s: starting command %02x\n", __func__, cmd);
	279	break;
	280	default:
	281	DPRINTF("%s: unknown command %02x\n", __func__, cmd);
	282	goto reset_flash;
	283	}
	284	break;
	285	case 3:
	286	switch (pfl->cmd) {
	287	case 0x80:
	288	/* We need another unlock sequence */
	289	goto check_unlock0;
	290	case 0xA0:
e96efcfc	291	DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
29133e9a FB	292	__func__, offset, value, width);
	293	p = pfl->storage;
	294	switch (width) {
	295	case 1:
	296	p[offset] &= value;
	297	pflash_update(pfl, offset, 1);
	298	break;
	299	case 2:
	300	#if defined(TARGET_WORDS_BIGENDIAN)
	301	p[offset] &= value >> 8;
	302	p[offset + 1] &= value;
	303	#else
	304	p[offset] &= value;
	305	p[offset + 1] &= value >> 8;
	306	#endif
	307	pflash_update(pfl, offset, 2);
	308	break;
	309	case 4:
	310	#if defined(TARGET_WORDS_BIGENDIAN)
	311	p[offset] &= value >> 24;
	312	p[offset + 1] &= value >> 16;
	313	p[offset + 2] &= value >> 8;
	314	p[offset + 3] &= value;
	315	#else
	316	p[offset] &= value;
	317	p[offset + 1] &= value >> 8;
	318	p[offset + 2] &= value >> 16;
	319	p[offset + 3] &= value >> 24;
	320	#endif
	321	pflash_update(pfl, offset, 4);
	322	break;
	323	}
	324	pfl->status = 0x00 \| ~(value & 0x80);
	325	/* Let's pretend write is immediate */
	326	if (pfl->bypass)
	327	goto do_bypass;
	328	goto reset_flash;
	329	case 0x90:
	330	if (pfl->bypass && cmd == 0x00) {
	331	/* Unlock bypass reset */
	332	goto reset_flash;
	333	}
	334	/* We can enter CFI query mode from autoselect mode */
	335	if (boff == 0x55 && cmd == 0x98)
	336	goto enter_CFI_mode;
	337	/* No break here */
	338	default:
	339	DPRINTF("%s: invalid write for command %02x\n",
	340	__func__, pfl->cmd);
	341	goto reset_flash;
	342	}
	343	case 4:
	344	switch (pfl->cmd) {
	345	case 0xA0:
	346	/* Ignore writes while flash data write is occuring */
	347	/* As we suppose write is immediate, this should never happen */
	348	return;
	349	case 0x80:
	350	goto check_unlock1;
	351	default:
	352	/* Should never happen */
	353	DPRINTF("%s: invalid command state %02x (wc 4)\n",
	354	__func__, pfl->cmd);
	355	goto reset_flash;
356	}
357	break;
358	case 5:
359	switch (cmd) {
360	case 0x10:
361	if (boff != 0x555) {
e96efcfc	362	DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
29133e9a FB	363	__func__, offset);
	364	goto reset_flash;
	365	}
	366	/* Chip erase */
	367	DPRINTF("%s: start chip erase\n", __func__);
	368	memset(pfl->storage, 0xFF, pfl->total_len);
	369	pfl->status = 0x00;
	370	pflash_update(pfl, 0, pfl->total_len);
	371	/* Let's wait 5 seconds before chip erase is done */
5fafdf24	372	qemu_mod_timer(pfl->timer,
29133e9a FB	373	qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
	374	break;
	375	case 0x30:
	376	/* Sector erase */
	377	p = pfl->storage;
	378	offset &= ~(pfl->sector_len - 1);
e96efcfc JM	379	DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
e96efcfc JM	380	offset);
29133e9a FB	381	memset(p + offset, 0xFF, pfl->sector_len);
	382	pflash_update(pfl, offset, pfl->sector_len);
	383	pfl->status = 0x00;
	384	/* Let's wait 1/2 second before sector erase is done */
5fafdf24	385	qemu_mod_timer(pfl->timer,
29133e9a FB	386	qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
	387	break;
	388	default:
	389	DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
	390	goto reset_flash;
	391	}
	392	pfl->cmd = cmd;
	393	break;
	394	case 6:
	395	switch (pfl->cmd) {
	396	case 0x10:
	397	/* Ignore writes during chip erase */
	398	return;
	399	case 0x30:
	400	/* Ignore writes during sector erase */
	401	return;
	402	default:
	403	/* Should never happen */
	404	DPRINTF("%s: invalid command state %02x (wc 6)\n",
	405	__func__, pfl->cmd);
	406	goto reset_flash;
	407	}
	408	break;
	409	case 7: /* Special value for CFI queries */
	410	DPRINTF("%s: invalid write in CFI query mode\n", __func__);
	411	goto reset_flash;
	412	default:
	413	/* Should never happen */
	414	DPRINTF("%s: invalid write state (wc 7)\n", __func__);
	415	goto reset_flash;
	416	}
	417	pfl->wcycle++;
	418
	419	return;
	420
	421	/* Reset flash */
	422	reset_flash:
95d1f3ed JM	423	cpu_register_physical_memory(pfl->base, pfl->total_len,
95d1f3ed JM	424	pfl->off \| IO_MEM_ROMD \| pfl->fl_mem);
29133e9a FB	425	pfl->bypass = 0;
	426	pfl->wcycle = 0;
	427	pfl->cmd = 0;
	428	return;
	429
	430	do_bypass:
	431	pfl->wcycle = 2;
	432	pfl->cmd = 0;
	433	return;
	434	}
	435
	436
	437	static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
	438	{
	439	return pflash_read(opaque, addr, 1);
	440	}
	441
	442	static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
	443	{
	444	pflash_t *pfl = opaque;
	445
	446	return pflash_read(pfl, addr, 2);
	447	}
	448
	449	static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
	450	{
	451	pflash_t *pfl = opaque;
	452
	453	return pflash_read(pfl, addr, 4);
	454	}
	455
	456	static void pflash_writeb (void *opaque, target_phys_addr_t addr,
	457	uint32_t value)
	458	{
	459	pflash_write(opaque, addr, value, 1);
	460	}
	461
	462	static void pflash_writew (void *opaque, target_phys_addr_t addr,
	463	uint32_t value)
	464	{
	465	pflash_t *pfl = opaque;
	466
	467	pflash_write(pfl, addr, value, 2);
	468	}
	469
	470	static void pflash_writel (void *opaque, target_phys_addr_t addr,
	471	uint32_t value)
	472	{
	473	pflash_t *pfl = opaque;
	474
	475	pflash_write(pfl, addr, value, 4);
	476	}
	477
	478	static CPUWriteMemoryFunc *pflash_write_ops[] = {
	479	&pflash_writeb,
	480	&pflash_writew,
	481	&pflash_writel,
	482	};
	483
	484	static CPUReadMemoryFunc *pflash_read_ops[] = {
	485	&pflash_readb,
	486	&pflash_readw,
	487	&pflash_readl,
	488	};
489
490	/* Count trailing zeroes of a 32 bits quantity */
491	static int ctz32 (uint32_t n)
492	{
493	int ret;
494
495	ret = 0;
496	if (!(n & 0xFFFF)) {
497	ret += 16;
498	n = n >> 16;
499	}
500	if (!(n & 0xFF)) {
501	ret += 8;
502	n = n >> 8;
503	}
504	if (!(n & 0xF)) {
505	ret += 4;
506	n = n >> 4;
507	}
508	if (!(n & 0x3)) {
509	ret += 2;
510	n = n >> 2;
511	}
512	if (!(n & 0x1)) {
513	ret++;
514	n = n >> 1;
515	}
516	#if 0 /* This is not necessary as n is never 0 */
517	if (!n)
518	ret++;
519	#endif
520
521	return ret;
522	}
523
71db710f	524	pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
29133e9a	525	BlockDriverState *bs,
71db710f	526	uint32_t sector_len, int nb_blocs, int width,
5fafdf24	527	uint16_t id0, uint16_t id1,
29133e9a FB	528	uint16_t id2, uint16_t id3)
	529	{
	530	pflash_t *pfl;
71db710f	531	int32_t total_len;
29133e9a FB	532
	533	total_len = sector_len * nb_blocs;
	534	/* XXX: to be fixed */
95d1f3ed	535	#if 0
29133e9a FB	536	if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
	537	total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
	538	return NULL;
95d1f3ed	539	#endif
29133e9a FB	540	pfl = qemu_mallocz(sizeof(pflash_t));
	541	if (pfl == NULL)
	542	return NULL;
	543	pfl->storage = phys_ram_base + off;
95d1f3ed JM	544	pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
95d1f3ed JM	545	pfl);
29133e9a FB	546	pfl->off = off;
	547	cpu_register_physical_memory(base, total_len,
	548	off \| pfl->fl_mem \| IO_MEM_ROMD);
	549	pfl->bs = bs;
	550	if (pfl->bs) {
	551	/* read the initial flash content */
	552	bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
	553	}
	554	#if 0 /* XXX: there should be a bit to set up read-only,
	555	* the same way the hardware does (with WP pin).
	556	*/
	557	pfl->ro = 1;
	558	#else
	559	pfl->ro = 0;
	560	#endif
	561	pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
	562	pfl->base = base;
	563	pfl->sector_len = sector_len;
	564	pfl->total_len = total_len;
	565	pfl->width = width;
	566	pfl->wcycle = 0;
	567	pfl->cmd = 0;
	568	pfl->status = 0;
	569	pfl->ident[0] = id0;
	570	pfl->ident[1] = id1;
	571	pfl->ident[2] = id2;
	572	pfl->ident[3] = id3;
	573	/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
	574	pfl->cfi_len = 0x52;
	575	/* Standard "QRY" string */
	576	pfl->cfi_table[0x10] = 'Q';
	577	pfl->cfi_table[0x11] = 'R';
	578	pfl->cfi_table[0x12] = 'Y';
	579	/* Command set (AMD/Fujitsu) */
	580	pfl->cfi_table[0x13] = 0x02;
	581	pfl->cfi_table[0x14] = 0x00;
	582	/* Primary extended table address (none) */
	583	pfl->cfi_table[0x15] = 0x00;
	584	pfl->cfi_table[0x16] = 0x00;
	585	/* Alternate command set (none) */
	586	pfl->cfi_table[0x17] = 0x00;
	587	pfl->cfi_table[0x18] = 0x00;
	588	/* Alternate extended table (none) */
	589	pfl->cfi_table[0x19] = 0x00;
	590	pfl->cfi_table[0x1A] = 0x00;
	591	/* Vcc min */
	592	pfl->cfi_table[0x1B] = 0x27;
	593	/* Vcc max */
	594	pfl->cfi_table[0x1C] = 0x36;
	595	/* Vpp min (no Vpp pin) */
	596	pfl->cfi_table[0x1D] = 0x00;
	597	/* Vpp max (no Vpp pin) */
	598	pfl->cfi_table[0x1E] = 0x00;
	599	/* Reserved */
	600	pfl->cfi_table[0x1F] = 0x07;
	601