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502a5395 PB |
1 | /* |
2 | * QEMU i440FX/PIIX3 PCI Bridge Emulation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "pc.h" | |
27 | #include "pci.h" | |
28 | ||
502a5395 PB |
29 | typedef uint32_t pci_addr_t; |
30 | #include "pci_host.h" | |
31 | ||
32 | typedef PCIHostState I440FXState; | |
33 | ||
34 | static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) | |
35 | { | |
36 | I440FXState *s = opaque; | |
37 | s->config_reg = val; | |
38 | } | |
39 | ||
40 | static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) | |
41 | { | |
42 | I440FXState *s = opaque; | |
43 | return s->config_reg; | |
44 | } | |
45 | ||
d537cf6c | 46 | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level); |
d2b59317 PB |
47 | |
48 | /* return the global irq number corresponding to a given device irq | |
49 | pin. We could also use the bus number to have a more precise | |
50 | mapping. */ | |
51 | static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) | |
52 | { | |
53 | int slot_addend; | |
54 | slot_addend = (pci_dev->devfn >> 3) - 1; | |
55 | return (irq_num + slot_addend) & 3; | |
56 | } | |
502a5395 | 57 | |
ee0ea1d0 FB |
58 | static uint32_t isa_page_descs[384 / 4]; |
59 | static uint8_t smm_enabled; | |
60 | ||
84631fd7 FB |
61 | static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r) |
62 | { | |
63 | uint32_t addr; | |
64 | ||
65 | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r); | |
66 | switch(r) { | |
67 | case 3: | |
68 | /* RAM */ | |
5fafdf24 | 69 | cpu_register_physical_memory(start, end - start, |
84631fd7 FB |
70 | start); |
71 | break; | |
72 | case 1: | |
73 | /* ROM (XXX: not quite correct) */ | |
5fafdf24 | 74 | cpu_register_physical_memory(start, end - start, |
84631fd7 FB |
75 | start | IO_MEM_ROM); |
76 | break; | |
77 | case 2: | |
78 | case 0: | |
79 | /* XXX: should distinguish read/write cases */ | |
80 | for(addr = start; addr < end; addr += 4096) { | |
5fafdf24 | 81 | cpu_register_physical_memory(addr, 4096, |
84631fd7 FB |
82 | isa_page_descs[(addr - 0xa0000) >> 12]); |
83 | } | |
84 | break; | |
85 | } | |
86 | } | |
ee0ea1d0 FB |
87 | |
88 | static void i440fx_update_memory_mappings(PCIDevice *d) | |
89 | { | |
90 | int i, r; | |
84631fd7 FB |
91 | uint32_t smram, addr; |
92 | ||
93 | update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3); | |
94 | for(i = 0; i < 12; i++) { | |
95 | r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; | |
96 | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); | |
ee0ea1d0 | 97 | } |
84631fd7 FB |
98 | smram = d->config[0x72]; |
99 | if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) { | |
100 | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); | |
101 | } else { | |
102 | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { | |
5fafdf24 | 103 | cpu_register_physical_memory(addr, 4096, |
84631fd7 | 104 | isa_page_descs[(addr - 0xa0000) >> 12]); |
ee0ea1d0 FB |
105 | } |
106 | } | |
107 | } | |
108 | ||
109 | void i440fx_set_smm(PCIDevice *d, int val) | |
110 | { | |
111 | val = (val != 0); | |
112 | if (smm_enabled != val) { | |
113 | smm_enabled = val; | |
114 | i440fx_update_memory_mappings(d); | |
115 | } | |
116 | } | |
117 | ||
118 | ||
119 | /* XXX: suppress when better memory API. We make the assumption that | |
120 | no device (in particular the VGA) changes the memory mappings in | |
121 | the 0xa0000-0x100000 range */ | |
122 | void i440fx_init_memory_mappings(PCIDevice *d) | |
123 | { | |
124 | int i; | |
125 | for(i = 0; i < 96; i++) { | |
126 | isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); | |
127 | } | |
128 | } | |
129 | ||
5fafdf24 | 130 | static void i440fx_write_config(PCIDevice *d, |
ee0ea1d0 FB |
131 | uint32_t address, uint32_t val, int len) |
132 | { | |
133 | /* XXX: implement SMRAM.D_LOCK */ | |
134 | pci_default_write_config(d, address, val, len); | |
84631fd7 | 135 | if ((address >= 0x59 && address <= 0x5f) || address == 0x72) |
ee0ea1d0 FB |
136 | i440fx_update_memory_mappings(d); |
137 | } | |
138 | ||
139 | static void i440fx_save(QEMUFile* f, void *opaque) | |
140 | { | |
141 | PCIDevice *d = opaque; | |
142 | pci_device_save(d, f); | |
143 | qemu_put_8s(f, &smm_enabled); | |
144 | } | |
145 | ||
146 | static int i440fx_load(QEMUFile* f, void *opaque, int version_id) | |
147 | { | |
148 | PCIDevice *d = opaque; | |
149 | int ret; | |
150 | ||
151 | if (version_id != 1) | |
152 | return -EINVAL; | |
153 | ret = pci_device_load(d, f); | |
154 | if (ret < 0) | |
155 | return ret; | |
156 | i440fx_update_memory_mappings(d); | |
157 | qemu_get_8s(f, &smm_enabled); | |
158 | return 0; | |
159 | } | |
160 | ||
d537cf6c | 161 | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic) |
502a5395 PB |
162 | { |
163 | PCIBus *b; | |
164 | PCIDevice *d; | |
165 | I440FXState *s; | |
166 | ||
167 | s = qemu_mallocz(sizeof(I440FXState)); | |
d537cf6c | 168 | b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4); |
502a5395 PB |
169 | s->bus = b; |
170 | ||
171 | register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); | |
172 | register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); | |
173 | ||
174 | register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); | |
175 | register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); | |
176 | register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); | |
177 | register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); | |
178 | register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); | |
179 | register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); | |
180 | ||
5fafdf24 | 181 | d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, |
ee0ea1d0 | 182 | NULL, i440fx_write_config); |
502a5395 PB |
183 | |
184 | d->config[0x00] = 0x86; // vendor_id | |
185 | d->config[0x01] = 0x80; | |
186 | d->config[0x02] = 0x37; // device_id | |
187 | d->config[0x03] = 0x12; | |
188 | d->config[0x08] = 0x02; // revision | |
189 | d->config[0x0a] = 0x00; // class_sub = host2pci | |
190 | d->config[0x0b] = 0x06; // class_base = PCI_bridge | |
191 | d->config[0x0e] = 0x00; // header_type | |
ee0ea1d0 | 192 | |
84631fd7 | 193 | d->config[0x72] = 0x02; /* SMRAM */ |
ee0ea1d0 FB |
194 | |
195 | register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d); | |
196 | *pi440fx_state = d; | |
502a5395 PB |
197 | return b; |
198 | } | |
199 | ||
200 | /* PIIX3 PCI to ISA bridge */ | |
201 | ||
8f1c91d8 | 202 | PCIDevice *piix3_dev; |
5c2b87e3 | 203 | PCIDevice *piix4_dev; |
502a5395 PB |
204 | |
205 | /* just used for simpler irq handling. */ | |
206 | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) | |
207 | ||
d2b59317 | 208 | static int pci_irq_levels[4]; |
502a5395 | 209 | |
d537cf6c | 210 | static void piix3_set_irq(qemu_irq *pic, int irq_num, int level) |
502a5395 | 211 | { |
d2b59317 | 212 | int i, pic_irq, pic_level; |
502a5395 | 213 | |
3f6ffb6a | 214 | piix3_dev->config[0x60 + irq_num] &= ~0x80; // enable bit |
d2b59317 | 215 | pci_irq_levels[irq_num] = level; |
502a5395 PB |
216 | |
217 | /* now we change the pic irq level according to the piix irq mappings */ | |
218 | /* XXX: optimize */ | |
219 | pic_irq = piix3_dev->config[0x60 + irq_num]; | |
220 | if (pic_irq < 16) { | |
d2b59317 | 221 | /* The pic level is the logical OR of all the PCI irqs mapped |
502a5395 PB |
222 | to it */ |
223 | pic_level = 0; | |
d2b59317 PB |
224 | for (i = 0; i < 4; i++) { |
225 | if (pic_irq == piix3_dev->config[0x60 + i]) | |
226 | pic_level |= pci_irq_levels[i]; | |
227 | } | |
d537cf6c | 228 | qemu_set_irq(pic[pic_irq], pic_level); |
502a5395 PB |
229 | } |
230 | } | |
231 | ||
232 | static void piix3_reset(PCIDevice *d) | |
233 | { | |
234 | uint8_t *pci_conf = d->config; | |
235 | ||
236 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
237 | pci_conf[0x05] = 0x00; | |
238 | pci_conf[0x06] = 0x00; | |
239 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
240 | pci_conf[0x4c] = 0x4d; | |
241 | pci_conf[0x4e] = 0x03; | |
242 | pci_conf[0x4f] = 0x00; | |
243 | pci_conf[0x60] = 0x80; | |
244 | pci_conf[0x69] = 0x02; | |
245 | pci_conf[0x70] = 0x80; | |
246 | pci_conf[0x76] = 0x0c; | |
247 | pci_conf[0x77] = 0x0c; | |
248 | pci_conf[0x78] = 0x02; | |
249 | pci_conf[0x79] = 0x00; | |
250 | pci_conf[0x80] = 0x00; | |
251 | pci_conf[0x82] = 0x00; | |
252 | pci_conf[0xa0] = 0x08; | |
502a5395 PB |
253 | pci_conf[0xa2] = 0x00; |
254 | pci_conf[0xa3] = 0x00; | |
255 | pci_conf[0xa4] = 0x00; | |
256 | pci_conf[0xa5] = 0x00; | |
257 | pci_conf[0xa6] = 0x00; | |
258 | pci_conf[0xa7] = 0x00; | |
259 | pci_conf[0xa8] = 0x0f; | |
260 | pci_conf[0xaa] = 0x00; | |
261 | pci_conf[0xab] = 0x00; | |
262 | pci_conf[0xac] = 0x00; | |
263 | pci_conf[0xae] = 0x00; | |
264 | } | |
265 | ||
5c2b87e3 TS |
266 | static void piix4_reset(PCIDevice *d) |
267 | { | |
268 | uint8_t *pci_conf = d->config; | |
269 | ||
270 | pci_conf[0x04] = 0x07; // master, memory and I/O | |
271 | pci_conf[0x05] = 0x00; | |
272 | pci_conf[0x06] = 0x00; | |
273 | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium | |
274 | pci_conf[0x4c] = 0x4d; | |
275 | pci_conf[0x4e] = 0x03; | |
276 | pci_conf[0x4f] = 0x00; | |
277 | pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 | |
278 | pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 | |
279 | pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 | |
280 | pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 | |
281 | pci_conf[0x69] = 0x02; | |
282 | pci_conf[0x70] = 0x80; | |
283 | pci_conf[0x76] = 0x0c; | |
284 | pci_conf[0x77] = 0x0c; | |
285 | pci_conf[0x78] = 0x02; | |
286 | pci_conf[0x79] = 0x00; | |
287 | pci_conf[0x80] = 0x00; | |
288 | pci_conf[0x82] = 0x00; | |
289 | pci_conf[0xa0] = 0x08; | |
5c2b87e3 TS |
290 | pci_conf[0xa2] = 0x00; |
291 | pci_conf[0xa3] = 0x00; | |
292 | pci_conf[0xa4] = 0x00; | |
293 | pci_conf[0xa5] = 0x00; | |
294 | pci_conf[0xa6] = 0x00; | |
295 | pci_conf[0xa7] = 0x00; | |
296 | pci_conf[0xa8] = 0x0f; | |
297 | pci_conf[0xaa] = 0x00; | |
298 | pci_conf[0xab] = 0x00; | |
299 | pci_conf[0xac] = 0x00; | |
300 | pci_conf[0xae] = 0x00; | |
301 | } | |
302 | ||
1941d19c FB |
303 | static void piix_save(QEMUFile* f, void *opaque) |
304 | { | |
305 | PCIDevice *d = opaque; | |
306 | pci_device_save(d, f); | |
307 | } | |
308 | ||
309 | static int piix_load(QEMUFile* f, void *opaque, int version_id) | |
310 | { | |
311 | PCIDevice *d = opaque; | |
312 | if (version_id != 2) | |
313 | return -EINVAL; | |
314 | return pci_device_load(d, f); | |
315 | } | |
316 | ||
8f1c91d8 | 317 | int piix3_init(PCIBus *bus, int devfn) |
502a5395 PB |
318 | { |
319 | PCIDevice *d; | |
320 | uint8_t *pci_conf; | |
321 | ||
322 | d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice), | |
8f1c91d8 | 323 | devfn, NULL, NULL); |
1941d19c | 324 | register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); |
502a5395 PB |
325 | |
326 | piix3_dev = d; | |
327 | pci_conf = d->config; | |
328 | ||
329 | pci_conf[0x00] = 0x86; // Intel | |
330 | pci_conf[0x01] = 0x80; | |
331 | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) | |
332 | pci_conf[0x03] = 0x70; | |
333 | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA | |
334 | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge | |
335 | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic | |
336 | ||
337 | piix3_reset(d); | |
338 | return d->devfn; | |
339 | } | |
5c2b87e3 TS |
340 | |
341 | int piix4_init(PCIBus *bus, int devfn) | |
342 | { | |
343 | PCIDevice *d; | |
344 | uint8_t *pci_conf; | |
345 | ||
346 | d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice), | |
347 | devfn, NULL, NULL); | |
348 | register_savevm("PIIX4", 0, 2, piix_save, piix_load, d); | |
349 | ||
350 | piix4_dev = d; | |
351 | pci_conf = d->config; | |
352 | ||
353 | pci_conf[0x00] = 0x86; // Intel | |
354 | pci_conf[0x01] = 0x80; | |
355 | pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge | |
356 | pci_conf[0x03] = 0x71; | |
357 | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA | |
358 | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge | |
359 | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic | |
360 | ||
361 | piix4_reset(d); | |
362 | return d->devfn; | |
363 | } |