[mirror_qemu.git] / hw / piix_pci.c

/*
 * QEMU i440FX/PIIX3 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "pc.h"
#include "pci.h"

typedef uint32_t pci_addr_t;
#include "pci_host.h"

typedef PCIHostState I440FXState;

static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
{
    I440FXState *s = opaque;
    s->config_reg = val;
}

static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
{
    I440FXState *s = opaque;
    return s->config_reg;
}

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);

/* return the global irq number corresponding to a given device irq
   pin. We could also use the bus number to have a more precise
   mapping. */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
{
    int slot_addend;
    slot_addend = (pci_dev->devfn >> 3) - 1;
    return (irq_num + slot_addend) & 3;
}

static uint32_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];

static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
{
    uint32_t addr;

    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
    switch(r) {
    case 3:
        /* RAM */
        cpu_register_physical_memory(start, end - start,
                                     start);
        break;
    case 1:
        /* ROM (XXX: not quite correct) */
        cpu_register_physical_memory(start, end - start,
                                     start | IO_MEM_ROM);
        break;
    case 2:
    case 0:
        /* XXX: should distinguish read/write cases */
        for(addr = start; addr < end; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
        break;
    }
}

static void i440fx_update_memory_mappings(PCIDevice *d)
{
    int i, r;
    uint32_t smram, addr;

    update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
    for(i = 0; i < 12; i++) {
        r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
    }
    smram = d->config[0x72];
    if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
    } else {
        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
            cpu_register_physical_memory(addr, 4096,
                                         isa_page_descs[(addr - 0xa0000) >> 12]);
        }
    }
}

void i440fx_set_smm(PCIDevice *d, int val)
{
    val = (val != 0);
    if (smm_enabled != val) {
        smm_enabled = val;
        i440fx_update_memory_mappings(d);
    }
}


/* XXX: suppress when better memory API. We make the assumption that
   no device (in particular the VGA) changes the memory mappings in
   the 0xa0000-0x100000 range */
void i440fx_init_memory_mappings(PCIDevice *d)
{
    int i;
    for(i = 0; i < 96; i++) {
        isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
    }
}

static void i440fx_write_config(PCIDevice *d,
                                uint32_t address, uint32_t val, int len)
{
    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(d, address, val, len);
    if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
        i440fx_update_memory_mappings(d);
}

static void i440fx_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    int i;

    pci_device_save(d, f);
    qemu_put_8s(f, &smm_enabled);

    for (i = 0; i < 4; i++)
        qemu_put_be32(f, pci_irq_levels[i]);
}

static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    int ret, i;

    if (version_id > 2)
        return -EINVAL;
    ret = pci_device_load(d, f);
    if (ret < 0)
        return ret;
    i440fx_update_memory_mappings(d);
    qemu_get_8s(f, &smm_enabled);

    if (version_id >= 2)
        for (i = 0; i < 4; i++)
            pci_irq_levels[i] = qemu_get_be32(f);

    return 0;
}

PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
{
    PCIBus *b;
    PCIDevice *d;
    I440FXState *s;

    s = qemu_mallocz(sizeof(I440FXState));
    b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
    s->bus = b;

    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
    register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);

    register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
    register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
    register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
    register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);

    d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
                            NULL, i440fx_write_config);

    d->config[0x00] = 0x86; // vendor_id
    d->config[0x01] = 0x80;
    d->config[0x02] = 0x37; // device_id
    d->config[0x03] = 0x12;
    d->config[0x08] = 0x02; // revision
    d->config[0x0a] = 0x00; // class_sub = host2pci
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
    d->config[0x0e] = 0x00; // header_type

    d->config[0x72] = 0x02; /* SMRAM */

    register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
    *pi440fx_state = d;
    return b;
}

/* PIIX3 PCI to ISA bridge */

PCIDevice *piix3_dev;
PCIDevice *piix4_dev;

/* just used for simpler irq handling. */
#define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)

static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
    int i, pic_irq, pic_level;

    pci_irq_levels[irq_num] = level;

    /* now we change the pic irq level according to the piix irq mappings */
    /* XXX: optimize */
    pic_irq = piix3_dev->config[0x60 + irq_num];
    if (pic_irq < 16) {
        /* The pic level is the logical OR of all the PCI irqs mapped
           to it */
        pic_level = 0;
        for (i = 0; i < 4; i++) {
            if (pic_irq == piix3_dev->config[0x60 + i])
                pic_level |= pci_irq_levels[i];
        }
        qemu_set_irq(pic[pic_irq], pic_level);
    }
}

static void piix3_reset(PCIDevice *d)
{
    uint8_t *pci_conf = d->config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x80;
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;
}

static void piix4_reset(PCIDevice *d)
{
    uint8_t *pci_conf = d->config;

    pci_conf[0x04] = 0x07; // master, memory and I/O
    pci_conf[0x05] = 0x00;
    pci_conf[0x06] = 0x00;
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
    pci_conf[0x4c] = 0x4d;
    pci_conf[0x4e] = 0x03;
    pci_conf[0x4f] = 0x00;
    pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
    pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
    pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
    pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
    pci_conf[0x69] = 0x02;
    pci_conf[0x70] = 0x80;
    pci_conf[0x76] = 0x0c;
    pci_conf[0x77] = 0x0c;
    pci_conf[0x78] = 0x02;
    pci_conf[0x79] = 0x00;
    pci_conf[0x80] = 0x00;
    pci_conf[0x82] = 0x00;
    pci_conf[0xa0] = 0x08;
    pci_conf[0xa2] = 0x00;
    pci_conf[0xa3] = 0x00;
    pci_conf[0xa4] = 0x00;
    pci_conf[0xa5] = 0x00;
    pci_conf[0xa6] = 0x00;
    pci_conf[0xa7] = 0x00;
    pci_conf[0xa8] = 0x0f;
    pci_conf[0xaa] = 0x00;
    pci_conf[0xab] = 0x00;
    pci_conf[0xac] = 0x00;
    pci_conf[0xae] = 0x00;
}

static void piix_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;
    pci_device_save(d, f);
}

static int piix_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;
    if (version_id != 2)
        return -EINVAL;
    return pci_device_load(d, f);
}

int piix3_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;
    uint8_t *pci_conf;

    d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
                                    devfn, NULL, NULL);
    register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);

    piix3_dev = d;
    pci_conf = d->config;

    pci_conf[0x00] = 0x86; // Intel
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
    pci_conf[0x03] = 0x70;
    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

    piix3_reset(d);
    return d->devfn;
}

int piix4_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;
    uint8_t *pci_conf;

    d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
                                    devfn, NULL, NULL);
    register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);

    piix4_dev = d;
    pci_conf = d->config;

    pci_conf[0x00] = 0x86; // Intel
    pci_conf[0x01] = 0x80;
    pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
    pci_conf[0x03] = 0x71;
    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

    piix4_reset(d);
    return d->devfn;
}
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU i440FX/PIIX3 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
87ecb68b PB	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "pci.h"
	28
502a5395 PB	29	typedef uint32_t pci_addr_t;
	30	#include "pci_host.h"
	31
	32	typedef PCIHostState I440FXState;
	33
	34	static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
	35	{
	36	I440FXState *s = opaque;
	37	s->config_reg = val;
	38	}
	39
	40	static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
	41	{
	42	I440FXState *s = opaque;
	43	return s->config_reg;
	44	}
	45
d537cf6c	46	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
d2b59317 PB	47
	48	/* return the global irq number corresponding to a given device irq
	49	pin. We could also use the bus number to have a more precise
	50	mapping. */
	51	static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
	52	{
	53	int slot_addend;
	54	slot_addend = (pci_dev->devfn >> 3) - 1;
	55	return (irq_num + slot_addend) & 3;
	56	}
502a5395	57
ee0ea1d0 FB	58	static uint32_t isa_page_descs[384 / 4];
ee0ea1d0 FB	59	static uint8_t smm_enabled;
52fc1d83	60	static int pci_irq_levels[4];
ee0ea1d0	61
84631fd7 FB	62	static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
	63	{
	64	uint32_t addr;
	65
	66	// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
	67	switch(r) {
	68	case 3:
	69	/* RAM */
5fafdf24	70	cpu_register_physical_memory(start, end - start,
84631fd7 FB	71	start);
	72	break;
	73	case 1:
	74	/* ROM (XXX: not quite correct) */
5fafdf24	75	cpu_register_physical_memory(start, end - start,
84631fd7 FB	76	start \| IO_MEM_ROM);
	77	break;
	78	case 2:
	79	case 0:
	80	/* XXX: should distinguish read/write cases */
	81	for(addr = start; addr < end; addr += 4096) {
5fafdf24	82	cpu_register_physical_memory(addr, 4096,
84631fd7 FB	83	isa_page_descs[(addr - 0xa0000) >> 12]);
	84	}
	85	break;
	86	}
	87	}
ee0ea1d0 FB	88
	89	static void i440fx_update_memory_mappings(PCIDevice *d)
	90	{
	91	int i, r;
84631fd7 FB	92	uint32_t smram, addr;
	93
	94	update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
	95	for(i = 0; i < 12; i++) {
	96	r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
	97	update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0	98	}
84631fd7 FB	99	smram = d->config[0x72];
	100	if ((smm_enabled && (smram & 0x08)) \|\| (smram & 0x40)) {
	101	cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
	102	} else {
	103	for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24	104	cpu_register_physical_memory(addr, 4096,
84631fd7	105	isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0 FB	106	}
	107	}
	108	}
	109
	110	void i440fx_set_smm(PCIDevice *d, int val)
	111	{
	112	val = (val != 0);
	113	if (smm_enabled != val) {
	114	smm_enabled = val;
	115	i440fx_update_memory_mappings(d);
	116	}
	117	}
	118
	119
	120	/* XXX: suppress when better memory API. We make the assumption that
	121	no device (in particular the VGA) changes the memory mappings in
	122	the 0xa0000-0x100000 range */
	123	void i440fx_init_memory_mappings(PCIDevice *d)
	124	{
	125	int i;
	126	for(i = 0; i < 96; i++) {
	127	isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
	128	}
	129	}
	130
5fafdf24	131	static void i440fx_write_config(PCIDevice *d,
ee0ea1d0 FB	132	uint32_t address, uint32_t val, int len)
	133	{
	134	/* XXX: implement SMRAM.D_LOCK */
	135	pci_default_write_config(d, address, val, len);
84631fd7	136	if ((address >= 0x59 && address <= 0x5f) \|\| address == 0x72)
ee0ea1d0 FB	137	i440fx_update_memory_mappings(d);
	138	}
	139
	140	static void i440fx_save(QEMUFile* f, void *opaque)
	141	{
	142	PCIDevice *d = opaque;
52fc1d83 AZ	143	int i;
52fc1d83 AZ	144
ee0ea1d0 FB	145	pci_device_save(d, f);
ee0ea1d0 FB	146	qemu_put_8s(f, &smm_enabled);
52fc1d83 AZ	147
	148	for (i = 0; i < 4; i++)
	149	qemu_put_be32(f, pci_irq_levels[i]);
ee0ea1d0 FB	150	}
	151
	152	static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
	153	{
	154	PCIDevice *d = opaque;
52fc1d83	155	int ret, i;
ee0ea1d0	156
52fc1d83	157	if (version_id > 2)
ee0ea1d0 FB	158	return -EINVAL;
	159	ret = pci_device_load(d, f);
	160	if (ret < 0)
	161	return ret;
	162	i440fx_update_memory_mappings(d);
	163	qemu_get_8s(f, &smm_enabled);
52fc1d83 AZ	164
	165	if (version_id >= 2)
	166	for (i = 0; i < 4; i++)
	167	pci_irq_levels[i] = qemu_get_be32(f);
	168
ee0ea1d0 FB	169	return 0;
	170	}
	171
d537cf6c	172	PCIBus i440fx_init(PCIDevice pi440fx_state, qemu_irq pic)
502a5395 PB	173	{
	174	PCIBus *b;
	175	PCIDevice *d;
	176	I440FXState *s;
	177
	178	s = qemu_mallocz(sizeof(I440FXState));
d537cf6c	179	b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
502a5395 PB	180	s->bus = b;
	181
	182	register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
	183	register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
	184
	185	register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
	186	register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
	187	register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
	188	register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
	189	register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
	190	register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
	191
5fafdf24	192	d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
ee0ea1d0	193	NULL, i440fx_write_config);
502a5395 PB	194
	195	d->config[0x00] = 0x86; // vendor_id
	196	d->config[0x01] = 0x80;
	197	d->config[0x02] = 0x37; // device_id
	198	d->config[0x03] = 0x12;
	199	d->config[0x08] = 0x02; // revision
	200	d->config[0x0a] = 0x00; // class_sub = host2pci
	201	d->config[0x0b] = 0x06; // class_base = PCI_bridge
	202	d->config[0x0e] = 0x00; // header_type
ee0ea1d0	203
84631fd7	204	d->config[0x72] = 0x02; /* SMRAM */
ee0ea1d0	205
52fc1d83	206	register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
ee0ea1d0	207	*pi440fx_state = d;
502a5395 PB	208	return b;
	209	}
	210
	211	/* PIIX3 PCI to ISA bridge */
	212
8f1c91d8	213	PCIDevice *piix3_dev;
5c2b87e3	214	PCIDevice *piix4_dev;
502a5395 PB	215
	216	/* just used for simpler irq handling. */
	217	#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
	218
d537cf6c	219	static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
502a5395	220	{
d2b59317	221	int i, pic_irq, pic_level;
502a5395	222
d2b59317	223	pci_irq_levels[irq_num] = level;
502a5395 PB	224
	225	/* now we change the pic irq level according to the piix irq mappings */
	226	/* XXX: optimize */
	227	pic_irq = piix3_dev->config[0x60 + irq_num];
	228	if (pic_irq < 16) {
d2b59317	229	/* The pic level is the logical OR of all the PCI irqs mapped
502a5395 PB	230	to it */
502a5395 PB	231	pic_level = 0;
d2b59317 PB	232	for (i = 0; i < 4; i++) {
	233	if (pic_irq == piix3_dev->config[0x60 + i])
	234	pic_level \|= pci_irq_levels[i];
	235	}
d537cf6c	236	qemu_set_irq(pic[pic_irq], pic_level);
502a5395 PB	237	}
	238	}
	239
	240	static void piix3_reset(PCIDevice *d)
	241	{
	242	uint8_t *pci_conf = d->config;
	243
	244	pci_conf[0x04] = 0x07; // master, memory and I/O
	245	pci_conf[0x05] = 0x00;
	246	pci_conf[0x06] = 0x00;
	247	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	248	pci_conf[0x4c] = 0x4d;
	249	pci_conf[0x4e] = 0x03;
	250	pci_conf[0x4f] = 0x00;
	251	pci_conf[0x60] = 0x80;
	252	pci_conf[0x69] = 0x02;
	253	pci_conf[0x70] = 0x80;
	254	pci_conf[0x76] = 0x0c;
	255	pci_conf[0x77] = 0x0c;
	256	pci_conf[0x78] = 0x02;
	257	pci_conf[0x79] = 0x00;
	258	pci_conf[0x80] = 0x00;
	259	pci_conf[0x82] = 0x00;
	260	pci_conf[0xa0] = 0x08;
502a5395 PB	261	pci_conf[0xa2] = 0x00;
	262	pci_conf[0xa3] = 0x00;
	263	pci_conf[0xa4] = 0x00;
	264	pci_conf[0xa5] = 0x00;
	265	pci_conf[0xa6] = 0x00;
	266	pci_conf[0xa7] = 0x00;
	267	pci_conf[0xa8] = 0x0f;
	268	pci_conf[0xaa] = 0x00;
	269	pci_conf[0xab] = 0x00;
	270	pci_conf[0xac] = 0x00;
	271	pci_conf[0xae] = 0x00;
	272	}
	273
5c2b87e3 TS	274	static void piix4_reset(PCIDevice *d)
	275	{
	276	uint8_t *pci_conf = d->config;
	277
	278	pci_conf[0x04] = 0x07; // master, memory and I/O
	279	pci_conf[0x05] = 0x00;
	280	pci_conf[0x06] = 0x00;
	281	pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
	282	pci_conf[0x4c] = 0x4d;
	283	pci_conf[0x4e] = 0x03;
	284	pci_conf[0x4f] = 0x00;
	285	pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
	286	pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
	287	pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
	288	pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
	289	pci_conf[0x69] = 0x02;
	290	pci_conf[0x70] = 0x80;
	291	pci_conf[0x76] = 0x0c;
	292	pci_conf[0x77] = 0x0c;
	293	pci_conf[0x78] = 0x02;
	294	pci_conf[0x79] = 0x00;
	295	pci_conf[0x80] = 0x00;
	296	pci_conf[0x82] = 0x00;
	297	pci_conf[0xa0] = 0x08;
5c2b87e3 TS	298	pci_conf[0xa2] = 0x00;
	299	pci_conf[0xa3] = 0x00;
	300	pci_conf[0xa4] = 0x00;
	301	pci_conf[0xa5] = 0x00;
	302	pci_conf[0xa6] = 0x00;
	303	pci_conf[0xa7] = 0x00;
	304	pci_conf[0xa8] = 0x0f;
	305	pci_conf[0xaa] = 0x00;
	306	pci_conf[0xab] = 0x00;
	307	pci_conf[0xac] = 0x00;
	308	pci_conf[0xae] = 0x00;
	309	}
	310
1941d19c FB	311	static void piix_save(QEMUFile* f, void *opaque)
	312	{
	313	PCIDevice *d = opaque;
	314	pci_device_save(d, f);
	315	}
	316
	317	static int piix_load(QEMUFile* f, void *opaque, int version_id)
	318	{
	319	PCIDevice *d = opaque;
	320	if (version_id != 2)
	321	return -EINVAL;
	322	return pci_device_load(d, f);
	323	}
	324
8f1c91d8	325	int piix3_init(PCIBus *bus, int devfn)
502a5395 PB	326	{
	327	PCIDevice *d;
	328	uint8_t *pci_conf;
	329
	330	d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
8f1c91d8	331	devfn, NULL, NULL);
1941d19c	332	register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
502a5395 PB	333
	334	piix3_dev = d;
	335	pci_conf = d->config;
	336
	337	pci_conf[0x00] = 0x86; // Intel
	338	pci_conf[0x01] = 0x80;
	339	pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
	340	pci_conf[0x03] = 0x70;
	341	pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
	342	pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
	343	pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
	344
	345	piix3_reset(d);
	346	return d->devfn;
	347	}
5c2b87e3 TS	348
	349	int piix4_init(PCIBus *bus, int devfn)
	350	{
	351	PCIDevice *d;
	352	uint8_t *pci_conf;
	353
	354	d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
	355	devfn, NULL, NULL);
	356	register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
	357
	358	piix4_dev = d;
	359	pci_conf = d->config;
	360
	361	pci_conf[0x00] = 0x86; // Intel
	362	pci_conf[0x01] = 0x80;
	363	pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
	364	pci_conf[0x03] = 0x71;
	365	pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
	366	pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
	367	pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
	368
	369	piix4_reset(d);
	370	return d->devfn;
	371	}