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Create PIIX3State instead of using PCIDevice for PIIX3
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CommitLineData
502a5395
PB
1/*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5fafdf24 5 *
502a5395
PB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
87ecb68b
PB
25#include "hw.h"
26#include "pc.h"
27#include "pci.h"
f75247f1 28#include "isa.h"
8a14daa5 29#include "sysbus.h"
87ecb68b 30
502a5395
PB
31typedef uint32_t pci_addr_t;
32#include "pci_host.h"
33
34typedef PCIHostState I440FXState;
35
fd37d881
JQ
36typedef struct PIIX3State {
37 PCIDevice dev;
38} PIIX3State;
39
0a3bacf3
JQ
40struct PCII440FXState {
41 PCIDevice dev;
6c009fa4
JQ
42 target_phys_addr_t isa_page_descs[384 / 4];
43 uint8_t smm_enabled;
0a3bacf3
JQ
44};
45
502a5395
PB
46static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
47{
48 I440FXState *s = opaque;
49 s->config_reg = val;
50}
51
52static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
53{
54 I440FXState *s = opaque;
55 return s->config_reg;
56}
57
5d4e84c8 58static void piix3_set_irq(void *opaque, int irq_num, int level);
d2b59317
PB
59
60/* return the global irq number corresponding to a given device irq
61 pin. We could also use the bus number to have a more precise
62 mapping. */
63static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
64{
65 int slot_addend;
66 slot_addend = (pci_dev->devfn >> 3) - 1;
67 return (irq_num + slot_addend) & 3;
68}
502a5395 69
52fc1d83 70static int pci_irq_levels[4];
ee0ea1d0 71
0a3bacf3 72static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
84631fd7
FB
73{
74 uint32_t addr;
75
76 // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
77 switch(r) {
78 case 3:
79 /* RAM */
5fafdf24 80 cpu_register_physical_memory(start, end - start,
84631fd7
FB
81 start);
82 break;
83 case 1:
84 /* ROM (XXX: not quite correct) */
5fafdf24 85 cpu_register_physical_memory(start, end - start,
84631fd7
FB
86 start | IO_MEM_ROM);
87 break;
88 case 2:
89 case 0:
90 /* XXX: should distinguish read/write cases */
91 for(addr = start; addr < end; addr += 4096) {
5fafdf24 92 cpu_register_physical_memory(addr, 4096,
6c009fa4 93 d->isa_page_descs[(addr - 0xa0000) >> 12]);
84631fd7
FB
94 }
95 break;
96 }
97}
ee0ea1d0 98
0a3bacf3 99static void i440fx_update_memory_mappings(PCII440FXState *d)
ee0ea1d0
FB
100{
101 int i, r;
84631fd7
FB
102 uint32_t smram, addr;
103
0a3bacf3 104 update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
84631fd7 105 for(i = 0; i < 12; i++) {
0a3bacf3 106 r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
84631fd7 107 update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
ee0ea1d0 108 }
0a3bacf3 109 smram = d->dev.config[0x72];
6c009fa4 110 if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
84631fd7
FB
111 cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
112 } else {
113 for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
5fafdf24 114 cpu_register_physical_memory(addr, 4096,
6c009fa4 115 d->isa_page_descs[(addr - 0xa0000) >> 12]);
ee0ea1d0
FB
116 }
117 }
118}
119
0a3bacf3 120void i440fx_set_smm(PCII440FXState *d, int val)
ee0ea1d0
FB
121{
122 val = (val != 0);
6c009fa4
JQ
123 if (d->smm_enabled != val) {
124 d->smm_enabled = val;
ee0ea1d0
FB
125 i440fx_update_memory_mappings(d);
126 }
127}
128
129
130/* XXX: suppress when better memory API. We make the assumption that
131 no device (in particular the VGA) changes the memory mappings in
132 the 0xa0000-0x100000 range */
0a3bacf3 133void i440fx_init_memory_mappings(PCII440FXState *d)
ee0ea1d0
FB
134{
135 int i;
136 for(i = 0; i < 96; i++) {
6c009fa4 137 d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
ee0ea1d0
FB
138 }
139}
140
0a3bacf3 141static void i440fx_write_config(PCIDevice *dev,
ee0ea1d0
FB
142 uint32_t address, uint32_t val, int len)
143{
0a3bacf3
JQ
144 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
145
ee0ea1d0 146 /* XXX: implement SMRAM.D_LOCK */
0a3bacf3 147 pci_default_write_config(dev, address, val, len);
84631fd7 148 if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
ee0ea1d0
FB
149 i440fx_update_memory_mappings(d);
150}
151
152static void i440fx_save(QEMUFile* f, void *opaque)
153{
0a3bacf3 154 PCII440FXState *d = opaque;
52fc1d83
AZ
155 int i;
156
0a3bacf3 157 pci_device_save(&d->dev, f);
6c009fa4 158 qemu_put_8s(f, &d->smm_enabled);
52fc1d83
AZ
159
160 for (i = 0; i < 4; i++)
161 qemu_put_be32(f, pci_irq_levels[i]);
ee0ea1d0
FB
162}
163
164static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
165{
0a3bacf3 166 PCII440FXState *d = opaque;
52fc1d83 167 int ret, i;
ee0ea1d0 168
52fc1d83 169 if (version_id > 2)
ee0ea1d0 170 return -EINVAL;
0a3bacf3 171 ret = pci_device_load(&d->dev, f);
ee0ea1d0
FB
172 if (ret < 0)
173 return ret;
174 i440fx_update_memory_mappings(d);
6c009fa4 175 qemu_get_8s(f, &d->smm_enabled);
52fc1d83
AZ
176
177 if (version_id >= 2)
178 for (i = 0; i < 4; i++)
179 pci_irq_levels[i] = qemu_get_be32(f);
180
ee0ea1d0
FB
181 return 0;
182}
183
81a322d4 184static int i440fx_pcihost_initfn(SysBusDevice *dev)
502a5395 185{
8a14daa5 186 I440FXState *s = FROM_SYSBUS(I440FXState, dev);
502a5395
PB
187
188 register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
189 register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
190
191 register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
192 register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
193 register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
194 register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
195 register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
196 register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
81a322d4 197 return 0;
8a14daa5 198}
502a5395 199
0a3bacf3 200static int i440fx_initfn(PCIDevice *dev)
8a14daa5 201{
0a3bacf3 202 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
ee0ea1d0 203
0a3bacf3
JQ
204 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
205 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
206 d->dev.config[0x08] = 0x02; // revision
207 pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
208 d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
209
210 d->dev.config[0x72] = 0x02; /* SMRAM */
ee0ea1d0 211
52fc1d83 212 register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
81a322d4 213 return 0;
8a14daa5
GH
214}
215
0a3bacf3 216PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
8a14daa5
GH
217{
218 DeviceState *dev;
219 PCIBus *b;
220 PCIDevice *d;
221 I440FXState *s;
222
223 dev = qdev_create(NULL, "i440FX-pcihost");
224 s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
225 b = pci_register_bus(&s->busdev.qdev, "pci.0",
226 piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
227 s->bus = b;
228 qdev_init(dev);
229
230 d = pci_create_simple(b, 0, "i440FX");
0a3bacf3 231 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
8a14daa5 232
502a5395
PB
233 return b;
234}
235
236/* PIIX3 PCI to ISA bridge */
237
fd37d881 238static PIIX3State *piix3_dev;
502a5395 239
5d4e84c8 240static void piix3_set_irq(void *opaque, int irq_num, int level)
502a5395 241{
d2b59317 242 int i, pic_irq, pic_level;
5d4e84c8 243 qemu_irq *pic = opaque;
502a5395 244
d2b59317 245 pci_irq_levels[irq_num] = level;
502a5395
PB
246
247 /* now we change the pic irq level according to the piix irq mappings */
248 /* XXX: optimize */
fd37d881 249 pic_irq = piix3_dev->dev.config[0x60 + irq_num];
502a5395 250 if (pic_irq < 16) {
d2b59317 251 /* The pic level is the logical OR of all the PCI irqs mapped
502a5395
PB
252 to it */
253 pic_level = 0;
d2b59317 254 for (i = 0; i < 4; i++) {
fd37d881 255 if (pic_irq == piix3_dev->dev.config[0x60 + i])
d2b59317
PB
256 pic_level |= pci_irq_levels[i];
257 }
d537cf6c 258 qemu_set_irq(pic[pic_irq], pic_level);
502a5395
PB
259 }
260}
261
15a1956a 262static void piix3_reset(void *opaque)
502a5395 263{
fd37d881
JQ
264 PIIX3State *d = opaque;
265 uint8_t *pci_conf = d->dev.config;
502a5395
PB
266
267 pci_conf[0x04] = 0x07; // master, memory and I/O
268 pci_conf[0x05] = 0x00;
269 pci_conf[0x06] = 0x00;
270 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
271 pci_conf[0x4c] = 0x4d;
272 pci_conf[0x4e] = 0x03;
273 pci_conf[0x4f] = 0x00;
274 pci_conf[0x60] = 0x80;
477afee3
AJ
275 pci_conf[0x61] = 0x80;
276 pci_conf[0x62] = 0x80;
277 pci_conf[0x63] = 0x80;
502a5395
PB
278 pci_conf[0x69] = 0x02;
279 pci_conf[0x70] = 0x80;
280 pci_conf[0x76] = 0x0c;
281 pci_conf[0x77] = 0x0c;
282 pci_conf[0x78] = 0x02;
283 pci_conf[0x79] = 0x00;
284 pci_conf[0x80] = 0x00;
285 pci_conf[0x82] = 0x00;
286 pci_conf[0xa0] = 0x08;
502a5395
PB
287 pci_conf[0xa2] = 0x00;
288 pci_conf[0xa3] = 0x00;
289 pci_conf[0xa4] = 0x00;
290 pci_conf[0xa5] = 0x00;
291 pci_conf[0xa6] = 0x00;
292 pci_conf[0xa7] = 0x00;
293 pci_conf[0xa8] = 0x0f;
294 pci_conf[0xaa] = 0x00;
295 pci_conf[0xab] = 0x00;
296 pci_conf[0xac] = 0x00;
297 pci_conf[0xae] = 0x00;
15a1956a
GN
298
299 memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
502a5395
PB
300}
301
1941d19c
FB
302static void piix_save(QEMUFile* f, void *opaque)
303{
304 PCIDevice *d = opaque;
305 pci_device_save(d, f);
306}
307
308static int piix_load(QEMUFile* f, void *opaque, int version_id)
309{
310 PCIDevice *d = opaque;
311 if (version_id != 2)
312 return -EINVAL;
313 return pci_device_load(d, f);
314}
315
fd37d881 316static int piix3_initfn(PCIDevice *dev)
502a5395 317{
fd37d881 318 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
502a5395
PB
319 uint8_t *pci_conf;
320
fd37d881 321 isa_bus_new(&d->dev.qdev);
1941d19c 322 register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
502a5395 323
fd37d881 324 pci_conf = d->dev.config;
deb54399
AL
325 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
326 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
173a543b 327 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
6407f373
IY
328 pci_conf[PCI_HEADER_TYPE] =
329 PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
502a5395 330
8a14daa5 331 piix3_dev = d;
502a5395 332 piix3_reset(d);
a08d4367 333 qemu_register_reset(piix3_reset, d);
81a322d4 334 return 0;
502a5395 335}
5c2b87e3 336
8a14daa5
GH
337int piix3_init(PCIBus *bus, int devfn)
338{
339 PCIDevice *d;
340
341 d = pci_create_simple(bus, devfn, "PIIX3");
5c2b87e3
TS
342 return d->devfn;
343}
8a14daa5 344
8a14daa5
GH
345static PCIDeviceInfo i440fx_info[] = {
346 {
347 .qdev.name = "i440FX",
348 .qdev.desc = "Host bridge",
0a3bacf3 349 .qdev.size = sizeof(PCII440FXState),
8a14daa5
GH
350 .qdev.no_user = 1,
351 .init = i440fx_initfn,
352 .config_write = i440fx_write_config,
353 },{
354 .qdev.name = "PIIX3",
355 .qdev.desc = "ISA bridge",
fd37d881 356 .qdev.size = sizeof(PIIX3State),
8a14daa5
GH
357 .qdev.no_user = 1,
358 .init = piix3_initfn,
8a14daa5
GH
359 },{
360 /* end of list */
361 }
362};
363
364static SysBusDeviceInfo i440fx_pcihost_info = {
365 .init = i440fx_pcihost_initfn,
366 .qdev.name = "i440FX-pcihost",
367 .qdev.size = sizeof(I440FXState),
368 .qdev.no_user = 1,
369};
370
371static void i440fx_register(void)
372{
373 sysbus_register_withprop(&i440fx_pcihost_info);
374 pci_qdev_register_many(i440fx_info);
375}
376device_init(i440fx_register);