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1 | /* |
2 | * ARM AMBA PrimeCell PL031 RTC | |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery | |
5 | * | |
6 | * This file is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
87ecb68b PB |
12 | #include "hw.h" |
13 | #include "primecell.h" | |
14 | #include "qemu-timer.h" | |
15 | #include "sysemu.h" | |
7e1543c2 PB |
16 | |
17 | //#define DEBUG_PL031 | |
18 | ||
19 | #ifdef DEBUG_PL031 | |
20 | #define DPRINTF(fmt, args...) \ | |
21 | do { printf("pl031: " fmt , ##args); } while (0) | |
22 | #else | |
23 | #define DPRINTF(fmt, args...) do {} while(0) | |
24 | #endif | |
25 | ||
26 | #define RTC_DR 0x00 /* Data read register */ | |
27 | #define RTC_MR 0x04 /* Match register */ | |
28 | #define RTC_LR 0x08 /* Data load register */ | |
29 | #define RTC_CR 0x0c /* Control register */ | |
30 | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ | |
31 | #define RTC_RIS 0x14 /* Raw interrupt status register */ | |
32 | #define RTC_MIS 0x18 /* Masked interrupt status register */ | |
33 | #define RTC_ICR 0x1c /* Interrupt clear register */ | |
34 | ||
35 | typedef struct { | |
36 | QEMUTimer *timer; | |
37 | qemu_irq irq; | |
7e1543c2 | 38 | |
7e1543c2 PB |
39 | uint32_t tick_offset; |
40 | ||
41 | uint32_t mr; | |
42 | uint32_t lr; | |
43 | uint32_t cr; | |
44 | uint32_t im; | |
45 | uint32_t is; | |
46 | } pl031_state; | |
47 | ||
48 | static const unsigned char pl031_id[] = { | |
49 | 0x31, 0x10, 0x14, 0x00, /* Device ID */ | |
50 | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ | |
51 | }; | |
52 | ||
53 | static void pl031_update(pl031_state *s) | |
54 | { | |
55 | qemu_set_irq(s->irq, s->is & s->im); | |
56 | } | |
57 | ||
58 | static void pl031_interrupt(void * opaque) | |
59 | { | |
60 | pl031_state *s = (pl031_state *)opaque; | |
61 | ||
62 | s->im = 1; | |
63 | DPRINTF("Alarm raised\n"); | |
64 | pl031_update(s); | |
65 | } | |
66 | ||
67 | static uint32_t pl031_get_count(pl031_state *s) | |
68 | { | |
69 | /* This assumes qemu_get_clock returns the time since the machine was | |
70 | created. */ | |
71 | return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec; | |
72 | } | |
73 | ||
74 | static void pl031_set_alarm(pl031_state *s) | |
75 | { | |
76 | int64_t now; | |
77 | uint32_t ticks; | |
78 | ||
79 | now = qemu_get_clock(vm_clock); | |
80 | ticks = s->tick_offset + now / ticks_per_sec; | |
81 | ||
82 | /* The timer wraps around. This subtraction also wraps in the same way, | |
83 | and gives correct results when alarm < now_ticks. */ | |
84 | ticks = s->mr - ticks; | |
85 | DPRINTF("Alarm set in %ud ticks\n", ticks); | |
86 | if (ticks == 0) { | |
87 | qemu_del_timer(s->timer); | |
88 | pl031_interrupt(s); | |
89 | } else { | |
90 | qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec); | |
91 | } | |
92 | } | |
93 | ||
94 | static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) | |
95 | { | |
96 | pl031_state *s = (pl031_state *)opaque; | |
97 | ||
7e1543c2 PB |
98 | if (offset >= 0xfe0 && offset < 0x1000) |
99 | return pl031_id[(offset - 0xfe0) >> 2]; | |
100 | ||
101 | switch (offset) { | |
102 | case RTC_DR: | |
103 | return pl031_get_count(s); | |
104 | case RTC_MR: | |
105 | return s->mr; | |
106 | case RTC_IMSC: | |
107 | return s->im; | |
108 | case RTC_RIS: | |
109 | return s->is; | |
110 | case RTC_LR: | |
111 | return s->lr; | |
112 | case RTC_CR: | |
113 | /* RTC is permanently enabled. */ | |
114 | return 1; | |
115 | case RTC_MIS: | |
116 | return s->is & s->im; | |
117 | case RTC_ICR: | |
118 | fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n", | |
119 | (int)offset); | |
120 | break; | |
121 | default: | |
122 | cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n", | |
123 | (int)offset); | |
124 | break; | |
125 | } | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
130 | static void pl031_write(void * opaque, target_phys_addr_t offset, | |
131 | uint32_t value) | |
132 | { | |
133 | pl031_state *s = (pl031_state *)opaque; | |
134 | ||
7e1543c2 PB |
135 | |
136 | switch (offset) { | |
137 | case RTC_LR: | |
138 | s->tick_offset += value - pl031_get_count(s); | |
139 | pl031_set_alarm(s); | |
140 | break; | |
141 | case RTC_MR: | |
142 | s->mr = value; | |
143 | pl031_set_alarm(s); | |
144 | break; | |
145 | case RTC_IMSC: | |
146 | s->im = value & 1; | |
147 | DPRINTF("Interrupt mask %d\n", s->im); | |
148 | pl031_update(s); | |
149 | break; | |
150 | case RTC_ICR: | |
151 | /* The PL031 documentation (DDI0224B) states that the interupt is | |
152 | cleared when bit 0 of the written value is set. However the | |
153 | arm926e documentation (DDI0287B) states that the interrupt is | |
154 | cleared when any value is written. */ | |
155 | DPRINTF("Interrupt cleared"); | |
156 | s->is = 0; | |
157 | pl031_update(s); | |
158 | break; | |
159 | case RTC_CR: | |
160 | /* Written value is ignored. */ | |
161 | break; | |
162 | ||
163 | case RTC_DR: | |
164 | case RTC_MIS: | |
165 | case RTC_RIS: | |
166 | fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n", | |
167 | (int)offset); | |
168 | break; | |
169 | ||
170 | default: | |
171 | cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n", | |
172 | (int)offset); | |
173 | break; | |
174 | } | |
175 | } | |
176 | ||
177 | static CPUWriteMemoryFunc * pl031_writefn[] = { | |
178 | pl031_write, | |
179 | pl031_write, | |
180 | pl031_write | |
181 | }; | |
182 | ||
183 | static CPUReadMemoryFunc * pl031_readfn[] = { | |
184 | pl031_read, | |
185 | pl031_read, | |
186 | pl031_read | |
187 | }; | |
188 | ||
189 | void pl031_init(uint32_t base, qemu_irq irq) | |
190 | { | |
191 | int iomemtype; | |
192 | pl031_state *s; | |
f6503059 | 193 | struct tm tm; |
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194 | |
195 | s = qemu_mallocz(sizeof(pl031_state)); | |
196 | if (!s) | |
197 | cpu_abort(cpu_single_env, "pl031_init: Out of memory\n"); | |
198 | ||
199 | iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s); | |
200 | if (iomemtype == -1) | |
201 | cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n"); | |
202 | ||
203 | cpu_register_physical_memory(base, 0x00001000, iomemtype); | |
204 | ||
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205 | s->irq = irq; |
206 | /* ??? We assume vm_clock is zero at this point. */ | |
f6503059 | 207 | qemu_get_timedate(&tm, 0); |
0cd2df75 | 208 | s->tick_offset = mktimegm(&tm); |
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209 | |
210 | s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); | |
211 | } |