[mirror_qemu.git] / hw / pl031.c

/*
 * ARM AMBA PrimeCell PL031 RTC
 *
 * Copyright (c) 2007 CodeSourcery
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "sysbus.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"

//#define DEBUG_PL031

#ifdef DEBUG_PL031
#define DPRINTF(fmt, ...) \
do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#endif

#define RTC_DR      0x00    /* Data read register */
#define RTC_MR      0x04    /* Match register */
#define RTC_LR      0x08    /* Data load register */
#define RTC_CR      0x0c    /* Control register */
#define RTC_IMSC    0x10    /* Interrupt mask and set register */
#define RTC_RIS     0x14    /* Raw interrupt status register */
#define RTC_MIS     0x18    /* Masked interrupt status register */
#define RTC_ICR     0x1c    /* Interrupt clear register */

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    QEMUTimer *timer;
    qemu_irq irq;

    /* Needed to preserve the tick_count across migration, even if the
     * absolute value of the rtc_clock is different on the source and
     * destination.
     */
    uint32_t tick_offset_vmstate;
    uint32_t tick_offset;

    uint32_t mr;
    uint32_t lr;
    uint32_t cr;
    uint32_t im;
    uint32_t is;
} pl031_state;

static const unsigned char pl031_id[] = {
    0x31, 0x10, 0x14, 0x00,         /* Device ID        */
    0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
};

static void pl031_update(pl031_state *s)
{
    qemu_set_irq(s->irq, s->is & s->im);
}

static void pl031_interrupt(void * opaque)
{
    pl031_state *s = (pl031_state *)opaque;

    s->is = 1;
    DPRINTF("Alarm raised\n");
    pl031_update(s);
}

static uint32_t pl031_get_count(pl031_state *s)
{
    int64_t now = qemu_get_clock_ns(rtc_clock);
    return s->tick_offset + now / get_ticks_per_sec();
}

static void pl031_set_alarm(pl031_state *s)
{
    uint32_t ticks;

    /* The timer wraps around.  This subtraction also wraps in the same way,
       and gives correct results when alarm < now_ticks.  */
    ticks = s->mr - pl031_get_count(s);
    DPRINTF("Alarm set in %ud ticks\n", ticks);
    if (ticks == 0) {
        qemu_del_timer(s->timer);
        pl031_interrupt(s);
    } else {
        int64_t now = qemu_get_clock_ns(rtc_clock);
        qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
    }
}

static uint64_t pl031_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    pl031_state *s = (pl031_state *)opaque;

    if (offset >= 0xfe0  &&  offset < 0x1000)
        return pl031_id[(offset - 0xfe0) >> 2];

    switch (offset) {
    case RTC_DR:
        return pl031_get_count(s);
    case RTC_MR:
        return s->mr;
    case RTC_IMSC:
        return s->im;
    case RTC_RIS:
        return s->is;
    case RTC_LR:
        return s->lr;
    case RTC_CR:
        /* RTC is permanently enabled.  */
        return 1;
    case RTC_MIS:
        return s->is & s->im;
    case RTC_ICR:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031: read of write-only register at offset 0x%x\n",
                      (int)offset);
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031_read: Bad offset 0x%x\n", (int)offset);
        break;
    }

    return 0;
}

static void pl031_write(void * opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    pl031_state *s = (pl031_state *)opaque;


    switch (offset) {
    case RTC_LR:
        s->tick_offset += value - pl031_get_count(s);
        pl031_set_alarm(s);
        break;
    case RTC_MR:
        s->mr = value;
        pl031_set_alarm(s);
        break;
    case RTC_IMSC:
        s->im = value & 1;
        DPRINTF("Interrupt mask %d\n", s->im);
        pl031_update(s);
        break;
    case RTC_ICR:
        /* The PL031 documentation (DDI0224B) states that the interrupt is
           cleared when bit 0 of the written value is set.  However the
           arm926e documentation (DDI0287B) states that the interrupt is
           cleared when any value is written.  */
        DPRINTF("Interrupt cleared");
        s->is = 0;
        pl031_update(s);
        break;
    case RTC_CR:
        /* Written value is ignored.  */
        break;

    case RTC_DR:
    case RTC_MIS:
    case RTC_RIS:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031: write to read-only register at offset 0x%x\n",
                      (int)offset);
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl031_write: Bad offset 0x%x\n", (int)offset);
        break;
    }
}

static const MemoryRegionOps pl031_ops = {
    .read = pl031_read,
    .write = pl031_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pl031_init(SysBusDevice *dev)
{
    pl031_state *s = FROM_SYSBUS(pl031_state, dev);
    struct tm tm;

    memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_irq(dev, &s->irq);
    qemu_get_timedate(&tm, 0);
    s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();

    s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
    return 0;
}

static void pl031_pre_save(void *opaque)
{
    pl031_state *s = opaque;

    /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
     * store the base time relative to the vm_clock for backwards-compatibility.  */
    int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
    s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
}

static int pl031_post_load(void *opaque, int version_id)
{
    pl031_state *s = opaque;

    int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
    s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
    pl031_set_alarm(s);
    return 0;
}

static const VMStateDescription vmstate_pl031 = {
    .name = "pl031",
    .version_id = 1,
    .minimum_version_id = 1,
    .pre_save = pl031_pre_save,
    .post_load = pl031_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
        VMSTATE_UINT32(mr, pl031_state),
        VMSTATE_UINT32(lr, pl031_state),
        VMSTATE_UINT32(cr, pl031_state),
        VMSTATE_UINT32(im, pl031_state),
        VMSTATE_UINT32(is, pl031_state),
        VMSTATE_END_OF_LIST()
    }
};

static void pl031_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl031_init;
    dc->no_user = 1;
    dc->vmsd = &vmstate_pl031;
}

static const TypeInfo pl031_info = {
    .name          = "pl031",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(pl031_state),
    .class_init    = pl031_class_init,
};

static void pl031_register_types(void)
{
    type_register_static(&pl031_info);
}

type_init(pl031_register_types)
Commit	Line	Data
7e1543c2 PB	1	/*
	2	* ARM AMBA PrimeCell PL031 RTC
	3	*
	4	* Copyright (c) 2007 CodeSourcery
	5	*
	6	* This file is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
6b620ca3 PB	10	* Contributions after 2012-01-13 are licensed under the terms of the
6b620ca3 PB	11	* GNU GPL, version 2 or (at your option) any later version.
7e1543c2 PB	12	*/
7e1543c2 PB	13
a63bdb31	14	#include "sysbus.h"
1de7afc9	15	#include "qemu/timer.h"
9c17d615	16	#include "sysemu/sysemu.h"
7e1543c2 PB	17
	18	//#define DEBUG_PL031
	19
	20	#ifdef DEBUG_PL031
001faf32 BS	21	#define DPRINTF(fmt, ...) \
001faf32 BS	22	do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
7e1543c2	23	#else
001faf32	24	#define DPRINTF(fmt, ...) do {} while(0)
7e1543c2 PB	25	#endif
	26
	27	#define RTC_DR 0x00 /* Data read register */
	28	#define RTC_MR 0x04 /* Match register */
	29	#define RTC_LR 0x08 /* Data load register */
	30	#define RTC_CR 0x0c /* Control register */
	31	#define RTC_IMSC 0x10 /* Interrupt mask and set register */
	32	#define RTC_RIS 0x14 /* Raw interrupt status register */
	33	#define RTC_MIS 0x18 /* Masked interrupt status register */
	34	#define RTC_ICR 0x1c /* Interrupt clear register */
	35
	36	typedef struct {
a63bdb31	37	SysBusDevice busdev;
9edbe481	38	MemoryRegion iomem;
7e1543c2 PB	39	QEMUTimer *timer;
7e1543c2 PB	40	qemu_irq irq;
7e1543c2	41
b0f26631 PB	42	/* Needed to preserve the tick_count across migration, even if the
	43	* absolute value of the rtc_clock is different on the source and
	44	* destination.
	45	*/
	46	uint32_t tick_offset_vmstate;
7e1543c2 PB	47	uint32_t tick_offset;
	48
	49	uint32_t mr;
	50	uint32_t lr;
	51	uint32_t cr;
	52	uint32_t im;
	53	uint32_t is;
	54	} pl031_state;
	55
	56	static const unsigned char pl031_id[] = {
	57	0x31, 0x10, 0x14, 0x00, /* Device ID */
	58	0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
	59	};
	60
	61	static void pl031_update(pl031_state *s)
	62	{
	63	qemu_set_irq(s->irq, s->is & s->im);
	64	}
	65
	66	static void pl031_interrupt(void * opaque)
	67	{
	68	pl031_state s = (pl031_state )opaque;
	69
13a16f1d	70	s->is = 1;
7e1543c2 PB	71	DPRINTF("Alarm raised\n");
	72	pl031_update(s);
	73	}
	74
	75	static uint32_t pl031_get_count(pl031_state *s)
	76	{
b0f26631 PB	77	int64_t now = qemu_get_clock_ns(rtc_clock);
b0f26631 PB	78	return s->tick_offset + now / get_ticks_per_sec();
7e1543c2 PB	79	}
	80
	81	static void pl031_set_alarm(pl031_state *s)
	82	{
7e1543c2 PB	83	uint32_t ticks;
7e1543c2 PB	84
7e1543c2 PB	85	/* The timer wraps around. This subtraction also wraps in the same way,
7e1543c2 PB	86	and gives correct results when alarm < now_ticks. */
b0f26631	87	ticks = s->mr - pl031_get_count(s);
7e1543c2 PB	88	DPRINTF("Alarm set in %ud ticks\n", ticks);
	89	if (ticks == 0) {
	90	qemu_del_timer(s->timer);
	91	pl031_interrupt(s);
	92	} else {
b0f26631	93	int64_t now = qemu_get_clock_ns(rtc_clock);
6ee093c9	94	qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
7e1543c2 PB	95	}
	96	}
	97
a8170e5e	98	static uint64_t pl031_read(void *opaque, hwaddr offset,
9edbe481	99	unsigned size)
7e1543c2 PB	100	{
	101	pl031_state s = (pl031_state )opaque;
	102
7e1543c2 PB	103	if (offset >= 0xfe0 && offset < 0x1000)
	104	return pl031_id[(offset - 0xfe0) >> 2];
	105
	106	switch (offset) {
	107	case RTC_DR:
	108	return pl031_get_count(s);
	109	case RTC_MR:
	110	return s->mr;
	111	case RTC_IMSC:
	112	return s->im;
	113	case RTC_RIS:
	114	return s->is;
	115	case RTC_LR:
	116	return s->lr;
	117	case RTC_CR:
	118	/* RTC is permanently enabled. */
	119	return 1;
	120	case RTC_MIS:
	121	return s->is & s->im;
	122	case RTC_ICR:
a5089c05 PM	123	qemu_log_mask(LOG_GUEST_ERROR,
	124	"pl031: read of write-only register at offset 0x%x\n",
	125	(int)offset);
7e1543c2 PB	126	break;
7e1543c2 PB	127	default:
a5089c05 PM	128	qemu_log_mask(LOG_GUEST_ERROR,
a5089c05 PM	129	"pl031_read: Bad offset 0x%x\n", (int)offset);
7e1543c2 PB	130	break;
	131	}
	132
	133	return 0;
	134	}
	135
a8170e5e	136	static void pl031_write(void * opaque, hwaddr offset,
9edbe481	137	uint64_t value, unsigned size)
7e1543c2 PB	138	{
	139	pl031_state s = (pl031_state )opaque;
	140
7e1543c2 PB	141
	142	switch (offset) {
	143	case RTC_LR:
	144	s->tick_offset += value - pl031_get_count(s);
	145	pl031_set_alarm(s);
	146	break;
	147	case RTC_MR:
	148	s->mr = value;
	149	pl031_set_alarm(s);
	150	break;
	151	case RTC_IMSC:
	152	s->im = value & 1;
	153	DPRINTF("Interrupt mask %d\n", s->im);
	154	pl031_update(s);
	155	break;
	156	case RTC_ICR:
ff2712ba	157	/* The PL031 documentation (DDI0224B) states that the interrupt is
7e1543c2 PB	158	cleared when bit 0 of the written value is set. However the
	159	arm926e documentation (DDI0287B) states that the interrupt is
	160	cleared when any value is written. */
	161	DPRINTF("Interrupt cleared");
	162	s->is = 0;
	163	pl031_update(s);
	164	break;
	165	case RTC_CR:
	166	/* Written value is ignored. */
	167	break;
	168
	169	case RTC_DR:
	170	case RTC_MIS:
	171	case RTC_RIS:
a5089c05 PM	172	qemu_log_mask(LOG_GUEST_ERROR,
	173	"pl031: write to read-only register at offset 0x%x\n",
	174	(int)offset);
7e1543c2 PB	175	break;
	176
	177	default:
a5089c05 PM	178	qemu_log_mask(LOG_GUEST_ERROR,
a5089c05 PM	179	"pl031_write: Bad offset 0x%x\n", (int)offset);
7e1543c2 PB	180	break;
	181	}
	182	}
	183
9edbe481 AK	184	static const MemoryRegionOps pl031_ops = {
	185	.read = pl031_read,
	186	.write = pl031_write,
	187	.endianness = DEVICE_NATIVE_ENDIAN,
7e1543c2 PB	188	};
7e1543c2 PB	189
81a322d4	190	static int pl031_init(SysBusDevice *dev)
7e1543c2	191	{
a63bdb31	192	pl031_state *s = FROM_SYSBUS(pl031_state, dev);
f6503059	193	struct tm tm;
7e1543c2	194
9edbe481	195	memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
750ecd44	196	sysbus_init_mmio(dev, &s->iomem);
7e1543c2	197
a63bdb31	198	sysbus_init_irq(dev, &s->irq);
f6503059	199	qemu_get_timedate(&tm, 0);
b0f26631	200	s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
7e1543c2	201
b0f26631	202	s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
81a322d4	203	return 0;
7e1543c2	204	}
a63bdb31	205
b0f26631 PB	206	static void pl031_pre_save(void *opaque)
	207	{
	208	pl031_state *s = opaque;
	209
	210	/* tick_offset is base_time - rtc_clock base time. Instead, we want to
	211	* store the base time relative to the vm_clock for backwards-compatibility. */
	212	int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
	213	s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
	214	}
	215
ac204b8f PB	216	static int pl031_post_load(void *opaque, int version_id)
	217	{
	218	pl031_state *s = opaque;
	219
b0f26631 PB	220	int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
b0f26631 PB	221	s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
ac204b8f PB	222	pl031_set_alarm(s);
	223	return 0;
	224	}
	225
	226	static const VMStateDescription vmstate_pl031 = {
	227	.name = "pl031",
	228	.version_id = 1,
	229	.minimum_version_id = 1,
b0f26631	230	.pre_save = pl031_pre_save,
ac204b8f PB	231	.post_load = pl031_post_load,
ac204b8f PB	232	.fields = (VMStateField[]) {
b0f26631	233	VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
ac204b8f PB	234	VMSTATE_UINT32(mr, pl031_state),
	235	VMSTATE_UINT32(lr, pl031_state),
	236	VMSTATE_UINT32(cr, pl031_state),
	237	VMSTATE_UINT32(im, pl031_state),
	238	VMSTATE_UINT32(is, pl031_state),
	239	VMSTATE_END_OF_LIST()
	240	}
	241	};
	242
999e12bb AL	243	static void pl031_class_init(ObjectClass klass, void data)
999e12bb AL	244	{
39bffca2	245	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	246	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	247
	248	k->init = pl031_init;
39bffca2 AL	249	dc->no_user = 1;
39bffca2 AL	250	dc->vmsd = &vmstate_pl031;
999e12bb AL	251	}
999e12bb AL	252
8c43a6f0	253	static const TypeInfo pl031_info = {
39bffca2 AL	254	.name = "pl031",
	255	.parent = TYPE_SYS_BUS_DEVICE,
	256	.instance_size = sizeof(pl031_state),
	257	.class_init = pl031_class_init,
0dc5595c PM	258	};
0dc5595c PM	259
83f7d43a	260	static void pl031_register_types(void)
a63bdb31	261	{
39bffca2	262	type_register_static(&pl031_info);
a63bdb31 PB	263	}
a63bdb31 PB	264
83f7d43a	265	type_init(pl031_register_types)