[mirror_qemu.git] / hw / pl190.c

/*
 * Arm PrimeCell PL190 Vector Interrupt Controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

/* The number of virtual priority levels.  16 user vectors plus the
   unvectored IRQ.  Chained interrupts would require an additional level
   if implemented.  */

#define PL190_NUM_PRIO 17

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    uint32_t level;
    uint32_t soft_level;
    uint32_t irq_enable;
    uint32_t fiq_select;
    uint8_t vect_control[16];
    uint32_t vect_addr[PL190_NUM_PRIO];
    /* Mask containing interrupts with higher priority than this one.  */
    uint32_t prio_mask[PL190_NUM_PRIO + 1];
    int protected;
    /* Current priority level.  */
    int priority;
    int prev_prio[PL190_NUM_PRIO];
    qemu_irq irq;
    qemu_irq fiq;
} pl190_state;

static const unsigned char pl190_id[] =
{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };

static inline uint32_t pl190_irq_level(pl190_state *s)
{
    return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
}

/* Update interrupts.  */
static void pl190_update(pl190_state *s)
{
    uint32_t level = pl190_irq_level(s);
    int set;

    set = (level & s->prio_mask[s->priority]) != 0;
    qemu_set_irq(s->irq, set);
    set = ((s->level | s->soft_level) & s->fiq_select) != 0;
    qemu_set_irq(s->fiq, set);
}

static void pl190_set_irq(void *opaque, int irq, int level)
{
    pl190_state *s = (pl190_state *)opaque;

    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    pl190_update(s);
}

static void pl190_update_vectors(pl190_state *s)
{
    uint32_t mask;
    int i;
    int n;

    mask = 0;
    for (i = 0; i < 16; i++)
      {
        s->prio_mask[i] = mask;
        if (s->vect_control[i] & 0x20)
          {
            n = s->vect_control[i] & 0x1f;
            mask |= 1 << n;
          }
      }
    s->prio_mask[16] = mask;
    pl190_update(s);
}

static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
                           unsigned size)
{
    pl190_state *s = (pl190_state *)opaque;
    int i;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl190_id[(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x100 && offset < 0x140) {
        return s->vect_addr[(offset - 0x100) >> 2];
    }
    if (offset >= 0x200 && offset < 0x240) {
        return s->vect_control[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* IRQSTATUS */
        return pl190_irq_level(s);
    case 1: /* FIQSATUS */
        return (s->level | s->soft_level) & s->fiq_select;
    case 2: /* RAWINTR */
        return s->level | s->soft_level;
    case 3: /* INTSELECT */
        return s->fiq_select;
    case 4: /* INTENABLE */
        return s->irq_enable;
    case 6: /* SOFTINT */
        return s->soft_level;
    case 8: /* PROTECTION */
        return s->protected;
    case 12: /* VECTADDR */
        /* Read vector address at the start of an ISR.  Increases the
           current priority level to that of the current interrupt.  */
        for (i = 0; i < s->priority; i++)
          {
            if ((s->level | s->soft_level) & s->prio_mask[i])
              break;
          }
        /* Reading this value with no pending interrupts is undefined.
           We return the default address.  */
        if (i == PL190_NUM_PRIO)
          return s->vect_addr[16];
        if (i < s->priority)
          {
            s->prev_prio[i] = s->priority;
            s->priority = i;
            pl190_update(s);
          }
        return s->vect_addr[s->priority];
    case 13: /* DEFVECTADDR */
        return s->vect_addr[16];
    default:
        hw_error("pl190_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl190_write(void *opaque, target_phys_addr_t offset,
                        uint64_t val, unsigned size)
{
    pl190_state *s = (pl190_state *)opaque;

    if (offset >= 0x100 && offset < 0x140) {
        s->vect_addr[(offset - 0x100) >> 2] = val;
        pl190_update_vectors(s);
        return;
    }
    if (offset >= 0x200 && offset < 0x240) {
        s->vect_control[(offset - 0x200) >> 2] = val;
        pl190_update_vectors(s);
        return;
    }
    switch (offset >> 2) {
    case 0: /* SELECT */
        /* This is a readonly register, but linux tries to write to it
           anyway.  Ignore the write.  */
        break;
    case 3: /* INTSELECT */
        s->fiq_select = val;
        break;
    case 4: /* INTENABLE */
        s->irq_enable |= val;
        break;
    case 5: /* INTENCLEAR */
        s->irq_enable &= ~val;
        break;
    case 6: /* SOFTINT */
        s->soft_level |= val;
        break;
    case 7: /* SOFTINTCLEAR */
        s->soft_level &= ~val;
        break;
    case 8: /* PROTECTION */
        /* TODO: Protection (supervisor only access) is not implemented.  */
        s->protected = val & 1;
        break;
    case 12: /* VECTADDR */
        /* Restore the previous priority level.  The value written is
           ignored.  */
        if (s->priority < PL190_NUM_PRIO)
            s->priority = s->prev_prio[s->priority];
        break;
    case 13: /* DEFVECTADDR */
        s->vect_addr[16] = val;
        break;
    case 0xc0: /* ITCR */
        if (val) {
            hw_error("pl190: Test mode not implemented\n");
        }
        break;
    default:
        hw_error("pl190_write: Bad offset %x\n", (int)offset);
        return;
    }
    pl190_update(s);
}

static const MemoryRegionOps pl190_ops = {
    .read = pl190_read,
    .write = pl190_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl190_reset(DeviceState *d)
{
  pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
  int i;

  for (i = 0; i < 16; i++)
    {
      s->vect_addr[i] = 0;
      s->vect_control[i] = 0;
    }
  s->vect_addr[16] = 0;
  s->prio_mask[17] = 0xffffffff;
  s->priority = PL190_NUM_PRIO;
  pl190_update_vectors(s);
}

static int pl190_init(SysBusDevice *dev)
{
    pl190_state *s = FROM_SYSBUS(pl190_state, dev);

    memory_region_init_io(&s->iomem, &pl190_ops, s, "pl190", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fiq);
    return 0;
}

static const VMStateDescription vmstate_pl190 = {
    .name = "pl190",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, pl190_state),
        VMSTATE_UINT32(soft_level, pl190_state),
        VMSTATE_UINT32(irq_enable, pl190_state),
        VMSTATE_UINT32(fiq_select, pl190_state),
        VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
        VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
        VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
        VMSTATE_INT32(protected, pl190_state),
        VMSTATE_INT32(priority, pl190_state),
        VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
        VMSTATE_END_OF_LIST()
    }
};

static void pl190_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pl190_init;
    dc->no_user = 1;
    dc->reset = pl190_reset;
    dc->vmsd = &vmstate_pl190;
}

static TypeInfo pl190_info = {
    .name          = "pl190",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(pl190_state),
    .class_init    = pl190_class_init,
};

static void pl190_register_types(void)
{
    type_register_static(&pl190_info);
}

type_init(pl190_register_types)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* Arm PrimeCell PL190 Vector Interrupt Controller
	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
97aff481	10	#include "sysbus.h"
cdbdb648 PB	11
	12	/* The number of virtual priority levels. 16 user vectors plus the
	13	unvectored IRQ. Chained interrupts would require an additional level
	14	if implemented. */
	15
	16	#define PL190_NUM_PRIO 17
	17
	18	typedef struct {
97aff481	19	SysBusDevice busdev;
7f8293bf	20	MemoryRegion iomem;
cdbdb648 PB	21	uint32_t level;
	22	uint32_t soft_level;
	23	uint32_t irq_enable;
	24	uint32_t fiq_select;
cdbdb648 PB	25	uint8_t vect_control[16];
	26	uint32_t vect_addr[PL190_NUM_PRIO];
	27	/* Mask containing interrupts with higher priority than this one. */
	28	uint32_t prio_mask[PL190_NUM_PRIO + 1];
	29	int protected;
	30	/* Current priority level. */
	31	int priority;
	32	int prev_prio[PL190_NUM_PRIO];
d537cf6c PB	33	qemu_irq irq;
d537cf6c PB	34	qemu_irq fiq;
cdbdb648 PB	35	} pl190_state;
	36
	37	static const unsigned char pl190_id[] =
	38	{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
	39
	40	static inline uint32_t pl190_irq_level(pl190_state *s)
	41	{
	42	return (s->level \| s->soft_level) & s->irq_enable & ~s->fiq_select;
	43	}
	44
	45	/* Update interrupts. */
	46	static void pl190_update(pl190_state *s)
	47	{
	48	uint32_t level = pl190_irq_level(s);
	49	int set;
	50
	51	set = (level & s->prio_mask[s->priority]) != 0;
d537cf6c	52	qemu_set_irq(s->irq, set);
cdbdb648	53	set = ((s->level \| s->soft_level) & s->fiq_select) != 0;
d537cf6c	54	qemu_set_irq(s->fiq, set);
cdbdb648 PB	55	}
	56
	57	static void pl190_set_irq(void *opaque, int irq, int level)
	58	{
	59	pl190_state s = (pl190_state )opaque;
	60
	61	if (level)
	62	s->level \|= 1u << irq;
	63	else
	64	s->level &= ~(1u << irq);
	65	pl190_update(s);
	66	}
	67
	68	static void pl190_update_vectors(pl190_state *s)
	69	{
	70	uint32_t mask;
	71	int i;
	72	int n;
	73
	74	mask = 0;
	75	for (i = 0; i < 16; i++)
	76	{
	77	s->prio_mask[i] = mask;
	78	if (s->vect_control[i] & 0x20)
	79	{
	80	n = s->vect_control[i] & 0x1f;
	81	mask \|= 1 << n;
	82	}
	83	}
	84	s->prio_mask[16] = mask;
	85	pl190_update(s);
	86	}
	87
7f8293bf AK	88	static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
7f8293bf AK	89	unsigned size)
cdbdb648 PB	90	{
	91	pl190_state s = (pl190_state )opaque;
	92	int i;
	93
cdbdb648 PB	94	if (offset >= 0xfe0 && offset < 0x1000) {
	95	return pl190_id[(offset - 0xfe0) >> 2];
	96	}
	97	if (offset >= 0x100 && offset < 0x140) {
	98	return s->vect_addr[(offset - 0x100) >> 2];
	99	}
	100	if (offset >= 0x200 && offset < 0x240) {
	101	return s->vect_control[(offset - 0x200) >> 2];
	102	}
	103	switch (offset >> 2) {
	104	case 0: /* IRQSTATUS */
	105	return pl190_irq_level(s);
	106	case 1: /* FIQSATUS */
	107	return (s->level \| s->soft_level) & s->fiq_select;
	108	case 2: /* RAWINTR */
	109	return s->level \| s->soft_level;
	110	case 3: /* INTSELECT */
	111	return s->fiq_select;
	112	case 4: /* INTENABLE */
	113	return s->irq_enable;
	114	case 6: /* SOFTINT */
	115	return s->soft_level;
	116	case 8: /* PROTECTION */
	117	return s->protected;
	118	case 12: /* VECTADDR */
	119	/* Read vector address at the start of an ISR. Increases the
	120	current priority level to that of the current interrupt. */
	121	for (i = 0; i < s->priority; i++)
	122	{
	123	if ((s->level \| s->soft_level) & s->prio_mask[i])
	124	break;
	125	}
	126	/* Reading this value with no pending interrupts is undefined.
	127	We return the default address. */
	128	if (i == PL190_NUM_PRIO)
	129	return s->vect_addr[16];
	130	if (i < s->priority)
	131	{
	132	s->prev_prio[i] = s->priority;
	133	s->priority = i;
	134	pl190_update(s);
	135	}
	136	return s->vect_addr[s->priority];
	137	case 13: /* DEFVECTADDR */
	138	return s->vect_addr[16];
	139	default:
2ac71179	140	hw_error("pl190_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	141	return 0;
	142	}
	143	}
	144
7f8293bf AK	145	static void pl190_write(void *opaque, target_phys_addr_t offset,
7f8293bf AK	146	uint64_t val, unsigned size)
cdbdb648 PB	147	{
	148	pl190_state s = (pl190_state )opaque;
	149
cdbdb648 PB	150	if (offset >= 0x100 && offset < 0x140) {
	151	s->vect_addr[(offset - 0x100) >> 2] = val;
	152	pl190_update_vectors(s);
	153	return;
	154	}
	155	if (offset >= 0x200 && offset < 0x240) {
	156	s->vect_control[(offset - 0x200) >> 2] = val;
	157	pl190_update_vectors(s);
	158	return;
	159	}
	160	switch (offset >> 2) {
	161	case 0: /* SELECT */
	162	/* This is a readonly register, but linux tries to write to it
	163	anyway. Ignore the write. */
	164	break;
	165	case 3: /* INTSELECT */
	166	s->fiq_select = val;
	167	break;
	168	case 4: /* INTENABLE */
	169	s->irq_enable \|= val;
	170	break;
	171	case 5: /* INTENCLEAR */
	172	s->irq_enable &= ~val;
	173	break;
	174	case 6: /* SOFTINT */
	175	s->soft_level \|= val;
	176	break;
	177	case 7: /* SOFTINTCLEAR */
	178	s->soft_level &= ~val;
	179	break;
	180	case 8: /* PROTECTION */
	181	/* TODO: Protection (supervisor only access) is not implemented. */
	182	s->protected = val & 1;
	183	break;
	184	case 12: /* VECTADDR */
	185	/* Restore the previous priority level. The value written is
	186	ignored. */
	187	if (s->priority < PL190_NUM_PRIO)
	188	s->priority = s->prev_prio[s->priority];
	189	break;
	190	case 13: /* DEFVECTADDR */
730986e4	191	s->vect_addr[16] = val;
cdbdb648 PB	192	break;
cdbdb648 PB	193	case 0xc0: /* ITCR */
2ac71179 PB	194	if (val) {
	195	hw_error("pl190: Test mode not implemented\n");
	196	}
cdbdb648 PB	197	break;
cdbdb648 PB	198	default:
2ac71179	199	hw_error("pl190_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	200	return;
	201	}
	202	pl190_update(s);
	203	}
	204
7f8293bf AK	205	static const MemoryRegionOps pl190_ops = {
	206	.read = pl190_read,
	207	.write = pl190_write,
	208	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	209	};
cdbdb648 PB	210
ac49d750	211	static void pl190_reset(DeviceState *d)
cdbdb648	212	{
ac49d750	213	pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
cdbdb648 PB	214	int i;
	215
	216	for (i = 0; i < 16; i++)
	217	{
	218	s->vect_addr[i] = 0;
	219	s->vect_control[i] = 0;
	220	}
	221	s->vect_addr[16] = 0;
	222	s->prio_mask[17] = 0xffffffff;
	223	s->priority = PL190_NUM_PRIO;
	224	pl190_update_vectors(s);
	225	}
	226
81a322d4	227	static int pl190_init(SysBusDevice *dev)
cdbdb648	228	{
97aff481	229	pl190_state *s = FROM_SYSBUS(pl190_state, dev);
cdbdb648	230
7f8293bf	231	memory_region_init_io(&s->iomem, &pl190_ops, s, "pl190", 0x1000);
750ecd44	232	sysbus_init_mmio(dev, &s->iomem);
067a3ddc	233	qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
97aff481 PB	234	sysbus_init_irq(dev, &s->irq);
97aff481 PB	235	sysbus_init_irq(dev, &s->fiq);
81a322d4	236	return 0;
cdbdb648	237	}
97aff481	238
ac49d750 PM	239	static const VMStateDescription vmstate_pl190 = {
	240	.name = "pl190",
	241	.version_id = 1,
	242	.minimum_version_id = 1,
	243	.fields = (VMStateField[]) {
	244	VMSTATE_UINT32(level, pl190_state),
	245	VMSTATE_UINT32(soft_level, pl190_state),
	246	VMSTATE_UINT32(irq_enable, pl190_state),
	247	VMSTATE_UINT32(fiq_select, pl190_state),
ac49d750 PM	248	VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
	249	VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
	250	VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
	251	VMSTATE_INT32(protected, pl190_state),
	252	VMSTATE_INT32(priority, pl190_state),
	253	VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
	254	VMSTATE_END_OF_LIST()
	255	}
	256	};
	257
999e12bb AL	258	static void pl190_class_init(ObjectClass klass, void data)
999e12bb AL	259	{
39bffca2	260	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	261	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	262
	263	k->init = pl190_init;
39bffca2 AL	264	dc->no_user = 1;
	265	dc->reset = pl190_reset;
	266	dc->vmsd = &vmstate_pl190;
999e12bb AL	267	}
999e12bb AL	268
39bffca2 AL	269	static TypeInfo pl190_info = {
	270	.name = "pl190",
	271	.parent = TYPE_SYS_BUS_DEVICE,
	272	.instance_size = sizeof(pl190_state),
	273	.class_init = pl190_class_init,
ac49d750 PM	274	};
ac49d750 PM	275
83f7d43a	276	static void pl190_register_types(void)
97aff481	277	{
39bffca2	278	type_register_static(&pl190_info);
97aff481 PB	279	}
97aff481 PB	280
83f7d43a	281	type_init(pl190_register_types)